diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
98 files changed, 45718 insertions, 39061 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index b7f7bfe13..c192e9ff7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -24,12 +25,12 @@ exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -59,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -87,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -109,6 +121,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -153,12 +166,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu0.tracer workload= dcache_port=system.cpu0.dcache.cpu_side @@ -174,11 +192,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu0.dcache] type=Cache @@ -187,12 +212,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -211,8 +241,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -235,9 +270,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -251,9 +291,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -647,12 +692,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -671,8 +721,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -730,9 +785,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -746,9 +806,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -759,12 +824,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -782,6 +852,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -792,6 +863,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -808,8 +883,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -817,10 +897,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -852,6 +937,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -896,12 +982,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu1.tracer workload= dcache_port=system.cpu1.dcache.cpu_side @@ -917,11 +1008,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu1.dcache] type=Cache @@ -930,12 +1028,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -954,8 +1057,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -978,9 +1086,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -994,9 +1107,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -1390,12 +1508,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -1414,8 +1537,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1473,9 +1601,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1489,9 +1622,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -1502,12 +1640,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -1525,6 +1668,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -1535,6 +1679,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -1551,8 +1699,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -1560,10 +1713,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1608,9 +1766,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1624,12 +1787,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1648,8 +1816,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1660,12 +1833,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1684,21 +1862,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1710,11 +1898,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1725,6 +1918,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -1759,6 +1959,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1770,7 +1971,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1813,10 +2018,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1897,14 +2107,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1913,13 +2128,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1929,6 +2149,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1999,10 +2220,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -2082,17 +2308,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -2118,12 +2349,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -2131,14 +2368,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2224,14 +2466,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2240,13 +2487,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2255,13 +2507,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2269,11 +2526,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2287,11 +2549,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2305,19 +2572,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -2363,14 +2636,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2379,11 +2667,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2393,21 +2686,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2417,12 +2720,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2431,10 +2739,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2444,12 +2757,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2459,26 +2777,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2487,10 +2815,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2498,10 +2831,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2509,21 +2847,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2537,11 +2885,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2552,11 +2905,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2564,10 +2922,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2583,10 +2946,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr index 99334c62c..02b3f36ba 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr @@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index fe36facf2..2149b379f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:30 -gem5 executing on phenom, pid 15961 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:42:06 +gem5 executing on e108600-lin, pid 23137 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2649116242500 because m5_exit instruction encountered +Exiting @ tick 2647778082500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 26497932e..43f49bfd8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.847227 # Number of seconds simulated -sim_ticks 2847227406000 # Number of ticks simulated -final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.647778 # Number of seconds simulated +sim_ticks 2647778082500 # Number of ticks simulated +final_tick 2647778082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166460 # Simulator instruction rate (inst/s) -host_op_rate 201569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3722516357 # Simulator tick rate (ticks/s) -host_mem_usage 624360 # Number of bytes of host memory used -host_seconds 764.87 # Real time elapsed on the host -sim_insts 127319545 # Number of instructions simulated -sim_ops 154173476 # Number of ops (including micro ops) simulated +host_inst_rate 109262 # Simulator instruction rate (inst/s) +host_op_rate 132319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2267003011 # Simulator tick rate (ticks/s) +host_mem_usage 618500 # Number of bytes of host memory used +host_seconds 1167.96 # Real time elapsed on the host +sim_insts 127613917 # Number of instructions simulated +sim_ops 154544077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 446720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1505216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1244784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8319232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 374976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 749140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 607232 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12635780 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1647744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8874176 # Number of bytes written to this memory +system.physmem.bytes_read::total 12811716 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1505216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 374976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1880192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9040448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8891740 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 117 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9058012 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130524 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 23519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 129988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 30 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9488 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197977 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138659 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200726 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141257 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 578719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 462749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2933919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 156896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4437924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 578719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 655032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3116778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3122947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3116778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 578719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 468904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2933919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 156896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7560871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197977 # Number of read requests accepted -system.physmem.writeReqs 143050 # Number of write requests accepted -system.physmem.readBursts 197977 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 143050 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12661056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 8904256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12635780 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8891740 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 145648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 568483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 470124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3141967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 141619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 229336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4838667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 568483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 141619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 710102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3414353 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6618 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3420986 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3414353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 568483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 476742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3141967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 141619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 282947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 229336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8259653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200726 # Number of read requests accepted +system.physmem.writeReqs 145648 # Number of write requests accepted +system.physmem.readBursts 200726 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145648 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12837568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 9070080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12811716 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9058012 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11990 # Per bank write bursts -system.physmem.perBankRdBursts::1 12090 # Per bank write bursts -system.physmem.perBankRdBursts::2 12710 # Per bank write bursts -system.physmem.perBankRdBursts::3 12556 # Per bank write bursts -system.physmem.perBankRdBursts::4 14859 # Per bank write bursts -system.physmem.perBankRdBursts::5 12263 # Per bank write bursts -system.physmem.perBankRdBursts::6 12121 # Per bank write bursts -system.physmem.perBankRdBursts::7 12401 # Per bank write bursts -system.physmem.perBankRdBursts::8 11839 # Per bank write bursts -system.physmem.perBankRdBursts::9 11973 # Per bank write bursts -system.physmem.perBankRdBursts::10 12288 # Per bank write bursts -system.physmem.perBankRdBursts::11 11633 # Per bank write bursts -system.physmem.perBankRdBursts::12 12418 # Per bank write bursts -system.physmem.perBankRdBursts::13 12730 # Per bank write bursts -system.physmem.perBankRdBursts::14 11938 # Per bank write bursts -system.physmem.perBankRdBursts::15 12020 # Per bank write bursts -system.physmem.perBankWrBursts::0 8637 # Per bank write bursts -system.physmem.perBankWrBursts::1 8726 # Per bank write bursts -system.physmem.perBankWrBursts::2 9304 # Per bank write bursts -system.physmem.perBankWrBursts::3 8986 # Per bank write bursts -system.physmem.perBankWrBursts::4 8078 # Per bank write bursts -system.physmem.perBankWrBursts::5 8592 # Per bank write bursts -system.physmem.perBankWrBursts::6 8645 # Per bank write bursts -system.physmem.perBankWrBursts::7 8770 # Per bank write bursts -system.physmem.perBankWrBursts::8 8363 # Per bank write bursts -system.physmem.perBankWrBursts::9 8478 # Per bank write bursts -system.physmem.perBankWrBursts::10 8927 # Per bank write bursts -system.physmem.perBankWrBursts::11 8795 # Per bank write bursts -system.physmem.perBankWrBursts::12 9084 # Per bank write bursts -system.physmem.perBankWrBursts::13 8813 # Per bank write bursts -system.physmem.perBankWrBursts::14 8578 # Per bank write bursts -system.physmem.perBankWrBursts::15 8353 # Per bank write bursts +system.physmem.perBankRdBursts::0 12684 # Per bank write bursts +system.physmem.perBankRdBursts::1 12558 # Per bank write bursts +system.physmem.perBankRdBursts::2 12677 # Per bank write bursts +system.physmem.perBankRdBursts::3 12470 # Per bank write bursts +system.physmem.perBankRdBursts::4 15173 # Per bank write bursts +system.physmem.perBankRdBursts::5 12439 # Per bank write bursts +system.physmem.perBankRdBursts::6 12705 # Per bank write bursts +system.physmem.perBankRdBursts::7 12895 # Per bank write bursts +system.physmem.perBankRdBursts::8 12483 # Per bank write bursts +system.physmem.perBankRdBursts::9 12862 # Per bank write bursts +system.physmem.perBankRdBursts::10 12103 # Per bank write bursts +system.physmem.perBankRdBursts::11 11319 # Per bank write bursts +system.physmem.perBankRdBursts::12 11938 # Per bank write bursts +system.physmem.perBankRdBursts::13 12281 # Per bank write bursts +system.physmem.perBankRdBursts::14 12069 # Per bank write bursts +system.physmem.perBankRdBursts::15 11931 # Per bank write bursts +system.physmem.perBankWrBursts::0 9144 # Per bank write bursts +system.physmem.perBankWrBursts::1 9177 # Per bank write bursts +system.physmem.perBankWrBursts::2 9224 # Per bank write bursts +system.physmem.perBankWrBursts::3 8920 # Per bank write bursts +system.physmem.perBankWrBursts::4 8442 # Per bank write bursts +system.physmem.perBankWrBursts::5 8744 # Per bank write bursts +system.physmem.perBankWrBursts::6 9263 # Per bank write bursts +system.physmem.perBankWrBursts::7 9163 # Per bank write bursts +system.physmem.perBankWrBursts::8 8908 # Per bank write bursts +system.physmem.perBankWrBursts::9 9183 # Per bank write bursts +system.physmem.perBankWrBursts::10 8711 # Per bank write bursts +system.physmem.perBankWrBursts::11 8187 # Per bank write bursts +system.physmem.perBankWrBursts::12 8717 # Per bank write bursts +system.physmem.perBankWrBursts::13 8673 # Per bank write bursts +system.physmem.perBankWrBursts::14 8851 # Per bank write bursts +system.physmem.perBankWrBursts::15 8413 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 2847226871000 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 2647777471000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 553 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 197396 # Read request sizes (log2) +system.physmem.readPktSize::6 200145 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138659 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see +system.physmem.writePktSize::6 141257 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -185,164 +185,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 145 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 233.562015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.589518 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.350425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50532 54.73% 54.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17809 19.29% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6200 6.71% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3503 3.79% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2794 3.03% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1407 1.52% 89.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 909 0.98% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 989 1.07% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8189 8.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92332 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.657830 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.171003 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6902 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7374 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 94963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.695997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 131.239554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.689609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52509 55.29% 55.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18085 19.04% 74.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6234 6.56% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3686 3.88% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2895 3.05% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1483 1.56% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 908 0.96% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1023 1.08% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8140 8.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94963 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.398839 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 555.406402 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7061 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6903 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6903 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.154860 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.644326 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.603874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5813 84.21% 84.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 373 5.40% 89.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 70 1.01% 90.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 58 0.84% 91.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 265 3.84% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.36% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 18 0.26% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 26 0.38% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.20% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.13% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 153 2.22% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.09% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 5 0.07% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.13% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7063 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7063 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.065128 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.613340 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.212436 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5945 84.17% 84.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 392 5.55% 89.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 71 1.01% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 48 0.68% 91.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 279 3.95% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 27 0.38% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.27% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.35% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 16 0.23% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.17% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 160 2.27% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.08% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6903 # Writes before turning the bus around for reads -system.physmem.totQLat 5250518808 # Total ticks spent queuing -system.physmem.totMemAccLat 8959812558 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26540.69 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7063 # Writes before turning the bus around for reads +system.physmem.totQLat 5391615341 # Total ticks spent queuing +system.physmem.totMemAccLat 9152621591 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1002935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26879.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45290.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45629.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.42 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.07 # Average write queue length when enqueuing -system.physmem.readRowHits 164412 # Number of row buffer hits during reads -system.physmem.writeRowHits 80213 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.64 # Row buffer hit rate for writes -system.physmem.avgGap 8348977.86 # Average gap between requests -system.physmem.pageHitRate 72.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 354957120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 193677000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 787722000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 451902240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83190012300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1635359290500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1906304222040 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.531375 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2720439936839 # Time in different power states -system.physmem_0.memoryStateTime::REF 95074980000 # Time in different power states +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing +system.physmem.readRowHits 166580 # Number of row buffer hits during reads +system.physmem.writeRowHits 80763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 56.97 # Row buffer hit rate for writes +system.physmem.avgGap 7644273.16 # Average gap between requests +system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 370341720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 202071375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 808080000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 467058960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79567681680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1518869897250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1773225027465 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.703351 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2526645938707 # Time in different power states +system.physmem_0.memoryStateTime::REF 88415080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31706739411 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32716967293 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 343072800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 187192500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 755336400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 449653680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82901008620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.500294 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states -system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states +system.physmem_1.actEnergy 347578560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189651000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 756490800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 451286640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78874475895 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1519477980750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1773037360125 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.632470 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2527659145749 # Time in different power states +system.physmem_1.memoryStateTime::REF 88415080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31702650501 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -352,39 +353,39 @@ system.realview.nvmem.bytes_inst_read::total 1344 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 508 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 508 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 508 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20737076 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1017313 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13202297 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8722072 # Number of BTB hits +system.cpu0.branchPred.lookups 34732065 # Number of BP lookups +system.cpu0.branchPred.condPredicted 16497595 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1496295 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 19609177 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10269070 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 52.368695 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11117365 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 739154 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4170441 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 3984607 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 185834 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 94839 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,60 +415,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 68420 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12395.971669 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11546.443771 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5803.014677 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6374 94.05% 94.05% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 345 5.09% 99.14% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.69% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6777 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 65243 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65243 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44492 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20751 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 65243 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 65243 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 65243 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6699 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12206.821914 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11332.778692 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5808.192470 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6323 94.39% 94.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 330 4.93% 99.31% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 32 0.48% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.10% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6699 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5225 77.10% 77.10% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1552 22.90% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6777 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.27% 77.27% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1523 22.73% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6699 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65243 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65243 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6699 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 71942 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17339981 # DTB read hits -system.cpu0.dtb.read_misses 61941 # DTB read misses -system.cpu0.dtb.write_hits 14540400 # DTB write hits -system.cpu0.dtb.write_misses 6479 # DTB write misses +system.cpu0.dtb.read_hits 23418517 # DTB read hits +system.cpu0.dtb.read_misses 59363 # DTB read misses +system.cpu0.dtb.write_hits 17357852 # DTB write hits +system.cpu0.dtb.write_misses 5880 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1178 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1722 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17401922 # DTB read accesses -system.cpu0.dtb.write_accesses 14546879 # DTB write accesses +system.cpu0.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23477880 # DTB read accesses +system.cpu0.dtb.write_accesses 17363732 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31880381 # DTB hits -system.cpu0.dtb.misses 68420 # DTB misses -system.cpu0.dtb.accesses 31948801 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 40776369 # DTB hits +system.cpu0.dtb.misses 65243 # DTB misses +system.cpu0.dtb.accesses 40841612 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -497,41 +499,41 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3977 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12713.811696 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12041.525578 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4752.572139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 358 14.85% 14.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1847 76.61% 91.46% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 161 6.68% 98.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 17 0.71% 98.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 4001 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4001 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3695 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4001 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4001 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4001 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2427 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12648.125258 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11968.911523 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4734.087286 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 373 15.37% 15.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1885 77.67% 93.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 118 4.86% 97.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.11% 99.01% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.91% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2427 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2112 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2126 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 301 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2427 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3977 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3977 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4001 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4001 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6388 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38606266 # ITB inst hits -system.cpu0.itb.inst_misses 3977 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2427 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2427 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6428 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 68314752 # ITB inst hits +system.cpu0.itb.inst_misses 4001 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -540,797 +542,795 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2164 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7135 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses -system.cpu0.itb.hits 38606266 # DTB hits -system.cpu0.itb.misses 3977 # DTB misses -system.cpu0.itb.accesses 38610243 # DTB accesses -system.cpu0.numPwrStateTransitions 3704 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1852 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1492233091.644168 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23940880637.068275 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1073 57.94% 57.94% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.68% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499965331660 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1852 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 83611720275 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 167224982 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 68318753 # ITB inst accesses +system.cpu0.itb.hits 68314752 # DTB hits +system.cpu0.itb.misses 4001 # DTB misses +system.cpu0.itb.accesses 68318753 # DTB accesses +system.cpu0.numPwrStateTransitions 4126 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 2063 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1227700157.144935 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 21500702795.368797 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1198 58.07% 58.07% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 860 41.69% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.05% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499984309000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 2063 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 115032658310 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2532745424190 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 230068064 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79715648 # Number of instructions committed -system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.097769 # CPI: cycles per instruction -system.cpu0.ipc 0.476697 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63730677 66.44% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92076 0.10% 66.53% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16811055 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction +system.cpu0.committedInsts 106706103 # Number of instructions committed +system.cpu0.committedOps 129024022 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8506641 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2063 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5065528558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.156091 # CPI: cycles per instruction +system.cpu0.ipc 0.463802 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2272 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 87919988 68.14% 68.14% # Class of committed instruction +system.cpu0.op_class_0::IntMult 105727 0.08% 68.23% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 7151 0.01% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::MemRead 22900542 17.75% 85.98% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 18088342 14.02% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 95927461 # Class of committed instruction +system.cpu0.op_class_0::total 129024022 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed -system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 715130 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed +system.cpu0.tickCycles 178511666 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 51556398 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 681177 # number of replacements +system.cpu0.dcache.tags.tagsinuse 487.337065 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 39381714 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 681689 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 57.770793 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.337065 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951830 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.951830 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29235144 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29235144 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29555584 # number of overall hits -system.cpu0.dcache.overall_hits::total 29555584 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 580901 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136483 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 136483 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21307 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21307 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20567 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20567 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1044624 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1044624 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1181107 # number of overall misses -system.cpu0.dcache.overall_misses::total 1181107 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6183627500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6183627500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10315375000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10315375000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 321766500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 321766500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 497952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 497952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 229500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 229500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16274055 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14005713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30279768 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30279768 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30736691 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30736691 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053890 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053890 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034499 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034499 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038427 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.038427 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13334.744017 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13334.744017 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17757.543884 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17757.543884 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15101.445534 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15101.445534 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24211.236447 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24211.236447 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81578447 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81578447 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21978387 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21978387 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16273218 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16273218 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306177 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 306177 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357355 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 357355 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352292 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 352292 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 38251605 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 38251605 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 38557782 # number of overall hits +system.cpu0.dcache.overall_hits::total 38557782 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 418335 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 418335 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 561531 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 561531 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131453 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 131453 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20802 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20802 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21460 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21460 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 979866 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 979866 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1111319 # number of overall misses +system.cpu0.dcache.overall_misses::total 1111319 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5562272000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5562272000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10028849500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10028849500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328076000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 328076000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 523772000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 523772000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 516000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 516000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 15591121500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15591121500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 15591121500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15591121500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22396722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22396722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16834749 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16834749 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437630 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 437630 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378157 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 378157 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373752 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 373752 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39231471 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39231471 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39669101 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39669101 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018678 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033355 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033355 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300375 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300375 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055009 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055009 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057418 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057418 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024977 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024977 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028015 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028015 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13296.214756 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13296.214756 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17859.832316 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17859.832316 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.368138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.368138 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24406.896552 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24406.896552 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15794.202029 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15794.202029 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13969.100598 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13969.100598 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15911.483305 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15911.483305 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14029.384452 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14029.384452 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 715130 # number of writebacks -system.cpu0.dcache.writebacks::total 715130 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 71798 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 71798 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255281 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255281 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14780 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14780 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 327079 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 327079 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 327079 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 327079 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391925 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 391925 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325620 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325620 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103078 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 103078 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6527 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6527 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20567 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20567 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 717545 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 717545 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 820623 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 820623 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4674150000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4674150000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5703236000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5703236000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1673631500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1673631500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101407500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101407500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 477391500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 477391500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10377386000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10377386000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12051017500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12051017500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4615609000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4615609000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4615609000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4615609000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024083 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024083 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225592 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225592 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016886 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016886 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053890 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053890 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023697 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023697 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026698 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026698 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11926.133827 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11926.133827 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17515.005221 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17515.005221 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16236.553872 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16236.553872 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15536.617129 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15536.617129 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23211.528176 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23211.528176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 681177 # number of writebacks +system.cpu0.dcache.writebacks::total 681177 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44450 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 44450 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 246335 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 246335 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14695 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14695 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 290785 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 290785 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 290785 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 290785 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373885 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 373885 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 315196 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 315196 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98829 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 98829 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6107 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6107 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 689081 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 689081 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 787910 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 787910 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29629 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29629 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26357 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26357 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55986 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55986 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4452451000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4452451000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5571993500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5571993500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1619437000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1619437000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94023500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94023500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 502325000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 502325000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 503000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 503000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10024444500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10024444500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11643881500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11643881500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6101487500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6101487500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6101487500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6101487500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016694 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016694 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018723 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018723 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225828 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225828 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057418 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057418 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017564 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017564 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019862 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019862 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11908.610937 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11908.610937 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17677.868691 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17677.868691 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16386.253023 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16386.253023 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15396.020960 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15396.020960 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23407.502330 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23407.502330 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1962004 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1962516 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.668158 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6612168000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774944 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14547.556093 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14547.556093 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14778.187230 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14778.187230 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205929.579129 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205929.579129 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 108982.379523 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 108982.379523 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1887196 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.757846 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 66419655 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1887708 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.185344 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6638125000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757846 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36636559 # number of overall hits -system.cpu0.icache.overall_hits::total 36636559 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1962531 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1962531 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1962531 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1962531 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1962531 # number of overall misses -system.cpu0.icache.overall_misses::total 1962531 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18757498000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18757498000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18757498000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18757498000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18757498000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18757498000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38599090 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38599090 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38599090 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38599090 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38599090 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38599090 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9557.809787 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9557.809787 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9557.809787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9557.809787 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 138502472 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 138502472 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 66419655 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 66419655 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 66419655 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 66419655 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 66419655 # number of overall hits +system.cpu0.icache.overall_hits::total 66419655 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1887721 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1887721 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1887721 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1887721 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1887721 # number of overall misses +system.cpu0.icache.overall_misses::total 1887721 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17836461000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17836461000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17836461000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17836461000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17836461000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17836461000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 68307376 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 68307376 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 68307376 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 68307376 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 68307376 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 68307376 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027636 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.027636 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027636 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.027636 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027636 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.027636 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9448.674354 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9448.674354 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9448.674354 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9448.674354 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1962004 # number of writebacks -system.cpu0.icache.writebacks::total 1962004 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1962531 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1962531 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1962531 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1962531 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1962531 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1962531 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3449 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3449 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17776233000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17776233000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17776233000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17776233000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17776233000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17776233000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 319470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9057.810042 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 1887196 # number of writebacks +system.cpu0.icache.writebacks::total 1887196 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1887721 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1887721 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1887721 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1887721 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1887721 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1887721 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3448 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3448 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3448 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3448 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16892601000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16892601000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16892601000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16892601000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16892601000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16892601000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319413000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319413000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319413000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 319413000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027636 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027636 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027636 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8948.674619 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767222 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1767306 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 74 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 298119 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 314209 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 14.902444 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 225214 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 281957 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16020.304669 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4495555 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 298080 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 15.081706 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 400 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 257 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 15153.098614 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.898882 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.073768 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 805.233405 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.924872 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049148 # 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number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41640 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41640 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 60329 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 60329 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100353 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100353 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 760 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 121 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 60329 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 141993 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2606173000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4026856993 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14000669196 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 20658930189 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 291829000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5864363500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6156192500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 291829000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5864363500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6156192500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010463 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163708 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163708 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034822 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199889 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.199889 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075686 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.161648 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161648 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.031959 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209586 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209586 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.167436 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26280.487805 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54135.843337 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19643.217143 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19643.217143 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15674.098026 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15674.098026 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 176499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 176499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39870.893725 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39870.893725 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42872.146620 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24148.579986 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24148.579986 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33389.283701 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44757.813723 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 216325.103281 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197417.852980 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88590 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43220 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114518 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288089 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284462 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1962531 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586533 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3131 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5893963 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2592135 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13195 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174334 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8673627 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251390912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99322292 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22180 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 334344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 351069728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1056913 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3897709 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.106693 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.313582 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166430 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28639.046538 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56558.077101 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19461.965107 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19461.965107 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15860.109060 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15860.109060 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 101124.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 101124.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40772.358309 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40772.358309 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43199.340284 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23209.032047 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23209.032047 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32766.548688 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45832.549870 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197926.474063 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 186117.014844 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 104746.963527 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103580.315981 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5292246 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2668157 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 40914 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 334901 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 330475 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 126809 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2542571 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 693110 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2103191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 223137 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 294264 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 92982 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43850 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 116200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 275510 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 272175 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1887721 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569608 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3113 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5669533 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2525108 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13291 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164598 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8372530 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 241815296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94996751 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22380 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 337148843 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1025467 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18711896 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3771293 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.106316 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.312026 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3487742 89.48% 89.48% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 404074 10.37% 99.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5893 0.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3374771 89.49% 89.49% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 392096 10.40% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4426 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3897709 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5501303494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3771293 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5293903990 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115667783 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114422325 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2949460514 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2837181638 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1225261932 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1188012916 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7656487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7701489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 90771952 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 86027432 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19337823 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6215951 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 910078 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9913117 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3669706 # Number of BTB hits +system.cpu1.branchPred.lookups 5469499 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3374978 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 316517 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3346860 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2136825 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 63.845664 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 972408 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 68961 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 195238 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 132437 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 62801 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 28788 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1360,64 +1360,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 26974 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11914.148858 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11049.041659 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5760.245338 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 673 24.80% 24.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1844 67.94% 92.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 118 4.35% 97.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.06% 99.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 13 0.48% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2714 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2024068032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2024068032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2024068032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.58% 73.58% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 717 26.42% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2714 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26974 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 30404 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 30404 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23807 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6597 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 30404 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 30404 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 30404 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2736 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12207.419591 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11247.456123 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8821.385005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 2714 99.20% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 14 0.51% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 4 0.15% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 3 0.11% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2736 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1954228032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1954228032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1954228032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2033 74.31% 74.31% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 703 25.69% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2736 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30404 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26974 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2714 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30404 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2736 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2714 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 29688 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2736 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 33140 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11185393 # DTB read hits -system.cpu1.dtb.read_misses 25019 # DTB read misses -system.cpu1.dtb.write_hits 6992115 # DTB write hits -system.cpu1.dtb.write_misses 1955 # DTB write misses +system.cpu1.dtb.read_hits 5173966 # DTB read hits +system.cpu1.dtb.read_misses 27871 # DTB read misses +system.cpu1.dtb.write_hits 4222414 # DTB write hits +system.cpu1.dtb.write_misses 2533 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 306 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 555 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11210412 # DTB read accesses -system.cpu1.dtb.write_accesses 6994070 # DTB write accesses +system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5201837 # DTB read accesses +system.cpu1.dtb.write_accesses 4224947 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18177508 # DTB hits -system.cpu1.dtb.misses 26974 # DTB misses -system.cpu1.dtb.accesses 18204482 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 9396380 # DTB hits +system.cpu1.dtb.misses 30404 # DTB misses +system.cpu1.dtb.accesses 9426784 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1447,46 +1442,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2420 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12165.931156 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11504.985007 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4742.932714 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 196 17.30% 17.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 640 56.49% 73.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 219 19.33% 93.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 41 3.62% 96.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.32% 98.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.71% 98.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.26% 99.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.44% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1133 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2024645532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2024645532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2024645532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 964 85.08% 85.08% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 169 14.92% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1133 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2488 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2488 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2306 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2488 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2488 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2488 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1135 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12427.312775 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11760.899210 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5007.072010 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 4 0.35% 0.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 156 13.74% 14.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 686 60.44% 74.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 210 18.50% 93.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 30 2.64% 95.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.85% 97.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.70% 98.41% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 15 1.32% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.26% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1135 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1954817532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1954817532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1954817532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 965 85.02% 85.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1135 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2420 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2420 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2488 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2488 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1133 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1133 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3553 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39602800 # ITB inst hits -system.cpu1.itb.inst_misses 2420 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3623 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10174079 # ITB inst hits +system.cpu1.itb.inst_misses 2488 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1495,769 +1488,778 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1102 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1107 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1891 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses -system.cpu1.itb.hits 39602800 # DTB hits -system.cpu1.itb.misses 2420 # DTB misses -system.cpu1.itb.accesses 39605220 # DTB accesses -system.cpu1.numPwrStateTransitions 5553 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2777 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1004505001.039251 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25654466824.490025 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1974 71.08% 71.08% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.77% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949981296504 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2777 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 57717018114 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 115435582 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10176567 # ITB inst accesses +system.cpu1.itb.hits 10174079 # DTB hits +system.cpu1.itb.misses 2488 # DTB misses +system.cpu1.itb.accesses 10176567 # DTB accesses +system.cpu1.numPwrStateTransitions 5445 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2723 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 962192053.212266 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 19383110303.670654 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1861 68.34% 68.34% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 855 31.40% 99.74% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 4 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 499966911836 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2723 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 27729121603 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2620048960897 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 55461727 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 47603897 # Number of instructions committed -system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.424919 # CPI: cycles per instruction -system.cpu1.ipc 0.412385 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40076529 68.81% 68.81% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45752 0.08% 68.88% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3347 0.01% 68.89% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.89% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.89% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.89% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11012402 18.91% 87.80% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction +system.cpu1.committedInsts 20907814 # Number of instructions committed +system.cpu1.committedOps 25520055 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1855956 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2723 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5239453402 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.652679 # CPI: cycles per instruction +system.cpu1.ipc 0.376977 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 67 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 16137166 63.23% 63.23% # Class of committed instruction +system.cpu1.op_class_0::IntMult 34169 0.13% 63.37% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 4083 0.02% 63.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 63.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 63.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 63.38% # Class of committed instruction +system.cpu1.op_class_0::MemRead 4989153 19.55% 82.93% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 4355417 17.07% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 58246015 # Class of committed instruction +system.cpu1.op_class_0::total 25520055 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed -system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 196286 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 196629 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.206907 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91177108000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.109798 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6704752 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50350 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50350 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80171 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80171 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71533 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71533 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17499828 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17499828 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17550178 # number of overall hits -system.cpu1.dcache.overall_hits::total 17550178 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 159722 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 159722 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145538 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145538 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31004 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 31004 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23795 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23795 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 305260 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 305260 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 336264 # number of overall misses -system.cpu1.dcache.overall_misses::total 336264 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2429598500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2429598500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3913148500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3913148500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317482500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 317482500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 583924500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 583924500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 387500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 387500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6342747000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6342747000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6342747000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6342747000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10954798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10954798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6850290 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6850290 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81354 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81354 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95328 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95328 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17805088 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17805088 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17886442 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17886442 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014580 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.014580 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021246 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021246 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381100 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381100 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174610 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174610 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249612 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249612 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017145 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.017145 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018800 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018800 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15211.420468 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15211.420468 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26887.469252 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26887.469252 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18719.487028 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18719.487028 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24539.798277 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24539.798277 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2723 # number of quiesce instructions executed +system.cpu1.tickCycles 37036327 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 18425400 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 231690 # number of replacements +system.cpu1.dcache.tags.tagsinuse 479.724430 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8932333 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 232024 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.497453 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 109862994000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.724430 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.936962 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.936962 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18884551 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18884551 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 4750067 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4750067 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3901959 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3901959 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65733 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 65733 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87399 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87399 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79392 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79392 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8652026 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8652026 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8717759 # number of overall hits +system.cpu1.dcache.overall_hits::total 8717759 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 172325 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 172325 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 169730 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 169730 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34831 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 34831 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17668 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17668 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23402 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23402 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 342055 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 342055 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 376886 # number of overall misses +system.cpu1.dcache.overall_misses::total 376886 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2622225500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2622225500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4369952500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4369952500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 333352000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 333352000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 570866500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 570866500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 547000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 547000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6992178000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6992178000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6992178000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6992178000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4922392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4922392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4071689 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4071689 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100564 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 100564 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105067 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105067 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102794 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 102794 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8994081 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8994081 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 9094645 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 9094645 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035008 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035008 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041685 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.041685 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346357 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346357 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.168159 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.168159 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227659 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227659 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038031 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038031 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041440 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041440 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15216.744523 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15216.744523 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25746.494432 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25746.494432 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18867.557165 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18867.557165 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24393.919323 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24393.919323 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20778.179257 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20778.179257 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18862.402755 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18862.402755 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20441.677508 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20441.677508 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18552.501287 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18552.501287 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 196286 # number of writebacks -system.cpu1.dcache.writebacks::total 196286 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16292 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16292 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52982 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52982 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12069 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12069 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 69274 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 69274 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 69274 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 69274 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143430 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 143430 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92556 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92556 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30096 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 30096 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23795 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23795 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 235986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 235986 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 266082 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 266082 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11758 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26182 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2041290000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2041290000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2380409500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2380409500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 535271500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 535271500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82814000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82814000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 560137500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 560137500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 379500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 379500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4421699500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4421699500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4956971000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4956971000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2479783500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2479783500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2479783500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2479783500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013093 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013093 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013511 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013511 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369939 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369939 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050355 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013254 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013254 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014876 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014876 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14231.959841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14231.959841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25718.586585 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25718.586585 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17785.469830 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17785.469830 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16931.915764 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16931.915764 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23540.134482 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23540.134482 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 231690 # number of writebacks +system.cpu1.dcache.writebacks::total 231690 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 6182 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 6182 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 63208 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 63208 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12205 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12205 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 69390 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 69390 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 69390 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 69390 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166143 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166143 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106522 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106522 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33373 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 33373 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5463 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5463 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23402 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23402 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 306038 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 306038 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5399 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5399 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4698 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4698 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10097 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2348457500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2348457500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2649909000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2649909000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 556338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 556338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95279500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95279500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 547474500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 547474500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 537000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 537000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4998366500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4998366500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5554705000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5554705000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 994956000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 994956000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 994956000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 994956000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033752 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033752 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026162 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331858 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331858 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051995 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051995 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227659 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227659 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030316 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030316 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033650 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033650 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14135.157665 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14135.157665 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24876.635812 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24876.635812 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16670.317322 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16670.317322 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17440.874977 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17440.874977 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23394.346637 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23394.346637 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 946364 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18331.529533 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18331.529533 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18150.376751 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18150.376751 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184285.238007 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184285.238007 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 98539.764286 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 98539.764286 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 1038587 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.233977 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9132995 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 1039099 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.789341 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72888333000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.233977 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973113 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973113 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38654025 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38654025 # number of overall hits -system.cpu1.icache.overall_hits::total 38654025 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 946876 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 946876 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 946876 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 946876 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 946876 # number of overall misses -system.cpu1.icache.overall_misses::total 946876 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8324695000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8324695000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8324695000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8324695000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8324695000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8324695000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39600901 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39600901 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39600901 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39600901 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39600901 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39600901 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023910 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023910 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023910 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023910 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023910 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023910 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8791.747811 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8791.747811 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8791.747811 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8791.747811 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21383287 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21383287 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 9132995 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9132995 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9132995 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9132995 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9132995 # number of overall hits +system.cpu1.icache.overall_hits::total 9132995 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 1039099 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 1039099 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 1039099 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 1039099 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 1039099 # number of overall misses +system.cpu1.icache.overall_misses::total 1039099 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9377315500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9377315500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9377315500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9377315500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9377315500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9377315500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10172094 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10172094 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10172094 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10172094 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10172094 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10172094 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9024.467832 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 946364 # number of writebacks -system.cpu1.icache.writebacks::total 946364 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 946876 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 946876 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 946876 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 946876 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 946876 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 946876 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 1038587 # number of writebacks +system.cpu1.icache.writebacks::total 1038587 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039099 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 1039099 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039099 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 1039099 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039099 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 1039099 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7851257000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7851257000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7851257000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7851257000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7851257000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7851257000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10474500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10474500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10474500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10474500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023910 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023910 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023910 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8291.747811 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857766000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857766000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857766000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8857766000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857766000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8857766000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10704000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10704000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10704000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10704000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.102152 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.102152 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.102152 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8524.467832 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95571.428571 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95571.428571 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 276399 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 276459 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 53 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 53638 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 69493 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 70219 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15563.656432 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 2283330 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 85023 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 26.855439 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 39.116539 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.045474 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 428.691662 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.904332 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002387 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026165 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.933009 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 907 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13776 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 323 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 581 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5681 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7813 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055359 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 33211 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 117792 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 117792 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 1004693 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 1004693 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2364337500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2373916000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9578500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2364337500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2373916000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025012 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10209 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3438500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 17140500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1312457547 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 566974500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 566974500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 370291999 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 370291999 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 461000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 461000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1222094000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1222094000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 987020000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 987020000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1373517992 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1373517992 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3438500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 987020000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2595611992 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3599772492 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3438500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 987020000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2595611992 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4912230039 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9808000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 951737000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 961545000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9808000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 951737000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 961545000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025284 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548003 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548003 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.021165 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402142 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402142 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103862 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.489121 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.489121 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025623 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364724 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364724 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102366 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125170 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16289.319249 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38663.269819 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16840.104566 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16840.104566 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15989.010296 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15989.010296 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33124.908799 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33124.908799 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33723.067711 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17377.391964 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17377.391964 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24203.219649 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26664.802502 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163916.909318 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163312.878371 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74303 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42261 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86315 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69975 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67112 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 946876 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 270105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 65 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2840340 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 913098 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8024 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64559 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3826021 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121174528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30799564 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13460 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152110344 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 428107 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1655199 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.135380 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.345288 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.130971 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18234.574468 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33841.925300 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17731.251564 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17731.251564 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15823.768172 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15823.768172 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 461000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33516.002523 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33516.002523 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37071.173709 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18372.364794 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18372.364794 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25937.202726 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27663.625832 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176280.237081 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174477.408819 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 94259.383975 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 94186.012342 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2654318 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1335711 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 21986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 212975 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 211032 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1943 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 47306 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1331970 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 177822 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1135956 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 137781 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 47279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75014 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89713 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 82844 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 80563 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1039099 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 293637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3117009 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1002647 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8284 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70688 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 4198628 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 132979072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35729427 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13960 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 134748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 168857207 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 473910 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5785960 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1814338 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.136111 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.346015 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1432915 86.57% 86.57% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 220487 13.32% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1797 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1569330 86.50% 86.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 243065 13.40% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1943 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1655199 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2373087991 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1814338 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2620766990 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79906669 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87124018 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1558968196 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 456771923 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4794998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 37016968 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31003 # Transaction distribution -system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31014 # Transaction distribution +system.iobus.trans_dist::ReadResp 31014 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2266,7 +2268,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2279,17 +2281,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2302,94 +2304,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48463001 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48375000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 113500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 329000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 574000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6138000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6358000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38893000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187720844 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36462 # number of replacements +system.iocache.tags.tagsinuse 14.359878 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271405535000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.359878 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.897492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.897492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328320 # Number of tag accesses +system.iocache.tags.data_accesses 328320 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses +system.iocache.ReadReq_misses::total 256 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses -system.iocache.demand_misses::total 36467 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36467 # number of overall misses -system.iocache.overall_misses::total 36467 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31712877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31712877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4301380974 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4301380974 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4333093851 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4333093851 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4333093851 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4333093851 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36480 # number of demand (read+write) misses +system.iocache.demand_misses::total 36480 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36480 # number of overall misses +system.iocache.overall_misses::total 36480 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33042377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33042377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4307289467 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4307289467 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4340331844 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4340331844 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4340331844 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4340331844 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36480 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36480 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36480 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36480 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2398,38 +2400,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130505.666667 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130505.666667 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118743.953567 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118743.953567 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118822.328434 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118822.328434 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129071.785156 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129071.785156 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118907.063466 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118907.063466 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118978.394846 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118978.394846 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.888889 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19562877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19562877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2487893822 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2487893822 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2507456699 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2507456699 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2507456699 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2507456699 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36480 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36480 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36480 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36480 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20242377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20242377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493740476 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2493740476 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2513982853 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2513982853 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2513982853 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2513982853 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2438,588 +2440,590 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 131721 # number of replacements -system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use -system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79071.785156 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79071.785156 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68842.217204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68842.217204 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 135113 # number of replacements +system.l2c.tags.tagsinuse 63251.941629 # Cycle average of tags in use +system.l2c.tags.total_refs 475115 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 198978 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.387777 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13508.912510 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.990696 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038635 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9208.691215 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2842.970469 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33089.520800 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.769626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2121.922145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 593.095570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1670.405219 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.206130 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001144 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 14216.048080 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.910809 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7426.792759 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2102.106662 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29896.915616 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 20.238831 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3811.016358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1509.520853 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4194.357849 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.216920 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.140513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043380 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.504906 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032378 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009050 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025488 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.963124 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 27523 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 36326 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.113324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.032076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.456191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.058151 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023033 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.965148 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 27324 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 36452 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4354 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23032 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 79 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3689 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 32199 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.419968 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001205 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6440622 # Number of tag accesses -system.l2c.tags.data_accesses 6440622 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2712 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36538 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1074 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3276 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4226 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1659 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5885 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 466 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 69 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 46028 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 50195 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48669 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 136 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 26 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 16745 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 10025 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5491 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 177850 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 466 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 69 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 46028 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 54421 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 48669 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 136 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 26 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 16745 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11684 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5491 # number of demand (read+write) hits -system.l2c.demand_hits::total 183735 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 466 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 69 # number of overall hits -system.l2c.overall_hits::cpu0.inst 46028 # number of overall hits -system.l2c.overall_hits::cpu0.data 54421 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 48669 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 136 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 26 # number of overall hits -system.l2c.overall_hits::cpu1.inst 16745 # number of overall hits -system.l2c.overall_hits::cpu1.data 11684 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5491 # number of overall hits -system.l2c.overall_hits::total 183735 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9873 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3017 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12890 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.495784 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.513955 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.513955 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23958.421959 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23070.102751 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23750.504267 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25792.503347 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24699.277978 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25082.317073 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89437.214305 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73128.741306 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 82502.962494 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.223788 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.527155 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.272629 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.324798 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.536335 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.415851 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736916 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.822320 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.263918 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.014706 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.332875 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.154148 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743618 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.143541 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.216338 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.184224 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.535712 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.503521 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.263918 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014706 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.332875 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.277097 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743618 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.143541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.216338 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.451163 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.535712 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.521983 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.263918 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014706 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.332875 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.277097 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743618 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.143541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.216338 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.451163 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.535712 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.521983 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23846.000210 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23640.581395 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23782.053138 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25393.672199 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 25105.152951 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25233.502077 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89063.592717 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72413.002567 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81603.755338 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78696.563606 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82897.365532 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88189.814683 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78947.545160 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79279.651021 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88793.314688 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84623.329098 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74043.911922 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 88063.668908 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198323.110571 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145946.883087 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166295.938507 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102406.715856 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 526346 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 301567 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84623.329098 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74043.911922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88063.668908 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179924.347835 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158365.363232 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166188.791033 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 95219.849641 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84658.163265 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92079.185841 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 535318 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 308111 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38557 # Transaction distribution -system.membus.trans_dist::ReadResp 213679 # Transaction distribution -system.membus.trans_dist::WriteReq 31029 # Transaction distribution -system.membus.trans_dist::WriteResp 31029 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution -system.membus.trans_dist::CleanEvict 18543 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38585 # Transaction distribution +system.membus.trans_dist::ReadResp 215902 # Transaction distribution +system.membus.trans_dist::WriteReq 31055 # Transaction distribution +system.membus.trans_dist::WriteResp 31055 # Transaction distribution +system.membus.trans_dist::WritebackDirty 141257 # Transaction distribution +system.membus.trans_dist::CleanEvict 18818 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79128 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41795 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 39665 # Transaction distribution -system.membus.trans_dist::ReadExResp 19299 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 175122 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 40708 # Transaction distribution +system.membus.trans_dist::ReadExResp 19870 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 177317 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664223 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 786371 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 859302 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 675920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 798178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 871135 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28380 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19209376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19401896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19551584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19744330 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21720040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123861 # Total snoops (count) -system.membus.snoop_fanout::samples 438659 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011132 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.104918 # Request fanout histogram +system.membus.pkt_size::total 22062474 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126237 # Total snoops (count) +system.membus.snoopTraffic 37184 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 444815 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011558 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106883 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 433776 98.89% 98.89% # Request fanout histogram -system.membus.snoop_fanout::1 4883 1.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 439674 98.84% 98.84% # Request fanout histogram +system.membus.snoop_fanout::1 5141 1.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 438659 # Request fanout histogram -system.membus.reqLayer0.occupancy 89013499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 444815 # Request fanout histogram +system.membus.reqLayer0.occupancy 94951000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12539499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1031011447 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1149570495 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3051,76 +3055,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 157763 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51662 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51662 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 474894 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4314 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1271960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368625 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1640585 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36024040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5855360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41879400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 387762 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 889983 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.383411 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.488617 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1073312 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 580718 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 172518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20634 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1066 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38588 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 515387 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 375084 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 144219 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 115852 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44839 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 160691 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51833 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51833 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 476801 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4556 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1253209 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 392983 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1646192 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34630659 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7267527 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41898186 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 395888 # Total snoops (count) +system.toL2Bus.snoopTraffic 16395788 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 898686 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.386698 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.489423 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 549795 61.78% 61.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 339147 38.11% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1041 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 552232 61.45% 61.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 345388 38.43% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1066 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 889983 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 926156147 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 898686 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 930017339 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 361623 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 669727799 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 658710189 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 257138606 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 272587474 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal index 263610058..03b467a01 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal @@ -158,8 +158,8 @@ ata1.00: 1048320 sectors, multi 0: LBA ata1.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: Attached scsi generic sg0 type 0
+sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sda: sda1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index c7afa2620..f97cdd248 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -108,6 +121,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -152,12 +166,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu.tracer workload= dcache_port=system.cpu.dcache.cpu_side @@ -173,11 +192,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -186,13 +212,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -211,8 +241,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -235,9 +270,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -251,9 +291,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -647,13 +692,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -672,8 +721,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -731,9 +785,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -747,9 +806,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -760,13 +824,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -785,8 +853,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -794,9 +867,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -841,9 +920,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -857,13 +941,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -882,8 +970,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -891,9 +984,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -907,11 +1006,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -956,6 +1060,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -967,7 +1072,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1010,10 +1119,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1094,14 +1208,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1110,13 +1229,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1126,6 +1250,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1196,10 +1321,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1279,17 +1409,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1315,12 +1450,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1328,14 +1469,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1421,14 +1567,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1437,13 +1588,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1452,13 +1608,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1466,11 +1627,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1484,11 +1650,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1502,19 +1673,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1560,14 +1737,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1576,11 +1768,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1590,21 +1787,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1614,12 +1821,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1628,10 +1840,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1641,12 +1858,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1656,26 +1878,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1684,10 +1916,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1695,10 +1932,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1706,21 +1948,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1734,11 +1986,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1749,11 +2006,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1761,10 +2023,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr index 99a5b93a6..db3e56a1a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr @@ -2,6 +2,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout index e3f9f5729..6bd9bc23a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 12:02:21 -gem5 executing on e104799-lin, pid 1517 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:21 +gem5 executing on e108600-lin, pid 23070 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2858558607500 because m5_exit instruction encountered +Exiting @ tick 2858997339500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 12eb20a39..60905542e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858505 # Number of seconds simulated -sim_ticks 2858505242500 # Number of ticks simulated -final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858997 # Number of seconds simulated +sim_ticks 2858997339500 # Number of ticks simulated +final_tick 2858997339500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152549 # Simulator instruction rate (inst/s) -host_op_rate 184443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3896990443 # Simulator tick rate (ticks/s) -host_mem_usage 585436 # Number of bytes of host memory used -host_seconds 733.52 # Real time elapsed on the host -sim_insts 111897168 # Number of instructions simulated -sim_ops 135292215 # Number of ops (including micro ops) simulated +host_inst_rate 120078 # Simulator instruction rate (inst/s) +host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3059253370 # Simulator tick rate (ticks/s) +host_mem_usage 579060 # Number of bytes of host memory used +host_seconds 934.54 # Real time elapsed on the host +sim_insts 112217626 # Number of instructions simulated +sim_ops 135683579 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1706880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9150764 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10871852 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1705984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1705984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7955328 # Number of bytes written to this memory +system.physmem.bytes_read::total 10866732 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1706880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1706880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7954240 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7972852 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143599 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7971764 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143502 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170394 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124302 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170314 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124285 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 596810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3203413 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128666 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 597020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3200690 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3803335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2783038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2789168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2783038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3209543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3800889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2782178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6129 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2788308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2782178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3206819 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6592503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170394 # Number of read requests accepted -system.physmem.writeReqs 128683 # Number of write requests accepted -system.physmem.readBursts 170394 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10896320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 7985280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10871852 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7972852 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6589197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170314 # Number of read requests accepted +system.physmem.writeReqs 128666 # Number of write requests accepted +system.physmem.readBursts 170314 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128666 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10892160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue +system.physmem.bytesWritten 7984576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10866732 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7971764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10648 # Per bank write bursts -system.physmem.perBankRdBursts::1 11113 # Per bank write bursts -system.physmem.perBankRdBursts::2 10810 # Per bank write bursts -system.physmem.perBankRdBursts::3 10613 # Per bank write bursts -system.physmem.perBankRdBursts::4 13551 # Per bank write bursts -system.physmem.perBankRdBursts::5 10292 # Per bank write bursts -system.physmem.perBankRdBursts::6 10857 # Per bank write bursts -system.physmem.perBankRdBursts::7 10932 # Per bank write bursts -system.physmem.perBankRdBursts::8 10292 # Per bank write bursts -system.physmem.perBankRdBursts::9 10622 # Per bank write bursts -system.physmem.perBankRdBursts::10 10100 # Per bank write bursts -system.physmem.perBankRdBursts::11 9078 # Per bank write bursts -system.physmem.perBankRdBursts::12 10356 # Per bank write bursts -system.physmem.perBankRdBursts::13 10810 # Per bank write bursts -system.physmem.perBankRdBursts::14 10110 # Per bank write bursts -system.physmem.perBankRdBursts::15 10071 # Per bank write bursts -system.physmem.perBankWrBursts::0 7962 # Per bank write bursts -system.physmem.perBankWrBursts::1 8429 # Per bank write bursts -system.physmem.perBankWrBursts::2 8465 # Per bank write bursts -system.physmem.perBankWrBursts::3 8172 # Per bank write bursts -system.physmem.perBankWrBursts::4 7181 # Per bank write bursts -system.physmem.perBankWrBursts::5 7509 # Per bank write bursts -system.physmem.perBankWrBursts::6 7876 # Per bank write bursts -system.physmem.perBankWrBursts::7 8019 # Per bank write bursts -system.physmem.perBankWrBursts::8 7862 # Per bank write bursts -system.physmem.perBankWrBursts::9 8101 # Per bank write bursts -system.physmem.perBankWrBursts::10 7665 # Per bank write bursts -system.physmem.perBankWrBursts::11 6948 # Per bank write bursts -system.physmem.perBankWrBursts::12 7780 # Per bank write bursts -system.physmem.perBankWrBursts::13 8006 # Per bank write bursts -system.physmem.perBankWrBursts::14 7432 # Per bank write bursts -system.physmem.perBankWrBursts::15 7363 # Per bank write bursts +system.physmem.perBankRdBursts::0 10846 # Per bank write bursts +system.physmem.perBankRdBursts::1 10861 # Per bank write bursts +system.physmem.perBankRdBursts::2 10970 # Per bank write bursts +system.physmem.perBankRdBursts::3 10944 # Per bank write bursts +system.physmem.perBankRdBursts::4 13948 # Per bank write bursts +system.physmem.perBankRdBursts::5 10354 # Per bank write bursts +system.physmem.perBankRdBursts::6 10606 # Per bank write bursts +system.physmem.perBankRdBursts::7 10917 # Per bank write bursts +system.physmem.perBankRdBursts::8 10091 # Per bank write bursts +system.physmem.perBankRdBursts::9 10226 # Per bank write bursts +system.physmem.perBankRdBursts::10 9938 # Per bank write bursts +system.physmem.perBankRdBursts::11 9330 # Per bank write bursts +system.physmem.perBankRdBursts::12 10171 # Per bank write bursts +system.physmem.perBankRdBursts::13 10932 # Per bank write bursts +system.physmem.perBankRdBursts::14 10237 # Per bank write bursts +system.physmem.perBankRdBursts::15 9819 # Per bank write bursts +system.physmem.perBankWrBursts::0 8179 # Per bank write bursts +system.physmem.perBankWrBursts::1 8215 # Per bank write bursts +system.physmem.perBankWrBursts::2 8623 # Per bank write bursts +system.physmem.perBankWrBursts::3 8456 # Per bank write bursts +system.physmem.perBankWrBursts::4 7543 # Per bank write bursts +system.physmem.perBankWrBursts::5 7549 # Per bank write bursts +system.physmem.perBankWrBursts::6 7648 # Per bank write bursts +system.physmem.perBankWrBursts::7 8016 # Per bank write bursts +system.physmem.perBankWrBursts::8 7706 # Per bank write bursts +system.physmem.perBankWrBursts::9 7733 # Per bank write bursts +system.physmem.perBankWrBursts::10 7506 # Per bank write bursts +system.physmem.perBankWrBursts::11 7211 # Per bank write bursts +system.physmem.perBankWrBursts::12 7604 # Per bank write bursts +system.physmem.perBankWrBursts::13 8124 # Per bank write bursts +system.physmem.perBankWrBursts::14 7522 # Per bank write bursts +system.physmem.perBankWrBursts::15 7124 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2858504798000 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 2858996896000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169837 # Read request sizes (log2) +system.physmem.readPktSize::6 169757 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124302 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124285 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -160,115 +160,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.217495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.591879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.526171 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22578 36.74% 36.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14767 24.03% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6693 10.89% 71.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3646 5.93% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2555 4.16% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2031 3.30% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1005 1.64% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1119 1.82% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7065 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61459 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6091 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.951896 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 574.936120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6090 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.126397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.384465 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.388642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22560 36.59% 36.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14992 24.31% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6700 10.87% 71.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3651 5.92% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2898 4.70% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1667 2.70% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1045 1.69% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1093 1.77% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7057 11.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61663 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6083 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.977314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 575.322656 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6082 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6091 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6090 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.486535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.508732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.308920 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5400 88.67% 88.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 109 1.79% 90.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.53% 90.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 43 0.71% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 35 0.57% 92.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 14 0.23% 92.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 47 0.77% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.25% 93.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 145 2.38% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.23% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 63 1.03% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.15% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.44% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 95 1.56% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6090 # Writes before turning the bus around for reads -system.physmem.totQLat 1821948750 # Total ticks spent queuing -system.physmem.totMemAccLat 5014230000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 851275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10701.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6083 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6083 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.509453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.487861 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.653648 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5420 89.10% 89.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 1.48% 90.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.64% 91.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 27 0.44% 91.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 35 0.58% 92.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 16 0.26% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.67% 93.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 151 2.48% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.10% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.13% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.21% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 69 1.13% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 36 0.59% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 90 1.48% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.16% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6083 # Writes before turning the bus around for reads +system.physmem.totQLat 1877618250 # Total ticks spent queuing +system.physmem.totMemAccLat 5068680750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850950000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11032.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29451.29 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29782.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -277,43 +277,43 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.82 # Average write queue length when enqueuing -system.physmem.readRowHits 139699 # Number of row buffer hits during reads -system.physmem.writeRowHits 93863 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.79 # Average write queue length when enqueuing +system.physmem.readRowHits 139443 # Number of row buffer hits during reads +system.physmem.writeRowHits 93842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes -system.physmem.avgGap 9557755.35 # Average gap between requests -system.physmem.pageHitRate 79.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240408000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131175000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 692764800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 412173360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86549850225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1639181430000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1913911365705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.550023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726766742000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95451720000 # Time in different power states +system.physmem.avgGap 9562502.16 # Average gap between requests +system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 244104840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133192125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 697678800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 416203920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86851227465 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1639211384250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1914289395000 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.567370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726812979000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95468100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36286757000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36713387250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224214480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122339250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 635216400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 396290880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85109194890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640445162750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913635982970 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.453685 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2728879759500 # Time in different power states -system.physmem_1.memoryStateTime::REF 95451720000 # Time in different power states +system.physmem_1.actEnergy 222067440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121167750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 629795400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 392234400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85246386480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640619139500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913966394570 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.454393 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2729170897750 # Time in different power states +system.physmem_1.memoryStateTime::REF 95468100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34358196250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -326,30 +326,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 30988279 # Number of BP lookups -system.cpu.branchPred.condPredicted 16810499 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2467893 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18543680 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10372624 # Number of BTB hits +system.cpu.branchPred.lookups 31086887 # Number of BP lookups +system.cpu.branchPred.condPredicted 16880230 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2489626 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18671153 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10424859 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.936168 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7863209 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1506080 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3044381 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2857246 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 55.834040 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7822517 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1524102 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3081262 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2891722 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 189540 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 109414 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,57 +379,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 66151 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22641 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66151 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66151 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66151 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7866 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12681.604373 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10478.068683 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8425.510925 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7859 99.91% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 67741 # Table walker walks requested +system.cpu.dtb.walker.walksShort 67741 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 45017 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22724 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 67741 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 67741 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 67741 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7842 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12675.784239 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10493.995103 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8407.754568 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7835 99.91% 99.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7866 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6508 82.74% 82.74% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1358 17.26% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7866 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66151 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 7842 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 517795000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 517795000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 517795000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6453 82.29% 82.29% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1389 17.71% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7842 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67741 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66151 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7866 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7842 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7842 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 75583 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24710833 # DTB read hits -system.cpu.dtb.read_misses 59358 # DTB read misses -system.cpu.dtb.write_hits 19424404 # DTB write hits -system.cpu.dtb.write_misses 6793 # DTB write misses +system.cpu.dtb.read_hits 24787454 # DTB read hits +system.cpu.dtb.read_misses 60877 # DTB read misses +system.cpu.dtb.write_hits 19460962 # DTB write hits +system.cpu.dtb.write_misses 6864 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4286 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4270 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1793 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24770191 # DTB read accesses -system.cpu.dtb.write_accesses 19431197 # DTB write accesses +system.cpu.dtb.perms_faults 741 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24848331 # DTB read accesses +system.cpu.dtb.write_accesses 19467826 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44135237 # DTB hits -system.cpu.dtb.misses 66151 # DTB misses -system.cpu.dtb.accesses 44201388 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44248416 # DTB hits +system.cpu.dtb.misses 67741 # DTB misses +system.cpu.dtb.accesses 44316157 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -459,37 +459,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 5761 # Table walker walks requested -system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5434 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5761 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5761 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5761 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3206 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12829.694323 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10737.941546 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7417.860411 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2464 76.86% 76.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 741 23.11% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 5895 # Table walker walks requested +system.cpu.itb.walker.walksShort 5895 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5574 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5895 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5895 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5895 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3205 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12907.644306 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10876.938214 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7322.763550 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2473 77.16% 77.16% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 731 22.81% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3206 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2896 90.33% 90.33% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.67% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3206 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 3205 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 517140500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 517140500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 517140500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2896 90.36% 90.36% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.64% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3205 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5761 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5761 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5895 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5895 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3206 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3206 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8967 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57333922 # ITB inst hits -system.cpu.itb.inst_misses 5761 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3205 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3205 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 9100 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57517109 # ITB inst hits +system.cpu.itb.inst_misses 5895 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -498,727 +498,728 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2928 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2926 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8405 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57339683 # ITB inst accesses -system.cpu.itb.hits 57333922 # DTB hits -system.cpu.itb.misses 5761 # DTB misses -system.cpu.itb.accesses 57339683 # DTB accesses -system.cpu.numPwrStateTransitions 6066 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887601126.287174 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17445279478.153702 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 57523004 # ITB inst accesses +system.cpu.itb.hits 57517109 # DTB hits +system.cpu.itb.misses 5895 # DTB misses +system.cpu.itb.accesses 57523004 # DTB accesses +system.cpu.numPwrStateTransitions 6068 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3034 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887205873.057680 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17434832353.062756 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2969 97.86% 97.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.94% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499966497156 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 166411026471 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2692094216029 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 332822103 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499967463084 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3034 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 167214720643 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2691782618857 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 334432391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111897168 # Number of instructions committed -system.cpu.committedOps 135292215 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7734017 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5384249089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.974357 # CPI: cycles per instruction -system.cpu.ipc 0.336207 # IPC: instructions per cycle +system.cpu.committedInsts 112217626 # Number of instructions committed +system.cpu.committedOps 135683579 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7838903 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5383627132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.980213 # CPI: cycles per instruction +system.cpu.ipc 0.335547 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 90691008 67.03% 67.04% # Class of committed instruction -system.cpu.op_class_0::IntMult 113025 0.08% 67.12% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 8533 0.01% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::MemRead 24225299 17.91% 85.03% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20252013 14.97% 100.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90974393 67.05% 67.05% # Class of committed instruction +system.cpu.op_class_0::IntMult 113069 0.08% 67.13% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8525 0.01% 67.14% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.14% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.14% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.14% # Class of committed instruction +system.cpu.op_class_0::MemRead 24296976 17.91% 85.05% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20288279 14.95% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 135292215 # Class of committed instruction +system.cpu.op_class_0::total 135683579 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked -system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 842468 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed +system.cpu.tickCycles 218593350 # Number of cycles that the object actually ticked +system.cpu.idleCycles 115839041 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 844257 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.899744 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42705909 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 844769 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.553357 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.899744 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18262413 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41278668 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41278668 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41634970 # number of overall hits -system.cpu.dcache.overall_hits::total 41634970 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 493842 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547981 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547981 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169870 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169870 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22311 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176476854 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176476854 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23143905 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23143905 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18298058 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18298058 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356964 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356964 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443845 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443845 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460247 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460247 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41441963 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41441963 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41798927 # number of overall hits +system.cpu.dcache.overall_hits::total 41798927 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 464900 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 464900 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548479 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548479 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169396 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169396 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22217 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22217 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1041823 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1041823 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1211693 # number of overall misses -system.cpu.dcache.overall_misses::total 1211693 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8047572500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8047572500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35605363979 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35605363979 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292635500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 292635500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1013379 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1013379 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1182775 # number of overall misses +system.cpu.dcache.overall_misses::total 1182775 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7474682000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7474682000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35725670480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35725670480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 298069500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 298069500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43652936479 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43652936479 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43652936479 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43652936479 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23510097 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23510097 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18810394 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18810394 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526172 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460207 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42320491 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42320491 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42846663 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42846663 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029132 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322841 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.322841 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047876 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 43200352480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43200352480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43200352480 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43200352480 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23608805 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23608805 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18846537 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18846537 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526360 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526360 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466062 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466062 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460249 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460249 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42455342 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42455342 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42981702 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42981702 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019692 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.019692 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029102 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029102 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321825 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.321825 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047670 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047670 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024617 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024617 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028280 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028280 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16295.844622 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16295.844622 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64975.544734 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64975.544734 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13116.198288 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13116.198288 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023869 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023869 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027518 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027518 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16078.042590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16078.042590 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65135.894866 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65135.894866 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13416.280326 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13416.280326 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41900.530588 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41900.530588 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36026.399822 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36026.399822 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42630.005635 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42630.005635 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36524.573549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36524.573549 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.304348 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.681818 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 699681 # number of writebacks -system.cpu.dcache.writebacks::total 699681 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76216 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76216 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249477 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14071 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14071 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325693 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325693 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325693 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325693 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417626 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417626 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298504 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298504 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121419 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121419 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8240 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8240 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 701092 # number of writebacks +system.cpu.dcache.writebacks::total 701092 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45747 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45747 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249493 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249493 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13970 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 13970 # 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LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8247 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 716130 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 716130 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 837549 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 837549 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6547764500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6547764500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19179621500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19179621500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1710969500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1710969500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 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overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6559792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6559792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19260233000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19260233000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1701865000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1701865000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115452000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115452000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25727386000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25727386000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27438355500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27438355500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277881000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277881000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6277881000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6277881000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017764 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017764 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015869 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230759 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230759 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017682 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017682 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25820025500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25820025500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27521890500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27521890500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6298878000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6298878000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6298878000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6298878000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017754 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017754 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230261 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230261 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017695 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017695 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016922 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016922 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019548 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019548 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.536537 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.536537 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64252.477354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64252.477354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.447796 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.447796 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13885.436893 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13885.436893 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019528 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019528 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15650.114636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15650.114636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64418.511235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64418.511235 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14041.790429 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14041.790429 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13999.272463 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13999.272463 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2894371 # number of replacements -system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2894883 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.802260 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18407091500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.208818 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35954.077832 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35954.077832 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32789.957931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32789.957931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202341.085769 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202341.085769 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107280.682631 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107280.682631 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2894242 # number of replacements +system.cpu.icache.tags.tagsinuse 511.201941 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54613603 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2894754 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.866406 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18510731500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.201941 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998441 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54430342 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54430342 # number of overall hits -system.cpu.icache.overall_hits::total 54430342 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2894895 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2894895 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2894895 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2894895 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2894895 # number of overall misses -system.cpu.icache.overall_misses::total 2894895 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40452971500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40452971500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40452971500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40452971500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40452971500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40452971500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57325237 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57325237 # number of ReadReq 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0.171748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044036 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044036 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130425.196850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.614260 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.614260 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118139.858244 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118139.858244 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120589.285714 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120589.285714 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122700.989682 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122700.989682 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118834.485210 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118834.485210 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120722.462156 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120722.462156 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122110.166527 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122110.166527 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189838.580148 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181628.869525 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100651.888817 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101432.129594 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 7509695 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770160 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58111 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 594 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 594 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 823992 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2894371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2778 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 136822 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3580395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 825389 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2894242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2784 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 547514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894766 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 548829 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2651684 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16008 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160884 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11520232 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370751872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98928925 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19252 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 469988417 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192705 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4072528 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021538 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145168 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691264 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2657074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 164402 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11529080 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370735360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99133929 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 295748 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 470184521 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192671 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 8062744 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 4076067 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021486 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.144999 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3984815 97.85% 97.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 87713 2.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3988487 97.85% 97.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 87580 2.15% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4072528 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7427836500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4076067 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7431755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4348460548 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4348377811 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1310984681 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1313662211 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 11196996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11470497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 90488952 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1269,66 +1270,66 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46452000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46348000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 104000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 107000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 330500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 85500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 623500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 51000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6139500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6076000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34107000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38906500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187147502 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187130005 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.038429 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 274806935000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.037066 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064817 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064817 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 275018797000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.038429 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064902 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064902 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1337,14 +1338,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4578036502 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4578036502 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4578036502 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4578036502 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4548884128 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4548884128 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4577939005 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4577939005 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4577939005 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4577939005 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1361,14 +1362,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125570.149268 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125570.149268 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125576.527385 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125576.527385 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125567.475040 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125567.475040 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1385,14 +1386,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2753710997 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2753710997 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2753710997 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2753710997 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736261614 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2736261614 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2753616491 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2753616491 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2753616491 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2753616491 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1401,83 +1402,84 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34891 # Transaction distribution -system.membus.trans_dist::ReadResp 72400 # Transaction distribution -system.membus.trans_dist::WriteReq 27583 # Transaction distribution -system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution -system.membus.trans_dist::CleanEvict 8612 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75537.257454 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75537.257454 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 34888 # Transaction distribution +system.membus.trans_dist::ReadResp 72464 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124285 # Transaction distribution +system.membus.trans_dist::CleanEvict 8552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4603 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129077 # Transaction distribution -system.membus.trans_dist::ReadExResp 129077 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37509 # Transaction distribution +system.membus.trans_dist::ReadExReq 128933 # Transaction distribution +system.membus.trans_dist::ReadExResp 128933 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37576 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450661 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558229 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 631337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 631126 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16527584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16691357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16521376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685161 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19008477 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 402790 # Request fanout histogram +system.membus.pkt_size::total 19002281 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 504 # Total snoops (count) +system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 402659 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402790 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402659 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402790 # Request fanout histogram -system.membus.reqLayer0.occupancy 87987000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402659 # Request fanout histogram +system.membus.reqLayer0.occupancy 92669500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1702000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1708000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 879699870 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 910164615 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 990225250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 990045000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1509,28 +1511,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index cf4e1ea1a..d68fc6b82 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -124,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -162,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -217,6 +232,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -235,6 +251,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -265,9 +285,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker [system.cpu.checker.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.dtb] @@ -281,9 +306,14 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[5] @@ -337,9 +367,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker [system.cpu.checker.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.itb] @@ -353,9 +388,14 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[4] @@ -370,12 +410,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -394,8 +439,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -418,9 +468,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -434,9 +489,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -712,12 +772,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -736,8 +801,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -795,9 +865,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -811,9 +886,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -824,12 +904,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -848,8 +933,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -857,10 +947,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -905,9 +1000,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -921,12 +1021,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -945,8 +1050,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -954,10 +1064,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -971,11 +1086,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1020,6 +1140,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1031,7 +1152,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1074,10 +1199,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1158,14 +1288,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1174,13 +1309,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1261,10 +1401,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1344,17 +1489,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1380,13 +1530,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1394,14 +1549,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1487,14 +1647,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1503,13 +1668,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1518,13 +1688,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1532,11 +1707,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1550,11 +1730,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1568,12 +1753,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -1641,10 +1831,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1653,11 +1848,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1667,21 +1867,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1691,12 +1901,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1705,10 +1920,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1718,12 +1938,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1733,26 +1958,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1761,10 +1996,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1772,10 +2012,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1783,21 +2028,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1811,11 +2066,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1826,11 +2086,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1838,10 +2103,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 6cbcdcc79..d158de479 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for miscreg ACTLR @@ -42,6 +44,5 @@ warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr warn: Ignoring write to miscreg pmcr -warn: 409343110000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000 warn: instruction 'mcr dcisw' unimplemented warn: instruction 'mcr bpiall' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 87c07a72a..b3e3131fa 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:31 -gem5 executing on phenom, pid 15958 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:23 +gem5 executing on e108600-lin, pid 23084 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -44,4 +44,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2832862976500 because m5_exit instruction encountered +Exiting @ tick 2832894126500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 6bd1b06da..a853a2952 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832863 # Number of seconds simulated -sim_ticks 2832862976500 # Number of ticks simulated -final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832894 # Number of seconds simulated +sim_ticks 2832894126500 # Number of ticks simulated +final_tick 2832894126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69451 # Simulator instruction rate (inst/s) -host_op_rate 84238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1739551926 # Simulator tick rate (ticks/s) -host_mem_usage 585172 # Number of bytes of host memory used -host_seconds 1628.50 # Real time elapsed on the host -sim_insts 113100501 # Number of instructions simulated -sim_ops 137180951 # Number of ops (including micro ops) simulated +host_inst_rate 55098 # Simulator instruction rate (inst/s) +host_op_rate 66829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1379949547 # Simulator tick rate (ticks/s) +host_mem_usage 579316 # Number of bytes of host memory used +host_seconds 2052.90 # Real time elapsed on the host +sim_insts 113111333 # Number of instructions simulated +sim_ops 137193850 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1321536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9400296 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8026368 # Number of bytes written to this memory +system.physmem.bytes_read::total 10724584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1321536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1321536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8031104 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8043892 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22878 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147146 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8048628 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147400 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 125412 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170339 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 125486 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129793 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 466095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3312564 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129867 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 466497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3318266 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3779563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 466095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2833306 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3785734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 466497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2834947 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2839492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2833306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 466095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3318750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2841133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2834947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 466497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3324452 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6619055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170065 # Number of read requests accepted -system.physmem.writeReqs 129793 # Number of write requests accepted -system.physmem.readBursts 170065 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129793 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10875840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 8056896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10707048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8043892 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6626867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170340 # Number of read requests accepted +system.physmem.writeReqs 129867 # Number of write requests accepted +system.physmem.readBursts 170340 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129867 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10892352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 8061056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10724648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8048628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11272 # Per bank write bursts -system.physmem.perBankRdBursts::1 10588 # Per bank write bursts -system.physmem.perBankRdBursts::2 10986 # Per bank write bursts -system.physmem.perBankRdBursts::3 11169 # Per bank write bursts -system.physmem.perBankRdBursts::4 12952 # Per bank write bursts -system.physmem.perBankRdBursts::5 9956 # Per bank write bursts -system.physmem.perBankRdBursts::6 10481 # Per bank write bursts -system.physmem.perBankRdBursts::7 10743 # Per bank write bursts -system.physmem.perBankRdBursts::8 10600 # Per bank write bursts -system.physmem.perBankRdBursts::9 10174 # Per bank write bursts -system.physmem.perBankRdBursts::10 10343 # Per bank write bursts -system.physmem.perBankRdBursts::11 9301 # Per bank write bursts -system.physmem.perBankRdBursts::12 10025 # Per bank write bursts -system.physmem.perBankRdBursts::13 11028 # Per bank write bursts -system.physmem.perBankRdBursts::14 10189 # Per bank write bursts -system.physmem.perBankRdBursts::15 10128 # Per bank write bursts -system.physmem.perBankWrBursts::0 8502 # Per bank write bursts -system.physmem.perBankWrBursts::1 7941 # Per bank write bursts -system.physmem.perBankWrBursts::2 8563 # Per bank write bursts -system.physmem.perBankWrBursts::3 8669 # Per bank write bursts -system.physmem.perBankWrBursts::4 7608 # Per bank write bursts -system.physmem.perBankWrBursts::5 7365 # Per bank write bursts -system.physmem.perBankWrBursts::6 7699 # Per bank write bursts -system.physmem.perBankWrBursts::7 7999 # Per bank write bursts -system.physmem.perBankWrBursts::8 7959 # Per bank write bursts -system.physmem.perBankWrBursts::9 7673 # Per bank write bursts -system.physmem.perBankWrBursts::10 7751 # Per bank write bursts -system.physmem.perBankWrBursts::11 6981 # Per bank write bursts -system.physmem.perBankWrBursts::12 7672 # Per bank write bursts -system.physmem.perBankWrBursts::13 8384 # Per bank write bursts -system.physmem.perBankWrBursts::14 7646 # Per bank write bursts -system.physmem.perBankWrBursts::15 7477 # Per bank write bursts +system.physmem.perBankRdBursts::0 11036 # Per bank write bursts +system.physmem.perBankRdBursts::1 10507 # Per bank write bursts +system.physmem.perBankRdBursts::2 10862 # Per bank write bursts +system.physmem.perBankRdBursts::3 11068 # Per bank write bursts +system.physmem.perBankRdBursts::4 13101 # Per bank write bursts +system.physmem.perBankRdBursts::5 10327 # Per bank write bursts +system.physmem.perBankRdBursts::6 10639 # Per bank write bursts +system.physmem.perBankRdBursts::7 10985 # Per bank write bursts +system.physmem.perBankRdBursts::8 10460 # Per bank write bursts +system.physmem.perBankRdBursts::9 10167 # Per bank write bursts +system.physmem.perBankRdBursts::10 10435 # Per bank write bursts +system.physmem.perBankRdBursts::11 9511 # Per bank write bursts +system.physmem.perBankRdBursts::12 9930 # Per bank write bursts +system.physmem.perBankRdBursts::13 10756 # Per bank write bursts +system.physmem.perBankRdBursts::14 10401 # Per bank write bursts +system.physmem.perBankRdBursts::15 10008 # Per bank write bursts +system.physmem.perBankWrBursts::0 8291 # Per bank write bursts +system.physmem.perBankWrBursts::1 7865 # Per bank write bursts +system.physmem.perBankWrBursts::2 8399 # Per bank write bursts +system.physmem.perBankWrBursts::3 8558 # Per bank write bursts +system.physmem.perBankWrBursts::4 7751 # Per bank write bursts +system.physmem.perBankWrBursts::5 7713 # Per bank write bursts +system.physmem.perBankWrBursts::6 7781 # Per bank write bursts +system.physmem.perBankWrBursts::7 8111 # Per bank write bursts +system.physmem.perBankWrBursts::8 7871 # Per bank write bursts +system.physmem.perBankWrBursts::9 7662 # Per bank write bursts +system.physmem.perBankWrBursts::10 7844 # Per bank write bursts +system.physmem.perBankWrBursts::11 7196 # Per bank write bursts +system.physmem.perBankWrBursts::12 7582 # Per bank write bursts +system.physmem.perBankWrBursts::13 8119 # Per bank write bursts +system.physmem.perBankWrBursts::14 7846 # Per bank write bursts +system.physmem.perBankWrBursts::15 7365 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 2832862744500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 2832893894500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166513 # Read request sizes (log2) +system.physmem.readPktSize::6 166788 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125412 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 728 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125486 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,162 +160,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.784899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.937223 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.895489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23052 37.23% 37.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14889 24.05% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6490 10.48% 71.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3653 5.90% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2551 4.12% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1649 2.66% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1497 2.42% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1106 1.79% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7028 11.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61915 # Bytes accessed per row activation +system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 305.167515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.813202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.494619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23016 37.06% 37.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15104 24.32% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6524 10.50% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3665 5.90% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2528 4.07% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1637 2.64% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1479 2.38% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1102 1.77% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7053 11.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62108 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.666884 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.620654 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.706936 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.623530 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.496418 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.503929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.596363 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5449 88.72% 88.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 115 1.87% 90.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.46% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 44 0.72% 91.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 34 0.55% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 18 0.29% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 53 0.86% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.11% 93.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 141 2.30% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.18% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.13% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 63 1.03% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.11% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.41% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 94 1.53% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.507001 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.506831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.607971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5435 88.49% 88.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 129 2.10% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.50% 91.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 49 0.80% 91.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.52% 92.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.28% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 48 0.78% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.23% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 140 2.28% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.18% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.13% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.13% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 65 1.06% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.34% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 93 1.51% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.18% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads -system.physmem.totQLat 2126742000 # Total ticks spent queuing -system.physmem.totMemAccLat 5313023250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849675000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12515.03 # Average queueing delay per DRAM burst +system.physmem.totQLat 2108320500 # Total ticks spent queuing +system.physmem.totMemAccLat 5299439250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850965000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12387.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31265.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31137.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing -system.physmem.readRowHits 139707 # Number of row buffer hits during reads -system.physmem.writeRowHits 94201 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.82 # Row buffer hit rate for writes -system.physmem.avgGap 9447347.56 # Average gap between requests -system.physmem.pageHitRate 79.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242207280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132156750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 687546600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 416962080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83427429555 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626531651000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896466320945 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.453835 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705741524500 # Time in different power states -system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states +system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing +system.physmem.readRowHits 139937 # Number of row buffer hits during reads +system.physmem.writeRowHits 94101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 9436468.49 # Average gap between requests +system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 243454680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132837375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 690495000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 417759120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83647548450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626357251250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896519747795 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.465335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705450093000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32519220500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32840757000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225870120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123242625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 637938600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398798640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82153488960 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.365771 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states -system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states +system.physmem_1.actEnergy 226081800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123358125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 637002600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398422800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82216233135 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627612791000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896244291380 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.368099 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2707556632500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30741160500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -328,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46806016 # Number of BP lookups -system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1175497 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29454915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13525299 # Number of BTB hits +system.cpu.branchPred.lookups 46812529 # Number of BP lookups +system.cpu.branchPred.condPredicted 23980713 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1174980 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29461889 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13525990 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 45.910125 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11726513 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 34925 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7916092 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7770128 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 145964 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60126 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,47 +383,47 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 9708 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9708 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9708 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9708 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9708 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.walks 9712 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9712 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9712 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9712 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9712 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6238 82.69% 82.69% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1306 17.31% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7544 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9708 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 6218 82.38% 82.38% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1330 17.62% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7548 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9712 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9708 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7544 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9712 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7548 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7544 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17252 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7548 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17260 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24576304 # DTB read hits -system.cpu.checker.dtb.read_misses 8296 # DTB read misses -system.cpu.checker.dtb.write_hits 19632670 # DTB write hits -system.cpu.checker.dtb.write_misses 1412 # DTB write misses +system.cpu.checker.dtb.read_hits 24578721 # DTB read hits +system.cpu.checker.dtb.read_misses 8315 # DTB read misses +system.cpu.checker.dtb.write_hits 19634427 # DTB write hits +system.cpu.checker.dtb.write_misses 1397 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.checker.dtb.flush_entries 4219 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24584600 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19634082 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24587036 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19635824 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44208974 # DTB hits -system.cpu.checker.dtb.misses 9708 # DTB misses -system.cpu.checker.dtb.accesses 44218682 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.hits 44213148 # DTB hits +system.cpu.checker.dtb.misses 9712 # DTB misses +system.cpu.checker.dtb.accesses 44222860 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,7 +453,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency @@ -470,7 +472,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115798779 # ITB inst hits +system.cpu.checker.itb.inst_hits 115810053 # ITB inst hits system.cpu.checker.itb.inst_misses 4825 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -487,15 +489,15 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115803604 # ITB inst accesses -system.cpu.checker.itb.hits 115798779 # DTB hits +system.cpu.checker.itb.inst_accesses 115814878 # ITB inst accesses +system.cpu.checker.itb.hits 115810053 # DTB hits system.cpu.checker.itb.misses 4825 # DTB misses -system.cpu.checker.itb.accesses 115803604 # DTB accesses -system.cpu.checker.pwrStateResidencyTicks::ON 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 139031272 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115814878 # DTB accesses +system.cpu.checker.pwrStateResidencyTicks::ON 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.checker.numCycles 139044613 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -525,81 +527,82 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 72368 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 51295 97.51% 97.51% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 909 1.73% 99.24% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 317 0.60% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 17 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 72186 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72186 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29334 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23181 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19671 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52515 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 467.713986 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2821.743931 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-8191 51203 97.50% 97.50% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-24575 322 0.61% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-32767 40 0.08% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-40959 18 0.03% 99.95% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52603 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17713 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8411.296807 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17487 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 220 1.24% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17713 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131327462316 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.619046 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.492812 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131267362816 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 40987500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 8789000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6827500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1022500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 578500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1418000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 467000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 52515 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17658 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8522.119991 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17438 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 214 1.21% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17658 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131358619316 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629965 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.490082 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131298865316 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 40695500 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 8747000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6751500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1053500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 584000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1412000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131327462316 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6375 82.60% 82.60% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1343 17.40% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7718 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72368 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131358619316 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6349 82.25% 82.25% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1370 17.75% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7719 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72186 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72186 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7719 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7719 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79905 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25410890 # DTB read hits -system.cpu.dtb.read_misses 62740 # DTB read misses -system.cpu.dtb.write_hits 19865163 # DTB write hits -system.cpu.dtb.write_misses 9628 # DTB write misses +system.cpu.dtb.read_hits 25413003 # DTB read hits +system.cpu.dtb.read_misses 62542 # DTB read misses +system.cpu.dtb.write_hits 19866296 # DTB write hits +system.cpu.dtb.write_misses 9644 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 366 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2075 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25473630 # DTB read accesses -system.cpu.dtb.write_accesses 19874791 # DTB write accesses +system.cpu.dtb.perms_faults 1321 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25475545 # DTB read accesses +system.cpu.dtb.write_accesses 19875940 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45276053 # DTB hits -system.cpu.dtb.misses 72368 # DTB misses -system.cpu.dtb.accesses 45348421 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45279299 # DTB hits +system.cpu.dtb.misses 72186 # DTB misses +system.cpu.dtb.accesses 45351485 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -629,58 +632,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 12817 # Table walker walks requested system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3407 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7692 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 10511 94.70% 94.70% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 118 1.06% 95.77% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 237 2.14% 97.90% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.01% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 46 0.41% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 742.229030 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 3116.397220 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.79% 94.79% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 119 1.07% 95.86% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 227 2.05% 97.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.02% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 47 0.42% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 5044 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12037.073751 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9689.647863 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7634.465398 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 4079 80.87% 80.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 946 18.75% 99.62% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::samples 5040 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12026.488095 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9684.197840 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7608.176186 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 4071 80.77% 80.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 955 18.95% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-49151 11 0.22% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 5044 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23953217916 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.646337 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.478297 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 8473460000 35.38% 35.38% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 15477752916 64.62% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 1917000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 5040 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23984374916 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.642154 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.479545 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 8584682500 35.79% 35.79% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 15397812416 64.20% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 1792000 0.01% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23953217916 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2992 89.96% 89.96% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 334 10.04% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 23984374916 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2987 89.92% 89.92% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 16143 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 65995629 # ITB inst hits +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 16139 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 65982481 # ITB inst hits system.cpu.itb.inst_misses 12817 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -690,112 +693,112 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3021 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2147 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66008446 # ITB inst accesses -system.cpu.itb.hits 65995629 # DTB hits +system.cpu.itb.inst_accesses 65995298 # ITB inst accesses +system.cpu.itb.hits 65982481 # DTB hits system.cpu.itb.misses 12817 # DTB misses -system.cpu.itb.accesses 66008446 # DTB accesses +system.cpu.itb.accesses 65995298 # DTB accesses system.cpu.numPwrStateTransitions 6074 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 886948130.312150 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17421700028.084686 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499972891000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 278423951 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 139232654742 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 278465363 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104979858 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184015649 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46812529 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33022631 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 161497089 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6057652 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 189263 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8972 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337056 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 558097 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65981271 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1027864 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6246 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 270599333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.829251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.216918 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171686790 63.45% 63.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29154260 10.77% 74.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14034299 5.19% 79.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55723984 20.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18530 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30752508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150221263 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 676943612 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 163957736 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10899 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141737618 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8483639 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2839333 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2643784 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13883095 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26339486 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21214202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1704469 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14294324 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 270599333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168109 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.660821 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77964907 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 121895477 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64303176 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3866825 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2568948 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3406986 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 467982 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 156982730 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3511045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2568948 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83721940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11815597 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76560081 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62413108 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33519659 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146432544 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 918349 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 465966 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65322 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 18586 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30762818 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150226924 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 676971311 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 163962292 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10893 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141750491 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8476427 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2839737 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2644396 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13885386 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26339908 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21214343 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1703941 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2126584 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143224778 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2118002 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143047064 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 260478 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8148926 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14278560 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121950 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270599333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.528631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.865147 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182394036 67.40% 67.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45259787 16.73% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31866202 11.78% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10262392 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 816883 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -803,9 +806,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270599333 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7342152 32.76% 32.76% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available @@ -834,13 +837,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5623214 25.10% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9441955 42.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5622313 25.09% 57.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9444091 42.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95844496 67.01% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114325 0.08% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95850690 67.01% 67.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114288 0.08% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued @@ -864,99 +867,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8577 0.01% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26130891 18.27% 85.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20940281 14.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued -system.cpu.iq.rate 0.513744 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses +system.cpu.iq.FU_type_0::total 143047064 # Type of FU issued +system.cpu.iq.rate 0.513698 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22408588 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156652 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 579326888 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153497201 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 139997351 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35639 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165429916 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 323958 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1435915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 710 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18680 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 623667 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1433781 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 712 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18665 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 622043 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88637 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6231 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88844 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6344 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2569037 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1239960 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 546279 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145517187 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2568948 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1241907 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 544667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145523405 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26339486 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21214202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1094236 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 509843 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18680 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 277456 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471588 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 749044 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142138491 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25734027 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 827925 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26339908 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21214343 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1094304 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17849 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 508298 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18665 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 277238 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471000 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 748238 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142148555 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25736254 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 826428 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180634 # number of nop insts executed -system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed -system.cpu.iew.exec_branches 26490215 # Number of branches executed -system.cpu.iew.exec_stores 20827406 # Number of stores executed -system.cpu.iew.exec_rate 0.510511 # Inst execution rate -system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63237137 # num instructions producing a value -system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value -system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180625 # number of nop insts executed +system.cpu.iew.exec_refs 46564673 # number of memory reference insts executed +system.cpu.iew.exec_branches 26492434 # Number of branches executed +system.cpu.iew.exec_stores 20828419 # Number of stores executed +system.cpu.iew.exec_rate 0.510471 # Inst execution rate +system.cpu.iew.wb_sent 141779361 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140008720 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63240555 # num instructions producing a value +system.cpu.iew.wb_consumers 95712709 # num instructions consuming a value +system.cpu.iew.wb_rate 0.502787 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660733 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7366290 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1996052 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 715102 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267708008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513054 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.118068 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194252968 72.56% 72.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43305040 16.18% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15457612 5.77% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4371808 1.63% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6428406 2.40% 98.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1610065 0.60% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 797962 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 411830 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1072317 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113255406 # Number of instructions committed -system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267708008 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113266238 # Number of instructions committed +system.cpu.commit.committedOps 137348755 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45494106 # Number of memory references committed -system.cpu.commit.loads 24903571 # Number of loads committed -system.cpu.commit.membars 814876 # Number of memory barriers committed -system.cpu.commit.branches 26023568 # Number of branches committed +system.cpu.commit.refs 45498427 # Number of memory references committed +system.cpu.commit.loads 24906127 # Number of loads committed +system.cpu.commit.membars 814995 # Number of memory barriers committed +system.cpu.commit.branches 26026646 # Number of branches committed system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120163713 # Number of committed integer instructions. -system.cpu.commit.function_calls 4884102 # Number of function calls committed. +system.cpu.commit.int_insts 120175202 # Number of committed integer instructions. +system.cpu.commit.function_calls 4885014 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91720354 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91728959 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112792 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -980,544 +983,544 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8577 0.01% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24903571 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24906127 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20592300 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction -system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389119868 # The number of ROB reads -system.cpu.rob.rob_writes 292294903 # The number of ROB writes -system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113100501 # Number of Instructions Simulated -system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads -system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155524954 # number of integer regfile reads -system.cpu.int_regfile_writes 88488763 # number of integer regfile writes -system.cpu.fp_regfile_reads 9529 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137348755 # Class of committed instruction +system.cpu.commit.bw_lim_events 1072317 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389160423 # The number of ROB reads +system.cpu.rob.rob_writes 292308325 # The number of ROB writes +system.cpu.timesIdled 890756 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7866030 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387322891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113111333 # Number of Instructions Simulated +system.cpu.committedOps 137193850 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.461870 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.461870 # CPI: Total CPI of All Threads +system.cpu.ipc 0.406195 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.406195 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155535200 # number of integer regfile reads +system.cpu.int_regfile_writes 88495254 # number of integer regfile writes +system.cpu.fp_regfile_reads 9528 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502156067 # number of cc regfile reads -system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes -system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 838747 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 502191760 # number of cc regfile reads +system.cpu.cc_regfile_writes 53133619 # number of cc regfile writes +system.cpu.misc_regfile_reads 459496628 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521804 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 838109 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.925913 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40060330 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838621 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.769290 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.925913 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits -system.cpu.dcache.overall_hits::total 39152132 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3607427 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177712 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177712 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 27363 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 27363 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179138470 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179138470 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23266826 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23266826 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542812 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542812 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345885 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345885 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441505 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441505 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460387 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460387 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38809638 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38809638 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39155523 # number of overall hits +system.cpu.dcache.overall_hits::total 39155523 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 704207 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 704207 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3608607 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3608607 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177503 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177503 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 27219 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 27219 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4312561 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4312561 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4490273 # number of overall misses -system.cpu.dcache.overall_misses::total 4490273 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711380000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711380000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 232487777697 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 232487777697 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376699000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 376699000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 276000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188380 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339527 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339527 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058381 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058381 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 4312814 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4312814 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4490317 # number of overall misses +system.cpu.dcache.overall_misses::total 4490317 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11705123500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11705123500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 232670418192 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 232670418192 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376308000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 376308000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 275000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 275000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 244375541692 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 244375541692 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 244375541692 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 244375541692 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23971033 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23971033 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19151419 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19151419 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523388 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523388 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468724 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468724 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460392 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460392 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43122452 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43122452 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43645840 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43645840 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029377 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029377 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188425 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188425 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339142 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339142 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058070 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100015 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100015 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102888 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102888 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16608.729688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16608.729688 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64446.980548 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.728794 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.728794 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55200 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55200 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56625.090682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56625.090682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.033598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54384.033598 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 871366 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.100013 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100013 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102881 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102881 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16621.708532 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16621.708532 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64476.519109 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64476.519109 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13825.195635 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13825.195635 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56662.666577 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56662.666577 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54422.781664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54422.781664 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 867732 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6856 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6871 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.095391 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 126.289041 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 696773 # number of writebacks -system.cpu.dcache.writebacks::total 696773 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291027 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 291027 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307518 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3307518 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18885 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18885 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3598545 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3598545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3598545 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3598545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414107 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414107 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299909 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299909 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119568 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119568 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8478 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8478 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 696134 # number of writebacks +system.cpu.dcache.writebacks::total 696134 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290642 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 290642 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3308599 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3308599 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18782 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18782 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3599241 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3599241 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3599241 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3599241 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413565 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 413565 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300008 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300008 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119442 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119442 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8437 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8437 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 714016 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 714016 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 833584 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 833584 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713573 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713573 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 833015 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 833015 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386388500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386388500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19974009472 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19974009472 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1699913000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1699913000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127031000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127031000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26360397972 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26360397972 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28060310972 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28060310972 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276272000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276272000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276272000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276272000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015661 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015661 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228440 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228440 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018088 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018088 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6383877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6383877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19987260971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19987260971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1693165000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1693165000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126972500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126972500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 270000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26371138471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26371138471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064303471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28064303471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276254500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276254500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276254500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276254500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015665 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015665 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228209 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228209 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016559 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016559 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019100 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019100 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15422.073281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15422.073281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66600.233644 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66600.233644 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.123311 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.123311 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14983.604624 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14983.604624 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54200 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54200 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1886245 # number of replacements -system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1886757 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.927749 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016548 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016548 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019086 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019086 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15436.213171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15436.213171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66622.426639 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66622.426639 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14175.624990 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1886431 # number of replacements +system.cpu.icache.tags.tagsinuse 511.154202 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64000082 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1886943 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.917337 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.154077 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.154202 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 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cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28160163493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28160163493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28160163493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28160163493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65991394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65991394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65991394 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65991394 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65991394 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65991394 # number of overall (read+write) accesses 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misses +system.cpu.icache.ReadReq_misses::total 1978185 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1978185 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1978185 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1978185 # number of overall misses +system.cpu.icache.overall_misses::total 1978185 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28158737492 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28158737492 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28158737492 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28158737492 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28158737492 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28158737492 # number of overall miss cycles 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demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 91184 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 91184 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 91184 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887001 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1887001 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1887001 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1887001 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1887001 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1887001 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25187429497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25187429497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25187429497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25187429497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25187429497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25187429497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25189687497 # number of ReadReq MSHR miss cycles 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-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028592 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028592 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028592 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.248861 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.248861 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028600 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028600 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028600 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.058902 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.058902 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.058902 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.058902 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.058902 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.058902 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96776 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162101 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 30.885109 # Average number of references to valid blocks. +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 97066 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65034.676246 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5004762 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162374 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 30.822435 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.737497 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.672900 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10369.952431 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5025.112172 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.757146 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000164 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49586.658386 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.610418 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.677884 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10386.588269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5047.141288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.756632 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000177 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000041 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158233 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.076677 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992260 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65312 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158487 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.077013 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992350 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65293 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6691 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55601 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 696773 # number of WritebackDirty hits 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latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119959.917496 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122544.732361 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456516 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.456516 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010548 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024468 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024468 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060426 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060426 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129553.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.381646 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.381646 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119832.402626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119832.402626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122449.228910 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122449.228910 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124710.607777 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124710.607777 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.418260 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.538849 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100267.900330 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.217396 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5483160 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757544 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 128619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557060 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 821637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1886431 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 149968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2806 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 542244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 541532 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665772 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640441 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8471013 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241517552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98498985 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5666337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2638583 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30857 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133499 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8469276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241541168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98417449 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340297169 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194360 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3054889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.024700 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.155211 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 231212 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340238093 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 194794 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 8145576 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3054607 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.024758 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.155386 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2979432 97.53% 97.53% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 75457 2.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2978982 97.52% 97.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 75625 2.48% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3054889 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5401923998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3054607 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5400960498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2834452098 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1304519551 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18799483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75755880 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30172 # Transaction distribution system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1714,66 +1718,66 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43093500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 43088500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 652000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 651500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33076500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33063500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187162988 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187149991 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.005857 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256506730000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005857 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062866 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062866 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328023 # Number of tag accesses system.iocache.tags.data_accesses 328023 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses system.iocache.ReadReq_misses::total 223 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1782,14 +1786,14 @@ system.iocache.demand_misses::realview.ide 36447 # system.iocache.demand_misses::total 36447 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36447 # number of overall misses system.iocache.overall_misses::total 36447 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28153877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28153877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4551268111 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4551268111 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4579421988 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4579421988 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4579421988 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4579421988 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28156877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28156877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4551348114 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4551348114 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4579504991 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4579504991 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4579504991 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4579504991 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1806,14 +1810,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126250.569507 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126250.569507 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125642.339637 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125642.339637 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125646.061075 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125646.061075 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126264.022422 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125648.338437 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125648.338437 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1830,14 +1834,14 @@ system.iocache.demand_mshr_misses::realview.ide 36447 system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17003877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17003877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738656099 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2738656099 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2755659976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2755659976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2755659976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2755659976 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17006877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17006877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738747578 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2738747578 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2755754455 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2755754455 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2755754455 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2755754455 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1846,83 +1850,84 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34132 # Transaction distribution -system.membus.trans_dist::ReadResp 67490 # Transaction distribution +system.membus.trans_dist::ReadResp 67530 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::WritebackDirty 125412 # Transaction distribution -system.membus.trans_dist::CleanEvict 7777 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4588 # Transaction distribution +system.membus.trans_dist::WritebackDirty 125486 # Transaction distribution +system.membus.trans_dist::CleanEvict 7993 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4611 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 133639 # Transaction distribution -system.membus.trans_dist::ReadExResp 133639 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33359 # Transaction distribution +system.membus.trans_dist::ReadExReq 133874 # Transaction distribution +system.membus.trans_dist::ReadExResp 133874 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33399 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558073 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 451368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558936 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 630948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 631811 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16433756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16597145 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16456092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16619481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18914265 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18936601 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 487 # Total snoops (count) -system.membus.snoop_fanout::samples 402739 # Request fanout histogram +system.membus.snoopTraffic 31040 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 403324 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402739 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 403324 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402739 # Request fanout histogram -system.membus.reqLayer0.occupancy 83678000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 403324 # Request fanout histogram +system.membus.reqLayer0.occupancy 83656500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1737499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1736499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 875953366 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 876921354 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 978576250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 979994750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1954,29 +1959,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 6af9f752e..ecd5fd333 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -124,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -162,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -218,12 +233,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -242,8 +262,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -266,9 +291,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -282,9 +312,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -560,12 +595,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -584,8 +624,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -643,9 +688,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -659,9 +709,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -672,12 +727,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -695,6 +755,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -705,6 +766,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -721,8 +786,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -730,10 +800,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -778,6 +853,7 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -816,6 +892,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -872,12 +952,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -896,8 +981,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -920,9 +1010,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -936,9 +1031,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -1214,12 +1314,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -1238,8 +1343,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1297,9 +1407,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1313,9 +1428,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -1326,12 +1446,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -1349,6 +1474,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -1359,6 +1485,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -1375,8 +1505,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -1384,10 +1519,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1432,9 +1572,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1448,12 +1593,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1472,8 +1622,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1484,12 +1639,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1508,8 +1668,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -1517,10 +1682,15 @@ size=4194304 type=CoherentXBar children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 @@ -1534,11 +1704,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1590,6 +1765,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1601,7 +1777,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1644,10 +1824,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1728,14 +1913,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1744,13 +1934,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1831,10 +2026,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1914,17 +2114,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1950,13 +2155,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1964,14 +2174,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2057,14 +2272,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2073,13 +2293,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2088,13 +2313,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2102,11 +2332,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2120,11 +2355,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2138,12 +2378,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -2211,10 +2456,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2223,11 +2473,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2237,21 +2492,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2261,12 +2526,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2275,10 +2545,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2288,12 +2563,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2303,26 +2583,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2331,10 +2621,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2342,10 +2637,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2353,21 +2653,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2381,11 +2691,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2396,11 +2711,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2408,10 +2728,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2427,10 +2752,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 3e7bd42ce..8041988f0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 5b77a63d3..1edb75ef2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:31 -gem5 executing on phenom, pid 15964 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:39:51 +gem5 executing on e108600-lin, pid 23108 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2825959731500 because m5_exit instruction encountered +Exiting @ tick 2825947406000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a155d5f42..d0d350a97 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825960 # Number of seconds simulated -sim_ticks 2825959731500 # Number of ticks simulated -final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.825947 # Number of seconds simulated +sim_ticks 2825947406000 # Number of ticks simulated +final_tick 2825947406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99061 # Simulator instruction rate (inst/s) -host_op_rate 120168 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2330545961 # Simulator tick rate (ticks/s) -host_mem_usage 626024 # Number of bytes of host memory used -host_seconds 1212.57 # Real time elapsed on the host -sim_insts 120118276 # Number of instructions simulated -sim_ops 145712235 # Number of ops (including micro ops) simulated +host_inst_rate 72283 # Simulator instruction rate (inst/s) +host_op_rate 87685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1700475056 # Simulator tick rate (ticks/s) +host_mem_usage 618496 # Number of bytes of host memory used +host_seconds 1661.86 # Real time elapsed on the host +sim_insts 120124543 # Number of instructions simulated +sim_ops 145720076 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 644308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 521472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1303616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1321960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8513856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 181024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 635732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 529024 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12495724 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1306176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 181104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1487280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8956736 # Number of bytes written to this memory +system.physmem.bytes_read::total 12488540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1303616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 181024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1484640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8962368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8974300 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8979932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 8148 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 8266 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198102 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139949 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197989 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140037 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144340 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 462206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 467701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3014044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 227996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 184529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 461302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 467794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3012744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 224962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 187202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4421763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 462206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 526292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3169449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4419240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 461302 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 525360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3171456 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3175665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3169449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3177671 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3171456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 462206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 473902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3014044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 228010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 184529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 461302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 473995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3012744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 224977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 187202 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7597427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198102 # Number of read requests accepted -system.physmem.writeReqs 144340 # Number of write requests accepted -system.physmem.readBursts 198102 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 144340 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12669056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 8986944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12495724 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8974300 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7596911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197990 # Number of read requests accepted +system.physmem.writeReqs 144428 # Number of write requests accepted +system.physmem.readBursts 197990 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 144428 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12662400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.physmem.bytesWritten 8992448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12488604 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8979932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12421 # Per bank write bursts -system.physmem.perBankRdBursts::1 12320 # Per bank write bursts -system.physmem.perBankRdBursts::2 12949 # Per bank write bursts -system.physmem.perBankRdBursts::3 12687 # Per bank write bursts -system.physmem.perBankRdBursts::4 14539 # Per bank write bursts -system.physmem.perBankRdBursts::5 12136 # Per bank write bursts -system.physmem.perBankRdBursts::6 12666 # Per bank write bursts -system.physmem.perBankRdBursts::7 12482 # Per bank write bursts -system.physmem.perBankRdBursts::8 12195 # Per bank write bursts -system.physmem.perBankRdBursts::9 12078 # Per bank write bursts -system.physmem.perBankRdBursts::10 11738 # Per bank write bursts -system.physmem.perBankRdBursts::11 11022 # Per bank write bursts -system.physmem.perBankRdBursts::12 11908 # Per bank write bursts -system.physmem.perBankRdBursts::13 13049 # Per bank write bursts -system.physmem.perBankRdBursts::14 12095 # Per bank write bursts -system.physmem.perBankRdBursts::15 11669 # Per bank write bursts -system.physmem.perBankWrBursts::0 9112 # Per bank write bursts +system.physmem.perBankRdBursts::0 12407 # Per bank write bursts +system.physmem.perBankRdBursts::1 12295 # Per bank write bursts +system.physmem.perBankRdBursts::2 12935 # Per bank write bursts +system.physmem.perBankRdBursts::3 12653 # Per bank write bursts +system.physmem.perBankRdBursts::4 14543 # Per bank write bursts +system.physmem.perBankRdBursts::5 12106 # Per bank write bursts +system.physmem.perBankRdBursts::6 12653 # Per bank write bursts +system.physmem.perBankRdBursts::7 12509 # Per bank write bursts +system.physmem.perBankRdBursts::8 12223 # Per bank write bursts +system.physmem.perBankRdBursts::9 12064 # Per bank write bursts +system.physmem.perBankRdBursts::10 11718 # Per bank write bursts +system.physmem.perBankRdBursts::11 11008 # Per bank write bursts +system.physmem.perBankRdBursts::12 11914 # Per bank write bursts +system.physmem.perBankRdBursts::13 13060 # Per bank write bursts +system.physmem.perBankRdBursts::14 12107 # Per bank write bursts +system.physmem.perBankRdBursts::15 11655 # Per bank write bursts +system.physmem.perBankWrBursts::0 9105 # Per bank write bursts system.physmem.perBankWrBursts::1 9127 # Per bank write bursts -system.physmem.perBankWrBursts::2 9607 # Per bank write bursts -system.physmem.perBankWrBursts::3 9172 # Per bank write bursts -system.physmem.perBankWrBursts::4 8420 # Per bank write bursts -system.physmem.perBankWrBursts::5 8729 # Per bank write bursts -system.physmem.perBankWrBursts::6 8984 # Per bank write bursts -system.physmem.perBankWrBursts::7 8803 # Per bank write bursts -system.physmem.perBankWrBursts::8 8716 # Per bank write bursts -system.physmem.perBankWrBursts::9 8606 # Per bank write bursts -system.physmem.perBankWrBursts::10 8527 # Per bank write bursts -system.physmem.perBankWrBursts::11 8118 # Per bank write bursts -system.physmem.perBankWrBursts::12 8733 # Per bank write bursts -system.physmem.perBankWrBursts::13 9183 # Per bank write bursts -system.physmem.perBankWrBursts::14 8560 # Per bank write bursts -system.physmem.perBankWrBursts::15 8024 # Per bank write bursts +system.physmem.perBankWrBursts::2 9615 # Per bank write bursts +system.physmem.perBankWrBursts::3 9150 # Per bank write bursts +system.physmem.perBankWrBursts::4 8481 # Per bank write bursts +system.physmem.perBankWrBursts::5 8750 # Per bank write bursts +system.physmem.perBankWrBursts::6 8993 # Per bank write bursts +system.physmem.perBankWrBursts::7 8806 # Per bank write bursts +system.physmem.perBankWrBursts::8 8720 # Per bank write bursts +system.physmem.perBankWrBursts::9 8569 # Per bank write bursts +system.physmem.perBankWrBursts::10 8518 # Per bank write bursts +system.physmem.perBankWrBursts::11 8119 # Per bank write bursts +system.physmem.perBankWrBursts::12 8743 # Per bank write bursts +system.physmem.perBankWrBursts::13 9182 # Per bank write bursts +system.physmem.perBankWrBursts::14 8573 # Per bank write bursts +system.physmem.perBankWrBursts::15 8056 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 2825959428000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2825947136000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3087 # Read request sizes (log2) +system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194436 # Read request sizes (log2) +system.physmem.readPktSize::6 194325 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 139949 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 72005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140037 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 72217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -189,118 +189,120 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 234.287927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.256290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.423161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50967 55.14% 55.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17630 19.07% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5955 6.44% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3343 3.62% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2739 2.96% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1518 1.64% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 933 1.01% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1042 1.13% 91.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8306 8.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92433 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6998 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.287082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.369682 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6996 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 234.414947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.500025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.048436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50794 54.98% 54.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17715 19.18% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5941 6.43% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3366 3.64% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2816 3.05% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1529 1.66% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 925 1.00% 89.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 990 1.07% 91.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8302 8.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92378 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.296339 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.591514 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6990 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6998 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.065876 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.638507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.720707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5824 83.22% 83.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 388 5.54% 88.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 101 1.44% 90.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 68 0.97% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 286 4.09% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 30 0.43% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.31% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 18 0.26% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.19% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.09% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.11% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 167 2.39% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.11% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.13% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6992 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.095395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.609227 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.295574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5854 83.72% 83.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 392 5.61% 89.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 80 1.14% 90.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 62 0.89% 91.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 277 3.96% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.29% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.21% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.34% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 25 0.36% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.17% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.13% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.20% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 142 2.03% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.14% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.10% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.20% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6998 # Writes before turning the bus around for reads -system.physmem.totQLat 6678126737 # Total ticks spent queuing -system.physmem.totMemAccLat 10389764237 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33735.75 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6992 # Writes before turning the bus around for reads +system.physmem.totQLat 6748582846 # Total ticks spent queuing +system.physmem.totMemAccLat 10458270346 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 989250000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34109.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52485.75 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 52859.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s @@ -309,43 +311,43 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 165316 # Number of row buffer hits during reads -system.physmem.writeRowHits 80625 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes -system.physmem.avgGap 8252373.91 # Average gap between requests -system.physmem.pageHitRate 72.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 362040840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 197542125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 797160000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 466261920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79687786095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625672869500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891761444000 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.423201 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704357113137 # Time in different power states -system.physmem_0.memoryStateTime::REF 94364920000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 165284 # Number of row buffer hits during reads +system.physmem.writeRowHits 80694 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.42 # Row buffer hit rate for writes +system.physmem.avgGap 8252916.42 # Average gap between requests +system.physmem.pageHitRate 72.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 361058040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 197005875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 796387800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 466734960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79734690540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625622381750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891755025365 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.424618 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704272847388 # Time in different power states +system.physmem_0.memoryStateTime::REF 94364400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27235374363 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27304587612 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 336752640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 183744000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 746873400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 443666160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79354368585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.369090 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states -system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states +system.physmem_1.actEnergy 337319640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 184053375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 746834400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 443750400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79554512970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1625780432250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891623669435 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.378136 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2704538486760 # Time in different power states +system.physmem_1.memoryStateTime::REF 94364400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27044516240 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -364,30 +366,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53057105 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 933540 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32092107 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 13945777 # Number of BTB hits +system.cpu0.branchPred.lookups 53058502 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24374377 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 933450 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32093175 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 13944864 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. +system.cpu0.branchPred.BTBHitPct 43.451182 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15470259 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33206 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 10120086 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 9964746 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 155340 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -417,86 +419,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 67255 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43255 97.44% 97.44% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 874 1.97% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 114 0.26% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 99 0.22% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 12 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 67164 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67164 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25323 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19031 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22810 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44354 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 458.594490 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2953.911408 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43233 97.47% 97.47% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 862 1.94% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 108 0.24% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44392 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 17098 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11190.109954 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9724.852754 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7829.867535 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 15731 92.00% 92.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1253 7.33% 99.33% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 72 0.42% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.04% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::147456-163839 16 0.09% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 17098 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 81474776356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.525392 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.513017 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 81416314856 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 41234500 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7083500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4738000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1423000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1004000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1185500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1778000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 81474776356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5261 77.38% 77.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6799 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67255 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44354 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 17047 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11038.716490 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9658.702439 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6683.029230 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 15750 92.39% 92.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1185 6.95% 99.34% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 75 0.44% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 14 0.08% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 14 0.08% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 17047 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 85757506152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.515718 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.512261 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 85699757152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 40650000 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7189500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4730000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1448500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1006500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1064000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1646000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 85757506152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5272 77.42% 77.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6810 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67164 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67255 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6799 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67164 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6810 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6799 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74054 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6810 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 73974 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23647306 # DTB read hits -system.cpu0.dtb.read_misses 56401 # DTB read misses -system.cpu0.dtb.write_hits 17573284 # DTB write hits -system.cpu0.dtb.write_misses 10854 # DTB write misses +system.cpu0.dtb.read_hits 23645826 # DTB read hits +system.cpu0.dtb.read_misses 56383 # DTB read misses +system.cpu0.dtb.write_hits 17571331 # DTB write hits +system.cpu0.dtb.write_misses 10781 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 213 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2243 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23703707 # DTB read accesses -system.cpu0.dtb.write_accesses 17584138 # DTB write accesses +system.cpu0.dtb.perms_faults 818 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23702209 # DTB read accesses +system.cpu0.dtb.write_accesses 17582112 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41220590 # DTB hits -system.cpu0.dtb.misses 67255 # DTB misses -system.cpu0.dtb.accesses 41287845 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 41217157 # DTB hits +system.cpu0.dtb.misses 67164 # DTB misses +system.cpu0.dtb.accesses 41284321 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,56 +526,59 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10944 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9496 96.09% 96.09% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 178 1.80% 97.90% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 126 1.28% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.23% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9882 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3633 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11938.893476 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11121.754202 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4829.169649 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 620 17.07% 17.07% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2792 76.85% 93.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.24% 99.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 33 0.91% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 10883 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10883 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3898 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5925 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1060 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9823 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 449.709865 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2327.234590 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9434 96.04% 96.04% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 184 1.87% 97.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.18% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9823 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3631 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11923.299367 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11119.549027 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4771.165368 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 614 16.91% 16.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2801 77.14% 94.05% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 0.74% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3633 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21344293712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.816978 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.386812 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3907509500 18.31% 18.31% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17435777712 81.69% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 987000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 19500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21344293712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2239 87.09% 87.09% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 332 12.91% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3631 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21332036712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.795904 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.403169 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 4354826000 20.41% 20.41% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 16976239212 79.58% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 901500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21332036712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2243 87.24% 87.24% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 328 12.76% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10944 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10944 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10883 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10883 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13515 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 72708872 # ITB inst hits -system.cpu0.itb.inst_misses 10944 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin::total 13454 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 72708520 # ITB inst hits +system.cpu0.itb.inst_misses 10883 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -584,111 +587,111 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2281 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses -system.cpu0.itb.hits 72708872 # DTB hits -system.cpu0.itb.misses 10944 # DTB misses -system.cpu0.itb.accesses 72719816 # DTB accesses -system.cpu0.numPwrStateTransitions 3656 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1828 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1490596475.785011 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23949118810.105305 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1055 57.71% 57.71% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 768 42.01% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 72719403 # ITB inst accesses +system.cpu0.itb.hits 72708520 # DTB hits +system.cpu0.itb.misses 10883 # DTB misses +system.cpu0.itb.accesses 72719403 # DTB accesses +system.cpu0.numPwrStateTransitions 3678 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1839 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1481668762.034258 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23877600166.586662 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1061 57.69% 57.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.03% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499973380096 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1828 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 101149373765 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724810357735 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 202299816 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499971949600 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1839 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 101158552619 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724788853381 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 202318013 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5690816 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148557 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 57787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 411894 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 415808 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 91444 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 72708572 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 259286 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5400 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 198828221 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.203592 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.307832 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 20370009 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 195788924 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53058502 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39379869 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 174489676 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5690920 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 148682 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 56911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 412776 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 413906 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 90774 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 72708226 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 258373 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5359 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 198828194 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.203611 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.307839 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 93975229 47.26% 47.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 30343697 15.26% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14563448 7.32% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 59945847 30.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 93974548 47.26% 47.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 30342793 15.26% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14563641 7.32% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 59947212 30.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 198828221 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.262270 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.967832 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25603497 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 106945433 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 58799621 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4964058 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2515612 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3059417 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 333874 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 154225745 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3810952 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2515612 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 34211381 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12457896 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 83569478 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 55018547 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11055307 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 137550697 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1033071 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1452205 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 164556 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 58179 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6849429 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 141656181 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 634589847 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 152645231 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9369 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 130468277 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11187893 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2697265 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2555549 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22573870 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 24578234 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19061004 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1697434 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2322680 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 134618116 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1713414 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 132756465 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 452944 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10581179 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21719888 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 120083 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 198828221 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.667694 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.963230 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 198828194 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.262253 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.967729 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25600367 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 106949118 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 58799478 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4963264 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2515967 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3058039 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 333585 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 154217934 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3811468 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2515967 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 34209280 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12450122 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 83570932 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 55016631 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11065262 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 137539344 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1033397 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1452682 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 164882 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 58749 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6858829 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 141646141 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 634543216 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 152633070 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9368 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 130461493 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11184637 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2697680 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2556046 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22573700 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 24576087 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19059052 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1700091 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2321608 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 134608055 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1714170 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 132746710 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 453040 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10578491 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21717645 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 121089 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 198828194 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.667645 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.963186 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 122137220 61.43% 61.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 33612355 16.91% 78.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31219254 15.70% 94.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10732023 5.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1127312 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 122140771 61.43% 61.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 33611714 16.90% 78.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 31218891 15.70% 94.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10730115 5.40% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1126646 0.57% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -696,44 +699,44 @@ system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 198828221 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 198828194 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10787922 43.88% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 67 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5632694 22.91% 66.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8166758 33.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10786366 43.89% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 65 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5629308 22.91% 66.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8160859 33.21% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 89674441 67.55% 67.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 111153 0.08% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 89668905 67.55% 67.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 111084 0.08% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued @@ -756,100 +759,100 @@ system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Ty system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8107 0.01% 67.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8099 0.01% 67.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24338377 18.33% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18622113 14.03% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 24336393 18.33% 85.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 18619956 14.03% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 132756465 # Type of FU issued -system.cpu0.iq.rate 0.656236 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24587441 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.185207 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 489349072 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 146920725 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 129226985 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32463 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11252 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 132746710 # Type of FU issued +system.cpu0.iq.rate 0.656129 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 24576598 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.185139 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 489318685 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 146908772 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 129217545 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32566 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11248 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157320500 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21133 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365431 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 157299800 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21235 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365614 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1915604 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19339 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 897405 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1914996 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2485 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19372 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 896753 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 120966 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 361642 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 121022 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362352 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2515612 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1602789 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 184527 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 136483987 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2515967 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1594217 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 188418 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 136474692 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 24578234 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19061004 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 875924 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28511 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 132116 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19339 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 261906 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398193 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 660099 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131724041 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 23895876 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 965291 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 24576087 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19059052 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876204 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28441 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 136041 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19372 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 261507 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 398935 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 660442 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 131715074 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 23894149 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 964599 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152457 # number of nop insts executed -system.cpu0.iew.exec_refs 42356949 # number of memory reference insts executed -system.cpu0.iew.exec_branches 25556056 # Number of branches executed -system.cpu0.iew.exec_stores 18461073 # Number of stores executed -system.cpu0.iew.exec_rate 0.651133 # Inst execution rate -system.cpu0.iew.wb_sent 131168007 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 129236702 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 65950850 # num instructions producing a value -system.cpu0.iew.wb_consumers 106665798 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.638837 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618294 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9550008 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1593331 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 603744 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 195669003 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.643292 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.341136 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152467 # number of nop insts executed +system.cpu0.iew.exec_refs 42353114 # number of memory reference insts executed +system.cpu0.iew.exec_branches 25555008 # Number of branches executed +system.cpu0.iew.exec_stores 18458965 # Number of stores executed +system.cpu0.iew.exec_rate 0.651030 # Inst execution rate +system.cpu0.iew.wb_sent 131158694 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 129227262 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 65946343 # num instructions producing a value +system.cpu0.iew.wb_consumers 106655009 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.638733 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618315 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9548145 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1593081 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 603957 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 195669167 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.643258 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.340979 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 135299612 69.15% 69.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33411311 17.08% 86.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12639941 6.46% 92.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3246105 1.66% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4896411 2.50% 96.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2789558 1.43% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1311154 0.67% 98.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 556760 0.28% 99.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1518151 0.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 135298586 69.15% 69.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 33412613 17.08% 86.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12639367 6.46% 92.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3246710 1.66% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4896676 2.50% 96.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2794942 1.43% 98.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1306268 0.67% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 556762 0.28% 99.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1517243 0.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 195669003 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 103938440 # Number of instructions committed -system.cpu0.commit.committedOps 125872394 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 195669167 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 103932879 # Number of instructions committed +system.cpu0.commit.committedOps 125865777 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 40826228 # Number of memory references committed -system.cpu0.commit.loads 22662629 # Number of loads committed -system.cpu0.commit.membars 647252 # Number of memory barriers committed -system.cpu0.commit.branches 24954847 # Number of branches committed +system.cpu0.commit.refs 40823389 # Number of memory references committed +system.cpu0.commit.loads 22661090 # Number of loads committed +system.cpu0.commit.membars 647148 # Number of memory barriers committed +system.cpu0.commit.branches 24954311 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 109891295 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4835454 # Number of function calls committed. +system.cpu0.commit.int_insts 109885490 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4835541 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 84929206 67.47% 67.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 108853 0.09% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 84925464 67.47% 67.47% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 108825 0.09% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction @@ -873,762 +876,758 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8107 0.01% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8099 0.01% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22662629 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18163599 14.43% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 22661090 18.00% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18162299 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 125872394 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1518151 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 306287204 # The number of ROB reads -system.cpu0.rob.rob_writes 273994781 # The number of ROB writes -system.cpu0.timesIdled 123974 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3471595 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5449619957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 103816388 # Number of Instructions Simulated -system.cpu0.committedOps 125750342 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.948631 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.948631 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.513181 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.513181 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads -system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 125865777 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1517243 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 306278084 # The number of ROB reads +system.cpu0.rob.rob_writes 273977566 # The number of ROB writes +system.cpu0.timesIdled 123981 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3489819 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5449576943 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 103810827 # Number of Instructions Simulated +system.cpu0.committedOps 125743725 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.948911 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.948911 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.513107 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.513107 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 142709258 # number of integer regfile reads +system.cpu0.int_regfile_writes 81672792 # number of integer regfile writes system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads -system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes -system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 709828 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks. +system.cpu0.cc_regfile_reads 464864695 # number of cc regfile reads +system.cpu0.cc_regfile_writes 49723023 # number of cc regfile writes +system.cpu0.misc_regfile_reads 388122601 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1224736 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 709879 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.426037 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 37661762 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 710391 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 53.015539 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.426037 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.975441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361109 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361109 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 36442971 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 36442971 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 36751498 # number of overall hits -system.cpu0.dcache.overall_hits::total 36751498 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 646522 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 646522 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1887777 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1887777 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147802 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147802 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25065 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25065 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20108 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20108 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2534299 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2534299 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2682101 # number of overall misses -system.cpu0.dcache.overall_misses::total 2682101 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8646662000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8646662000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29876871349 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29876871349 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399690500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 399690500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484891000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 484891000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 240000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 240000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38523533349 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38523533349 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38523533349 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38523533349 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22101371 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22101371 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16875899 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16875899 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456329 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456329 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388131 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388131 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381217 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381217 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38977270 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38977270 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39433599 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39433599 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029253 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029253 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111862 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.111862 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323894 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323894 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064579 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064579 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052747 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052747 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065020 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065020 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068016 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.068016 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13374.118746 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13374.118746 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15826.483398 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15826.483398 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15946.159984 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15946.159984 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24114.332604 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24114.332604 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81162963 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81162963 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21452365 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21452365 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14987011 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14987011 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308699 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 308699 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363086 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363086 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361018 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361018 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 36439376 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 36439376 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 36748075 # number of overall hits +system.cpu0.dcache.overall_hits::total 36748075 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 646473 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 646473 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1887751 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1887751 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147620 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 147620 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25081 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25081 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20154 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20154 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2534224 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2534224 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2681844 # number of overall misses +system.cpu0.dcache.overall_misses::total 2681844 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8640238000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8640238000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29904279351 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29904279351 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399794500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 399794500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 485945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 390500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 390500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38544517351 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38544517351 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38544517351 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38544517351 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22098838 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22098838 # number of ReadReq accesses(hits+misses) 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accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39429919 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39429919 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029254 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029254 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111868 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.111868 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323502 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323502 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064614 # miss rate for LoadLockedReq accesses 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14363.192642 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1028 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4276317 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 201917 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.416667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21.178588 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 709828 # number of writebacks -system.cpu0.dcache.writebacks::total 709828 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 259036 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 259036 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563852 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1563852 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18553 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18553 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822888 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1822888 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822888 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1822888 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387486 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 387486 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323925 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323925 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101400 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101400 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6512 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6512 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20108 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20108 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 711411 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 711411 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 812811 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 812811 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31771 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60221 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4570691500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4570691500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6113916381 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6113916381 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664414000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664414000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102380000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102380000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464790000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464790000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 233000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 233000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10684607881 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10684607881 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12349021881 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12349021881 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621026500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621026500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621026500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621026500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017532 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017532 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222208 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222208 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052747 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052747 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018252 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018252 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020612 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020612 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11795.759073 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11795.759073 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18874.481380 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18874.481380 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16414.339250 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16414.339250 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15721.744472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15721.744472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23114.680724 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23114.680724 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15209.593687 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15209.593687 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14372.393529 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14372.393529 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4275244 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 201901 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.069767 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21.174952 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 709879 # number of writebacks +system.cpu0.dcache.writebacks::total 709879 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 258972 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 258972 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563802 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1563802 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18565 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18565 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822774 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1822774 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822774 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1822774 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387501 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 387501 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323949 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323949 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101413 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101413 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6516 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6516 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20154 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20154 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 711450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 711450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 812863 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 812863 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31772 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31772 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28451 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28451 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60223 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60223 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4575351000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4575351000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6134433385 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6134433385 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1666291000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1666291000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103051000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103051000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 465800500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 465800500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 381500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 381500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10709784385 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10709784385 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376075385 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12376075385 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621057500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621057500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017535 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017535 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222241 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222241 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016787 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016787 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052874 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052874 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018255 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018255 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020615 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020615 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11807.326949 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11807.326949 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18936.417106 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18936.417106 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16430.743593 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16430.743593 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15815.070595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15815.070595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23112.062122 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23112.062122 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1253795 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks. +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15053.460377 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15053.460377 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15225.290590 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15225.290590 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208392.845902 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208392.845902 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109942.339306 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109942.339306 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1252995 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.762307 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 71397425 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1253507 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.958138 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762307 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999536 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999536 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits -system.cpu0.icache.overall_hits::total 71396857 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1308156 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1308156 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1308156 # number of overall misses -system.cpu0.icache.overall_misses::total 1308156 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13216802476 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13216802476 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13216802476 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13216802476 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13216802476 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13216802476 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 72705013 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 72705013 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 72705013 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 72705013 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 72705013 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 72705013 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017993 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017993 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017993 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017993 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017993 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017993 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10103.384058 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10103.384058 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10103.384058 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10103.384058 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1586454 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 146662859 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 146662859 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 71397425 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 71397425 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 71397425 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 71397425 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 71397425 # number of overall hits +system.cpu0.icache.overall_hits::total 71397425 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1307231 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1307231 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1307231 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1307231 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1307231 # number of overall misses +system.cpu0.icache.overall_misses::total 1307231 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13217921463 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13217921463 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13217921463 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13217921463 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13217921463 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13217921463 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 72704656 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 72704656 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 72704656 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 72704656 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 72704656 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 72704656 # number of overall (read+write) accesses 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overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10111.389236 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1578280 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 112621 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 112202 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.086662 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.066416 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1253795 # number of writebacks -system.cpu0.icache.writebacks::total 1253795 # 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11994065954 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11994065954 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11994065954 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11994065954 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11993376465 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11993376465 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11993376465 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11993376465 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11993376465 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11993376465 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9561.969460 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017242 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017242 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9567.544653 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9567.544653 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9567.544653 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837427 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1839978 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2305 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 276743 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236878 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 277234 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16111.552153 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3276769 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 293338 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.170626 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.382075 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1413.670732 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.895209 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000987 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000084 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086284 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982564 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 303 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 375 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 295 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 469 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits 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-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398814 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 398814 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55484 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13243 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1201423 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 620115 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1890265 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55484 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13243 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1201423 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 620115 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1890265 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 413 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 554 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54992 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 54992 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20107 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20107 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14693.899751 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.282247 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.429995 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1405.940159 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.896844 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000689 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000026 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085812 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.983371 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1005 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id 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cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613220000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366568000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613189000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007982 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366599000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613220000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008254 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999964 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999964 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155926 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155926 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042142 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193237 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193237 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091515 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155984 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155984 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042593 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193770 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193770 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091953 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214872 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21102.169982 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59806.977641 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19406.413660 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.413660 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15556.497737 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15556.497737 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42895.951002 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42895.951002 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46654.909194 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24316.828228 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24316.828228 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34566.939827 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49057.182910 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.215216 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21136.602452 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60094.658138 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19414.471651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19414.471651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15555.078648 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15555.078648 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42865.667731 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42865.667731 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46298.252514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24357.983048 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24357.983048 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34500.278749 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49159.199531 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200389.285827 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190176.252372 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200383.954425 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190171.675054 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86629 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42593 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112544 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284127 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1254351 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576083 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3239 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3768469 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2609794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29242 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119275 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6526780 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160567216 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98579420 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105717.068230 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104596.526745 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4076758 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058809 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31269 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 324106 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 319070 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5036 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 113929 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1910818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28451 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28451 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 712670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1480466 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 204485 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 327834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86644 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42628 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112569 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 27 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287578 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284142 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1253548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576173 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3244 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3766063 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2610032 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29029 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119282 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6524406 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160464624 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98586020 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53124 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259423760 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1028398 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3154188 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.120549 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.330082 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 259327356 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1029792 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18816792 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3154811 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.120834 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.330795 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2778586 88.09% 88.09% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 370970 11.76% 99.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4632 0.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2778640 88.08% 88.08% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 371135 11.76% 99.84% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5036 0.16% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3154188 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4077816986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3154811 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4076288994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113410626 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113402059 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1885067918 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1883892360 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1231542700 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1231592300 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15872970 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15761972 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63417420 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63433401 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4689327 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2779312 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 269179 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2466051 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1570212 # Number of BTB hits +system.cpu1.branchPred.lookups 4691512 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2780704 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 269312 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2468444 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1570862 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 63.637741 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 878870 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7026 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 249224 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 213650 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 35574 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10610 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1658,89 +1657,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21410 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13903 95.52% 95.52% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 193 1.33% 96.85% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 240 1.65% 98.50% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.67% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 26 0.18% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 15 0.10% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14555 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5693 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11275.601616 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9954.937359 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6246.075100 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1927 33.85% 33.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3145 55.24% 89.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 429 7.54% 96.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 137 2.41% 99.03% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 17 0.30% 99.33% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 31 0.54% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21486 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21486 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8656 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5913 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6917 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14569 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 593.417530 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3219.344489 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13924 95.57% 95.57% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 239 1.64% 98.54% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 88 0.60% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.11% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.03% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 2 0.01% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14569 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5700 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11230.789474 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9917.122912 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6183.592938 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1944 34.11% 34.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3149 55.25% 89.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 398 6.98% 96.33% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 155 2.72% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 22 0.39% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.42% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5693 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 72606451764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.284045 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.454557 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 72584974764 99.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 16673000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 2243500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 1638500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 418000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 173000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walkCompletionTime::total 5700 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 72594020264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.245062 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.433850 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 72572506264 99.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 16659500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 2233500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 1798000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 337000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 155000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 118000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 72606451764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1957 73.85% 73.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 693 26.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2650 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21410 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walksPending::14-15 133000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 72594020264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1956 73.89% 73.89% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 691 26.11% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21486 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21410 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2650 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21486 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2650 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24133 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4195760 # DTB read hits -system.cpu1.dtb.read_misses 18440 # DTB read misses -system.cpu1.dtb.write_hits 3493575 # DTB write hits -system.cpu1.dtb.write_misses 2970 # DTB write misses +system.cpu1.dtb.read_hits 4198525 # DTB read hits +system.cpu1.dtb.read_misses 18524 # DTB read misses +system.cpu1.dtb.write_hits 3495808 # DTB write hits +system.cpu1.dtb.write_misses 2962 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1987 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1985 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 390 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4214200 # DTB read accesses -system.cpu1.dtb.write_accesses 3496545 # DTB write accesses +system.cpu1.dtb.read_accesses 4217049 # DTB read accesses +system.cpu1.dtb.write_accesses 3498770 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7689335 # DTB hits -system.cpu1.dtb.misses 21410 # DTB misses -system.cpu1.dtb.accesses 7710745 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7694333 # DTB hits +system.cpu1.dtb.misses 21486 # DTB misses +system.cpu1.dtb.accesses 7715819 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1770,58 +1770,62 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 5994 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 5231 97.28% 97.28% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 63 1.17% 98.46% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 36 0.67% 99.13% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 24 0.45% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.13% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 7 0.13% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5377 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11592.031425 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10629.889069 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5561.428024 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 316 17.73% 17.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1349 75.70% 93.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 63 3.54% 96.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.40% 98.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 19 1.07% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.17% 99.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16752128416 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.862615 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.344368 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2302152764 13.74% 13.74% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14449314652 86.25% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 661000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16752128416 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 990 84.98% 84.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 175 15.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 5992 # Table walker walks requested +system.cpu1.itb.walker.walksShort 5992 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2735 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2646 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 611 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5381 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 357.461438 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2249.604382 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 5186 96.38% 96.38% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.80% 97.18% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 39 0.72% 97.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.39% 98.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 21 0.39% 98.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 16 0.30% 98.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 17 0.32% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 9 0.17% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.11% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.04% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 6 0.11% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 3 0.06% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.07% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::30720-32767 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5381 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1781 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11779.618192 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10714.112038 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6875.589868 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1655 92.93% 92.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 93 5.22% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-49151 29 1.63% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-65535 1 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-81919 1 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-147455 2 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1781 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 16739710416 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.877376 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.328141 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2053443264 12.27% 12.27% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 14685521152 87.73% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 746000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 16739710416 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 995 85.04% 85.04% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 175 14.96% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1170 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5994 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5994 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5992 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5992 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7159 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 8253439 # ITB inst hits -system.cpu1.itb.inst_misses 5994 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1170 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1170 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7162 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 8257878 # ITB inst hits +system.cpu1.itb.inst_misses 5992 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1830,114 +1834,114 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1130 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1134 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses -system.cpu1.itb.hits 8253439 # DTB hits -system.cpu1.itb.misses 5994 # DTB misses -system.cpu1.itb.accesses 8259433 # DTB accesses -system.cpu1.numPwrStateTransitions 5525 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2763 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1016473602.620702 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25821981878.711128 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1969 71.26% 71.26% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 788 28.52% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 8263870 # ITB inst accesses +system.cpu1.itb.hits 8257878 # DTB hits +system.cpu1.itb.misses 5992 # DTB misses +system.cpu1.itb.accesses 8263870 # DTB accesses +system.cpu1.numPwrStateTransitions 5517 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2759 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1017941071.285973 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25840669198.429722 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1966 71.26% 71.26% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 787 28.52% 99.78% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959984667908 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2763 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 17443167459 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808516564041 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 34887121 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959984595936 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2759 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 17447990322 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808499415678 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 34896767 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 780426 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78816 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 28892 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 168872 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 301988 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23027 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8252257 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 107887 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 34136181 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.885084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.219625 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8573013 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 24834691 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4691512 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2663382 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 24575638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 780918 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78787 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 29336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 166978 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 305850 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23292 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8256698 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 107917 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2264 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 34143353 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.885357 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.219701 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20248194 59.32% 59.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4889749 14.32% 73.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1671087 4.90% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7327151 21.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20247760 59.30% 59.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4892921 14.33% 73.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1671892 4.90% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7330780 21.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 34136181 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.134414 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.711489 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7136711 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16890873 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8747772 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1097057 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 263768 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 709532 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129045 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 23428697 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1046505 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 263768 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8558773 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2377328 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11841982 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8401624 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2692706 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 22261726 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 187544 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 264330 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36982 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15461 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1675349 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 22265644 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 103648875 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 25648399 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 34143353 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.134440 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.711662 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7142387 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16886237 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8753269 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1097578 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 263882 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 709919 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 129188 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 23442151 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1047211 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 263882 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8565513 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2371212 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11834998 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8406528 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2701220 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 22274891 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 187368 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 265665 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37047 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 14963 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1683318 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 22278743 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 103710935 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 25664622 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 19867778 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2397866 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 407377 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 334219 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2894111 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4447920 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3797613 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 625649 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 631175 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21446441 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 559995 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21251983 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91992 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2044542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4726903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 43295 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 34136181 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.622565 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.949324 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 19882725 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2396018 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 407656 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 334437 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2896541 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4450446 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3799896 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 626454 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 628235 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21459278 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 560382 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21266552 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 92050 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2043308 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4721488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 43321 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 34143353 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.622861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.949388 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21624116 63.35% 63.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6146372 18.01% 81.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4248735 12.45% 93.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1859698 5.45% 99.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 257253 0.75% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 21621380 63.33% 63.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6152293 18.02% 81.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4252408 12.45% 93.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1859652 5.45% 99.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 257613 0.75% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -1945,44 +1949,44 @@ system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 34136181 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 34143353 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1435935 29.89% 29.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 668 0.01% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1614233 33.60% 63.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1753849 36.50% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1436712 29.87% 29.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 667 0.01% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1615148 33.58% 63.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1757949 36.54% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13143313 61.85% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28154 0.13% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 13152288 61.84% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 28200 0.13% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued @@ -2006,99 +2010,99 @@ system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Ty system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3291 0.02% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4401591 20.71% 82.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3675568 17.30% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4404606 20.71% 82.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3678091 17.30% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21251983 # Type of FU issued -system.cpu1.iq.rate 0.609164 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4804685 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226082 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 81530573 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24059081 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20789563 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6251 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2056 # Number of floating instruction queue writes +system.cpu1.iq.FU_type_0::total 21266552 # Type of FU issued +system.cpu1.iq.rate 0.609413 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4810476 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226199 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 81572724 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 24071099 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20803651 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6259 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 26052476 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4126 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87608 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 26072828 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4134 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87634 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 411817 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 594 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10183 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 255647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 411414 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10207 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 255357 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 40342 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 77877 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 40430 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 77958 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 263768 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 542908 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 100291 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22047493 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 263882 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 544522 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 96828 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 22060743 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4447920 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3797613 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 296998 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7633 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 86238 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10183 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 34861 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 119032 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 153893 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 21020629 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4306114 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 209967 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 4450446 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3799896 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 297241 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7639 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 82763 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10207 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 34804 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 119058 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 153862 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21034955 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4309085 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 210133 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41057 # number of nop insts executed -system.cpu1.iew.exec_refs 7931495 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3060021 # Number of branches executed -system.cpu1.iew.exec_stores 3625381 # Number of stores executed -system.cpu1.iew.exec_rate 0.602533 # Inst execution rate -system.cpu1.iew.wb_sent 20889464 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20791352 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10424214 # num instructions producing a value -system.cpu1.iew.wb_consumers 16342751 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.595961 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.637849 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1830942 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 516700 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142734 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 33726190 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.592855 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.351829 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41083 # number of nop insts executed +system.cpu1.iew.exec_refs 7936975 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3061868 # Number of branches executed +system.cpu1.iew.exec_stores 3627890 # Number of stores executed +system.cpu1.iew.exec_rate 0.602777 # Inst execution rate +system.cpu1.iew.wb_sent 20903580 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20805440 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10431521 # num instructions producing a value +system.cpu1.iew.wb_consumers 16355895 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.596200 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.637784 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1829884 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 517061 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 142735 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 33733433 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.593157 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.351929 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 24181138 71.70% 71.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5602280 16.61% 88.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1689893 5.01% 93.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 666101 1.98% 95.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 523339 1.55% 96.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 342031 1.01% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 220744 0.65% 98.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 118908 0.35% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 381756 1.13% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24180502 71.68% 71.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 5607484 16.62% 88.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1690092 5.01% 93.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 667448 1.98% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 524113 1.55% 96.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 341983 1.01% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 221163 0.66% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119335 0.35% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 381313 1.13% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 33726190 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 16334743 # Number of instructions committed -system.cpu1.commit.committedOps 19994748 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 33733433 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 16346571 # Number of instructions committed +system.cpu1.commit.committedOps 20009206 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 7578069 # Number of memory references committed -system.cpu1.commit.loads 4036103 # Number of loads committed -system.cpu1.commit.membars 208295 # Number of memory barriers committed -system.cpu1.commit.branches 2905369 # Number of branches committed +system.cpu1.commit.refs 7583571 # Number of memory references committed +system.cpu1.commit.loads 4039032 # Number of loads committed +system.cpu1.commit.membars 208429 # Number of memory barriers committed +system.cpu1.commit.branches 2907402 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17763800 # Number of committed integer instructions. -system.cpu1.commit.function_calls 462325 # Number of function calls committed. +system.cpu1.commit.int_insts 17776817 # Number of committed integer instructions. +system.cpu1.commit.function_calls 462681 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12386323 61.95% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 27065 0.14% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12395212 61.95% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 27122 0.14% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction @@ -2122,737 +2126,740 @@ system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3291 0.02% 62.10% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 62.10% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4036103 20.19% 82.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3541966 17.71% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4039032 20.19% 82.29% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3544539 17.71% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 19994748 # Class of committed instruction -system.cpu1.commit.bw_lim_events 381756 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 54190677 # The number of ROB reads -system.cpu1.rob.rob_writes 44052640 # The number of ROB writes -system.cpu1.timesIdled 55343 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 750940 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5616474700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 16301888 # Number of Instructions Simulated -system.cpu1.committedOps 19961893 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.140066 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.140066 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.467275 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.467275 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads -system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 20009206 # Class of committed instruction +system.cpu1.commit.bw_lim_events 381313 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 54211090 # The number of ROB reads +system.cpu1.rob.rob_writes 44079362 # The number of ROB writes +system.cpu1.timesIdled 55353 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 753414 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5616440201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 16313716 # Number of Instructions Simulated +system.cpu1.committedOps 19976351 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.139106 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.139106 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.467485 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.467485 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 23597502 # number of integer regfile reads +system.cpu1.int_regfile_writes 13487852 # number of integer regfile writes system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads -system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes -system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads -system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 189214 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy +system.cpu1.cc_regfile_reads 75515975 # number of cc regfile reads +system.cpu1.cc_regfile_writes 6821727 # number of cc regfile writes +system.cpu1.misc_regfile_reads 66067792 # number of misc regfile reads +system.cpu1.misc_regfile_writes 387520 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 189327 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.259638 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6803525 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 189662 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.871840 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 103705106000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.259638 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922382 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70537 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70537 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6546274 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6546274 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6595167 # number of overall hits -system.cpu1.dcache.overall_hits::total 6595167 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 215923 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 215923 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 399880 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 399880 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30250 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30250 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18610 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18610 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23458 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23458 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 615803 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 615803 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 646053 # number of overall misses -system.cpu1.dcache.overall_misses::total 646053 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3499498000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3499498000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10163021954 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10163021954 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366635500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 366635500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572131000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 572131000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1270000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1270000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13662519954 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13662519954 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13662519954 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13662519954 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3846750 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3846750 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3315327 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3315327 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79143 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79143 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96738 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96738 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93995 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93995 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7162077 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7162077 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7241220 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7241220 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056131 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.056131 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120616 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.120616 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249566 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249566 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085981 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085981 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089219 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.089219 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16207.157181 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16207.157181 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25415.179439 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25415.179439 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19700.994089 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19700.994089 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24389.589905 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24389.589905 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 15106665 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15106665 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3632818 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3632818 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2917516 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2917516 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48925 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48925 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78194 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78194 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70603 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70603 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6550334 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6550334 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6599259 # number of overall hits +system.cpu1.dcache.overall_hits::total 6599259 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 216356 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 216356 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 400081 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 400081 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30281 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30281 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18627 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18627 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23453 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23453 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 616437 # number of demand (read+write) misses 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495967500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96498000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96498000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548698000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548698000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1245000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1245000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4397697465 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4397697465 # number of demand (read+write) MSHR miss cycles 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-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027438 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365238 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365238 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249566 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249566 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031803 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031803 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22118.016042 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22118.016042 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21082.393648 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21082.393648 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 336 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1512378 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 40281 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.200000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.545692 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 189327 # number of writebacks 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demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 227933 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 256846 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256846 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2438 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2438 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5519 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5519 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1914813500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914813500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2474458965 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2474458965 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 498834500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 498834500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96515500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96515500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548354000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548354000 # number of StoreCondReq MSHR miss cycles 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uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442121000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035566 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027439 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027439 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365035 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365035 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055443 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055443 # mshr miss rate for LoadLockedReq accesses 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27258.307573 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17157.942988 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17157.942988 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17986.579683 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17986.579683 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23390.655640 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23390.655640 # average StoreCondReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.848160 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.848160 # average ReadReq mshr miss latency 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average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 585593 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19256.853834 # average overall mshr miss latency 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replacements +system.cpu1.icache.tags.tagsinuse 499.448153 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7647462 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 586855 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 13.031263 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79062638500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448153 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 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accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8251989 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8251989 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8251989 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8251989 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8251989 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073702 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073702 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073702 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073702 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073702 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073702 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9002.712520 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9002.712520 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9002.712520 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9002.712520 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 487413 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 41153 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.843924 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 585593 # number of writebacks -system.cpu1.icache.writebacks::total 585593 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22069 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22069 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22069 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22069 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22069 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22069 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586115 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 586115 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 586115 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 586115 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 586115 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 586115 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5018314097 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5018314097 # number of ReadReq MSHR miss cycles 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overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.tags.tag_accesses 17099739 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 17099739 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 7647462 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7647462 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7647462 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7647462 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7647462 # number of overall hits +system.cpu1.icache.overall_hits::total 7647462 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 608974 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 608974 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 608974 # number of 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cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.930353 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 977 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13602 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 835 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 128 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 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number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16755 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6229 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 570057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 128890 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 721931 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16755 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6229 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 570057 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 128890 # number of overall hits -system.cpu1.l2cache.overall_hits::total 721931 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 448 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 691 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29892 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29892 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23453 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23453 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34596 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34596 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16047 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 16047 # number of ReadCleanReq misses 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3031111997 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3704240497 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9860500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5063000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658205000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3031111997 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3704240497 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17203 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4458 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059631 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.830200 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 26728427 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 26728427 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16758 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6223 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 22981 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 115160 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 115160 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 648098 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 648098 # number of WritebackClean hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27344 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27344 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570840 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 570840 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101859 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 101859 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16758 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6223 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 570840 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 129203 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 723024 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16758 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6223 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 570840 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 129203 # number of overall hits +system.cpu1.l2cache.overall_hits::total 723024 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 453 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 249 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 702 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29938 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29938 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23451 # number of 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-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16661.301721 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16661.301721 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24260.714307 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28073.264587 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135579.272255 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133892.138365 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71200 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41639 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86222 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68548 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66385 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586115 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 251518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 256 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1758016 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 847991 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14492 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37672 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2658171 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74990240 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29751886 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174524 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15688.746439 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45067.816403 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16719.386733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16719.386733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15872.713317 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15872.713317 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1264000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1264000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34904.520758 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34904.520758 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35242.114796 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16647.638634 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16647.638634 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24286.916090 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28152.992215 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135484.582928 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133813.953488 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75634.716434 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75764.412811 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1659506 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 839728 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 183739 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180899 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 31691 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 827645 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 153507 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 660509 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 108712 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33822 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71296 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41636 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86274 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 68587 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66399 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586867 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 252106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 259 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1760267 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 848480 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14499 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37693 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2660939 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75086288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29768550 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68812 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 104836826 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 408149 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1234265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.169046 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.379975 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68844 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 104949570 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 408766 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5198376 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1235773 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.169662 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.381410 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1028032 83.29% 83.29% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 203819 16.51% 99.80% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2414 0.20% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1028949 83.26% 83.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 203984 16.51% 99.77% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2840 0.23% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1234265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1616622989 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1235773 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1618384496 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80296887 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80334899 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 880530739 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 381648033 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8035982 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20499963 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution @@ -2903,31 +2910,31 @@ system.iobus.pkt_size_system.bridge.master::total 162794 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40382501 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40384000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 328500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 582000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) @@ -2937,32 +2944,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6099000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6095500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33840000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187690100 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.555462 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255127474000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.555462 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909716 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909716 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2971,14 +2978,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32586377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32586377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303595229 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303595229 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4336181606 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4336181606 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4336181606 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4336181606 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32581877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32581877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4303830223 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4303830223 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4336412100 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4336412100 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4336412100 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4336412100 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2995,19 +3002,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129311.019841 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129311.019841 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.080306 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118805.080306 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118877.662189 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118877.662189 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129293.162698 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129293.162698 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118811.567552 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118811.567552 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118883.981248 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118883.981248 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3019,14 +3026,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19986377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19986377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490041664 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2490041664 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2510028041 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2510028041 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2510028041 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2510028041 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19981877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19981877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490259225 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2490259225 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2510241102 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2510241102 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2510241102 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2510241102 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3035,617 +3042,620 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 132778 # number of replacements -system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use -system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79293.162698 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79293.162698 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68746.113764 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68746.113764 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 132786 # number of replacements +system.l2c.tags.tagsinuse 63192.932289 # Cycle average of tags in use +system.l2c.tags.total_refs 445408 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 196622 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.265301 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065836 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8064.380543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2772.729395 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33768.581689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.679196 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1783.108864 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 674.072360 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2431.451744 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.208824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000250 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13716.070006 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.287927 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.059977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8086.686479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2783.200527 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33654.604995 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.598228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910717 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1777.688460 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 638.769137 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2513.055836 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.209291 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000249 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.123053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.515268 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.123393 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.513529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000070 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.027208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010286 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.037101 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964414 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29279 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34582 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 180 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5628 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23471 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6131058 # Number of tag accesses -system.l2c.tags.data_accesses 6131058 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4036 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 163 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 33190 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 46982 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46066 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 73 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 13227 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9835 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5456 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 155096 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 163 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 33190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51018 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46066 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 73 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 13227 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11214 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5456 # number of demand (read+write) hits -system.l2c.demand_hits::total 160511 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 163 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits -system.l2c.overall_hits::cpu0.inst 33190 # number of overall hits -system.l2c.overall_hits::cpu0.data 51018 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46066 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 73 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits -system.l2c.overall_hits::cpu1.inst 13227 # number of overall hits -system.l2c.overall_hits::cpu1.data 11214 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5456 # number of overall hits -system.l2c.overall_hits::total 160511 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8984 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2771 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11755 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1290 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11642 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8933 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 20575 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.027125 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009747 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038346 # Average percentage of cache occupancy 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blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27255 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.445023 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.528732 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6142016 # Number of tag accesses +system.l2c.tags.data_accesses 6142016 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 267222 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 267222 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32477 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2702 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 35179 # number of UpgradeReq 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(read+write) accesses +system.l2c.overall_accesses::cpu0.inst 53391 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 72019 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179245 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 75 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 39 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 16010 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 21161 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13840 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 356077 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.217723 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.506574 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.251383 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.241583 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.574124 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.391763 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.746064 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.868028 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.794306 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.120930 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036585 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367721 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.163898 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743039 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.080000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.051282 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176265 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.101121 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.597254 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.527675 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.120930 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.036585 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.367721 # miss rate for demand accesses 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miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743039 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.080000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.051282 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176265 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.470205 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.597254 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.546955 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1049.120478 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1057.858688 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1051.172437 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2330.781011 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 833.724570 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1339.979285 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102845.878908 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84468.891403 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 94902.376412 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99788.461538 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83121.606507 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90991.431670 # average ReadSharedReq miss latency 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96259.259259 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82871.007997 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 97727.640913 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109848.935181 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90833.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 93500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 86631.821403 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85616.783920 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134674.112751 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 105307.520086 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99788.461538 # average overall miss latency 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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182388.624878 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117695.609756 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167473.228663 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182383.088883 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117600.389864 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167459.688043 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96223.393849 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96220.306195 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65622.552574 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92322.603605 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 523570 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 298445 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 37951 # Transaction distribution -system.membus.trans_dist::ReadResp 212466 # Transaction distribution -system.membus.trans_dist::WriteReq 30885 # Transaction distribution -system.membus.trans_dist::WriteResp 30885 # Transaction distribution -system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution -system.membus.trans_dist::CleanEvict 17155 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 37954 # Transaction distribution +system.membus.trans_dist::ReadResp 212485 # Transaction distribution +system.membus.trans_dist::WriteReq 30889 # Transaction distribution +system.membus.trans_dist::WriteResp 30889 # Transaction distribution +system.membus.trans_dist::WritebackDirty 140037 # Transaction distribution +system.membus.trans_dist::CleanEvict 17084 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74884 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40573 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 40333 # Transaction distribution -system.membus.trans_dist::ReadExResp 20490 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174516 # Transaction distribution +system.membus.trans_dist::ReadExReq 40212 # Transaction distribution +system.membus.trans_dist::ReadExResp 20363 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174532 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661033 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782607 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 855668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 855556 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19151816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19342114 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19150328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19340658 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21660258 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122014 # Total snoops (count) -system.membus.snoop_fanout::samples 435296 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011884 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108364 # Request fanout histogram +system.membus.pkt_size::total 21658802 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122046 # Total snoops (count) +system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 435271 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011878 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108336 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430123 98.81% 98.81% # Request fanout histogram -system.membus.snoop_fanout::1 5173 1.19% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430101 98.81% 98.81% # Request fanout histogram +system.membus.snoop_fanout::1 5170 1.19% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 435296 # Request fanout histogram -system.membus.reqLayer0.occupancy 81593499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 435271 # Request fanout histogram +system.membus.reqLayer0.occupancy 81633500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11523000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1022470046 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1120816043 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1359381 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3677,80 +3687,81 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153354 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51065 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51065 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 447881 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4599 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241884 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315944 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1557828 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34423168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674082 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40097250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382843 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 858573 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.374933 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486434 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1014149 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 548985 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 155175 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21000 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 486750 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 371053 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 122899 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109975 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43571 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153546 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50842 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50842 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 448796 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4596 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1244094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315957 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1560051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34491784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674154 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40165938 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382861 # Total snoops (count) +system.toL2Bus.snoopTraffic 15835212 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 859470 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.375184 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486300 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 537636 62.62% 62.62% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 319967 37.27% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 970 0.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 537899 62.58% 62.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 320683 37.31% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 888 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 858573 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 885446562 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 859470 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 886309294 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 647873032 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 648979933 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 232753441 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 232794950 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1839 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2763 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2759 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index cf234591c..d07548930 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -124,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -162,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -218,12 +233,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -242,8 +262,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -266,9 +291,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -282,9 +312,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -560,12 +595,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -584,8 +624,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -643,9 +688,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -659,9 +709,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -672,12 +727,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -696,8 +756,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -705,10 +770,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -753,9 +823,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -769,12 +844,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -793,8 +873,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -802,10 +887,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -819,11 +909,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -868,6 +963,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -879,7 +975,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -922,10 +1022,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1006,14 +1111,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1022,13 +1132,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1109,10 +1224,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1192,17 +1312,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1228,13 +1353,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1242,14 +1372,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1335,14 +1470,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1351,13 +1491,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1366,13 +1511,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1380,11 +1530,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1398,11 +1553,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1416,12 +1576,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -1489,10 +1654,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1501,11 +1671,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1515,21 +1690,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1539,12 +1724,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1553,10 +1743,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1566,12 +1761,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1581,26 +1781,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1609,10 +1819,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1620,10 +1835,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1631,21 +1851,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1659,11 +1889,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1674,11 +1909,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1686,10 +1926,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index ab972f12d..2f947390d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -2,6 +2,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 76b741f0a..2736dcdd3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:35 -gem5 executing on phenom, pid 15973 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:25 +gem5 executing on e108600-lin, pid 23094 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2832862976500 because m5_exit instruction encountered +Exiting @ tick 2832894126500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5c309f807..ae5fa99bf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832863 # Number of seconds simulated -sim_ticks 2832862976500 # Number of ticks simulated -final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832894 # Number of seconds simulated +sim_ticks 2832894126500 # Number of ticks simulated +final_tick 2832894126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93807 # Simulator instruction rate (inst/s) -host_op_rate 113780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2349621266 # Simulator tick rate (ticks/s) -host_mem_usage 586720 # Number of bytes of host memory used -host_seconds 1205.67 # Real time elapsed on the host -sim_insts 113100501 # Number of instructions simulated -sim_ops 137180951 # Number of ops (including micro ops) simulated +host_inst_rate 74158 # Simulator instruction rate (inst/s) +host_op_rate 89946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1857289633 # Simulator tick rate (ticks/s) +host_mem_usage 579060 # Number of bytes of host memory used +host_seconds 1525.28 # Real time elapsed on the host +sim_insts 113111333 # Number of instructions simulated +sim_ops 137193850 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1321536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9400296 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8026368 # Number of bytes written to this memory +system.physmem.bytes_read::total 10724584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1321536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1321536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8031104 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8043892 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22878 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147146 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8048628 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147400 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 125412 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170339 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 125486 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129793 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 466095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3312564 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129867 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 466497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3318266 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3779563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 466095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2833306 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3785734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 466497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2834947 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2839492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2833306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 466095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3318750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2841133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2834947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 466497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3324452 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6619055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170065 # Number of read requests accepted -system.physmem.writeReqs 129793 # Number of write requests accepted -system.physmem.readBursts 170065 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129793 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10875840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 8056896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10707048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8043892 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6626867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170340 # Number of read requests accepted +system.physmem.writeReqs 129867 # Number of write requests accepted +system.physmem.readBursts 170340 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129867 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10892352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 8061056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10724648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8048628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11272 # Per bank write bursts -system.physmem.perBankRdBursts::1 10588 # Per bank write bursts -system.physmem.perBankRdBursts::2 10986 # Per bank write bursts -system.physmem.perBankRdBursts::3 11169 # Per bank write bursts -system.physmem.perBankRdBursts::4 12952 # Per bank write bursts -system.physmem.perBankRdBursts::5 9956 # Per bank write bursts -system.physmem.perBankRdBursts::6 10481 # Per bank write bursts -system.physmem.perBankRdBursts::7 10743 # Per bank write bursts -system.physmem.perBankRdBursts::8 10600 # Per bank write bursts -system.physmem.perBankRdBursts::9 10174 # Per bank write bursts -system.physmem.perBankRdBursts::10 10343 # Per bank write bursts -system.physmem.perBankRdBursts::11 9301 # Per bank write bursts -system.physmem.perBankRdBursts::12 10025 # Per bank write bursts -system.physmem.perBankRdBursts::13 11028 # Per bank write bursts -system.physmem.perBankRdBursts::14 10189 # Per bank write bursts -system.physmem.perBankRdBursts::15 10128 # Per bank write bursts -system.physmem.perBankWrBursts::0 8502 # Per bank write bursts -system.physmem.perBankWrBursts::1 7941 # Per bank write bursts -system.physmem.perBankWrBursts::2 8563 # Per bank write bursts -system.physmem.perBankWrBursts::3 8669 # Per bank write bursts -system.physmem.perBankWrBursts::4 7608 # Per bank write bursts -system.physmem.perBankWrBursts::5 7365 # Per bank write bursts -system.physmem.perBankWrBursts::6 7699 # Per bank write bursts -system.physmem.perBankWrBursts::7 7999 # Per bank write bursts -system.physmem.perBankWrBursts::8 7959 # Per bank write bursts -system.physmem.perBankWrBursts::9 7673 # Per bank write bursts -system.physmem.perBankWrBursts::10 7751 # Per bank write bursts -system.physmem.perBankWrBursts::11 6981 # Per bank write bursts -system.physmem.perBankWrBursts::12 7672 # Per bank write bursts -system.physmem.perBankWrBursts::13 8384 # Per bank write bursts -system.physmem.perBankWrBursts::14 7646 # Per bank write bursts -system.physmem.perBankWrBursts::15 7477 # Per bank write bursts +system.physmem.perBankRdBursts::0 11036 # Per bank write bursts +system.physmem.perBankRdBursts::1 10507 # Per bank write bursts +system.physmem.perBankRdBursts::2 10862 # Per bank write bursts +system.physmem.perBankRdBursts::3 11068 # Per bank write bursts +system.physmem.perBankRdBursts::4 13101 # Per bank write bursts +system.physmem.perBankRdBursts::5 10327 # Per bank write bursts +system.physmem.perBankRdBursts::6 10639 # Per bank write bursts +system.physmem.perBankRdBursts::7 10985 # Per bank write bursts +system.physmem.perBankRdBursts::8 10460 # Per bank write bursts +system.physmem.perBankRdBursts::9 10167 # Per bank write bursts +system.physmem.perBankRdBursts::10 10435 # Per bank write bursts +system.physmem.perBankRdBursts::11 9511 # Per bank write bursts +system.physmem.perBankRdBursts::12 9930 # Per bank write bursts +system.physmem.perBankRdBursts::13 10756 # Per bank write bursts +system.physmem.perBankRdBursts::14 10401 # Per bank write bursts +system.physmem.perBankRdBursts::15 10008 # Per bank write bursts +system.physmem.perBankWrBursts::0 8291 # Per bank write bursts +system.physmem.perBankWrBursts::1 7865 # Per bank write bursts +system.physmem.perBankWrBursts::2 8399 # Per bank write bursts +system.physmem.perBankWrBursts::3 8558 # Per bank write bursts +system.physmem.perBankWrBursts::4 7751 # Per bank write bursts +system.physmem.perBankWrBursts::5 7713 # Per bank write bursts +system.physmem.perBankWrBursts::6 7781 # Per bank write bursts +system.physmem.perBankWrBursts::7 8111 # Per bank write bursts +system.physmem.perBankWrBursts::8 7871 # Per bank write bursts +system.physmem.perBankWrBursts::9 7662 # Per bank write bursts +system.physmem.perBankWrBursts::10 7844 # Per bank write bursts +system.physmem.perBankWrBursts::11 7196 # Per bank write bursts +system.physmem.perBankWrBursts::12 7582 # Per bank write bursts +system.physmem.perBankWrBursts::13 8119 # Per bank write bursts +system.physmem.perBankWrBursts::14 7846 # Per bank write bursts +system.physmem.perBankWrBursts::15 7365 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 2832862744500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 2832893894500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166513 # Read request sizes (log2) +system.physmem.readPktSize::6 166788 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125412 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 728 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125486 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,162 +160,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.784899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.937223 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.895489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23052 37.23% 37.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14889 24.05% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6490 10.48% 71.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3653 5.90% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2551 4.12% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1649 2.66% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1497 2.42% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1106 1.79% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7028 11.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61915 # Bytes accessed per row activation +system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 305.167515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.813202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.494619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23016 37.06% 37.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15104 24.32% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6524 10.50% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3665 5.90% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2528 4.07% 81.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1637 2.64% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1479 2.38% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1102 1.77% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7053 11.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62108 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.666884 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.620654 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.706936 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.623530 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.496418 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.503929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.596363 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5449 88.72% 88.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 115 1.87% 90.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.46% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 44 0.72% 91.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 34 0.55% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 18 0.29% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 53 0.86% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.11% 93.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 141 2.30% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.18% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.13% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 63 1.03% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.11% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.41% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 94 1.53% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.507001 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.506831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.607971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5435 88.49% 88.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 129 2.10% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.50% 91.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 49 0.80% 91.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.52% 92.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.28% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 48 0.78% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.23% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 140 2.28% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.18% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.13% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.13% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 65 1.06% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.34% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 93 1.51% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.18% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads -system.physmem.totQLat 2126742000 # Total ticks spent queuing -system.physmem.totMemAccLat 5313023250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849675000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12515.03 # Average queueing delay per DRAM burst +system.physmem.totQLat 2108320500 # Total ticks spent queuing +system.physmem.totMemAccLat 5299439250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850965000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12387.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31265.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31137.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing -system.physmem.readRowHits 139707 # Number of row buffer hits during reads -system.physmem.writeRowHits 94201 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.82 # Row buffer hit rate for writes -system.physmem.avgGap 9447347.56 # Average gap between requests -system.physmem.pageHitRate 79.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242207280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132156750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 687546600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 416962080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83427429555 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626531651000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896466320945 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.453835 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705741524500 # Time in different power states -system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states +system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing +system.physmem.readRowHits 139937 # Number of row buffer hits during reads +system.physmem.writeRowHits 94101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 9436468.49 # Average gap between requests +system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 243454680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132837375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 690495000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 417759120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83647548450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626357251250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896519747795 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.465335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705450093000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32519220500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32840757000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225870120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123242625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 637938600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398798640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82153488960 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.365771 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states -system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states +system.physmem_1.actEnergy 226081800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123358125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 637002600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398422800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82216233135 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627612791000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896244291380 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.368099 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2707556632500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30741160500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -328,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46806016 # Number of BP lookups -system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1175497 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29454915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13525299 # Number of BTB hits +system.cpu.branchPred.lookups 46812529 # Number of BP lookups +system.cpu.branchPred.condPredicted 23980713 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1174980 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29461889 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13525990 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 45.910125 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11726513 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 34925 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7916092 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7770128 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 145964 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60126 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,81 +383,82 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 72368 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 51295 97.51% 97.51% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 909 1.73% 99.24% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 317 0.60% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 17 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 72186 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72186 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29334 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23181 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19671 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52515 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 467.713986 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2821.743931 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-8191 51203 97.50% 97.50% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-24575 322 0.61% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-32767 40 0.08% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-40959 18 0.03% 99.95% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52603 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17713 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8411.296807 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17487 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 220 1.24% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17713 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131327462316 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.619046 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.492812 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131267362816 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 40987500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 8789000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6827500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1022500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 578500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1418000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 467000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 52515 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17658 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8522.119991 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17438 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 214 1.21% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17658 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131358619316 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629965 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.490082 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131298865316 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 40695500 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 8747000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6751500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1053500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 584000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1412000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131327462316 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6375 82.60% 82.60% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1343 17.40% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7718 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72368 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131358619316 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6349 82.25% 82.25% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1370 17.75% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7719 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72186 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72186 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7719 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7719 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79905 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25410890 # DTB read hits -system.cpu.dtb.read_misses 62740 # DTB read misses -system.cpu.dtb.write_hits 19865163 # DTB write hits -system.cpu.dtb.write_misses 9628 # DTB write misses +system.cpu.dtb.read_hits 25413003 # DTB read hits +system.cpu.dtb.read_misses 62542 # DTB read misses +system.cpu.dtb.write_hits 19866296 # DTB write hits +system.cpu.dtb.write_misses 9644 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 366 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2075 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25473630 # DTB read accesses -system.cpu.dtb.write_accesses 19874791 # DTB write accesses +system.cpu.dtb.perms_faults 1321 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25475545 # DTB read accesses +system.cpu.dtb.write_accesses 19875940 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45276053 # DTB hits -system.cpu.dtb.misses 72368 # DTB misses -system.cpu.dtb.accesses 45348421 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45279299 # DTB hits +system.cpu.dtb.misses 72186 # DTB misses +system.cpu.dtb.accesses 45351485 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,58 +488,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 12817 # Table walker walks requested system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3407 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7692 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 10511 94.70% 94.70% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 118 1.06% 95.77% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 237 2.14% 97.90% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.01% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 46 0.41% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 742.229030 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 3116.397220 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.79% 94.79% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 119 1.07% 95.86% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 227 2.05% 97.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.02% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 47 0.42% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 5044 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12037.073751 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9689.647863 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7634.465398 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 4079 80.87% 80.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 946 18.75% 99.62% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::samples 5040 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12026.488095 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9684.197840 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7608.176186 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 4071 80.77% 80.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 955 18.95% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-49151 11 0.22% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 5044 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23953217916 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.646337 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.478297 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 8473460000 35.38% 35.38% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 15477752916 64.62% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 1917000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 5040 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23984374916 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.642154 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.479545 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 8584682500 35.79% 35.79% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 15397812416 64.20% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 1792000 0.01% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23953217916 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2992 89.96% 89.96% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 334 10.04% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 23984374916 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2987 89.92% 89.92% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 16143 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 65995629 # ITB inst hits +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 16139 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 65982481 # ITB inst hits system.cpu.itb.inst_misses 12817 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -546,112 +549,112 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3021 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2147 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66008446 # ITB inst accesses -system.cpu.itb.hits 65995629 # DTB hits +system.cpu.itb.inst_accesses 65995298 # ITB inst accesses +system.cpu.itb.hits 65982481 # DTB hits system.cpu.itb.misses 12817 # DTB misses -system.cpu.itb.accesses 66008446 # DTB accesses +system.cpu.itb.accesses 65995298 # DTB accesses system.cpu.numPwrStateTransitions 6074 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 886948130.312150 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17421700028.084686 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499972891000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 278423951 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 139232654742 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 278465363 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104979858 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184015649 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46812529 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33022631 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 161497089 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6057652 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 189263 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8972 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337056 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 558097 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65981271 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1027864 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6246 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 270599333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.829251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.216918 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171686790 63.45% 63.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29154260 10.77% 74.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14034299 5.19% 79.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55723984 20.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18530 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30752508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150221263 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 676943612 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 163957736 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10899 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141737618 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8483639 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2839333 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2643784 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13883095 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26339486 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21214202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1704469 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14294324 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 270599333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168109 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.660821 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77964907 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 121895477 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64303176 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3866825 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2568948 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3406986 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 467982 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 156982730 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3511045 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2568948 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83721940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11815597 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76560081 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62413108 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33519659 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146432544 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 918349 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 465966 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65322 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 18586 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30762818 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150226924 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 676971311 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 163962292 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10893 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141750491 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8476427 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2839737 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2644396 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13885386 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26339908 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21214343 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1703941 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2126584 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143224778 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2118002 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143047064 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 260478 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8148926 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14278560 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121950 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270599333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.528631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.865147 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182394036 67.40% 67.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45259787 16.73% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31866202 11.78% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10262392 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 816883 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -659,9 +662,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270599333 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7342152 32.76% 32.76% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available @@ -690,13 +693,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5623214 25.10% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9441955 42.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5622313 25.09% 57.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9444091 42.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95844496 67.01% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114325 0.08% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95850690 67.01% 67.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114288 0.08% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued @@ -720,99 +723,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8577 0.01% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26130891 18.27% 85.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20940281 14.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued -system.cpu.iq.rate 0.513744 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses +system.cpu.iq.FU_type_0::total 143047064 # Type of FU issued +system.cpu.iq.rate 0.513698 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22408588 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156652 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 579326888 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153497201 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 139997351 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35639 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165429916 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 323958 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1435915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 710 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18680 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 623667 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1433781 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 712 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18665 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 622043 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88637 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6231 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88844 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6344 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2569037 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1239960 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 546279 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145517187 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2568948 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1241907 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 544667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145523405 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26339486 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21214202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1094236 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 509843 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18680 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 277456 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471588 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 749044 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142138491 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25734027 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 827925 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26339908 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21214343 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1094304 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17849 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 508298 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18665 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 277238 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471000 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 748238 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142148555 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25736254 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 826428 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180634 # number of nop insts executed -system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed -system.cpu.iew.exec_branches 26490215 # Number of branches executed -system.cpu.iew.exec_stores 20827406 # Number of stores executed -system.cpu.iew.exec_rate 0.510511 # Inst execution rate -system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63237137 # num instructions producing a value -system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value -system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180625 # number of nop insts executed +system.cpu.iew.exec_refs 46564673 # number of memory reference insts executed +system.cpu.iew.exec_branches 26492434 # Number of branches executed +system.cpu.iew.exec_stores 20828419 # Number of stores executed +system.cpu.iew.exec_rate 0.510471 # Inst execution rate +system.cpu.iew.wb_sent 141779361 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140008720 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63240555 # num instructions producing a value +system.cpu.iew.wb_consumers 95712709 # num instructions consuming a value +system.cpu.iew.wb_rate 0.502787 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660733 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7366290 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1996052 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 715102 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267708008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513054 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.118068 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194252968 72.56% 72.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43305040 16.18% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15457612 5.77% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4371808 1.63% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6428406 2.40% 98.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1610065 0.60% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 797962 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 411830 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1072317 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113255406 # Number of instructions committed -system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267708008 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113266238 # Number of instructions committed +system.cpu.commit.committedOps 137348755 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45494106 # Number of memory references committed -system.cpu.commit.loads 24903571 # Number of loads committed -system.cpu.commit.membars 814876 # Number of memory barriers committed -system.cpu.commit.branches 26023568 # Number of branches committed +system.cpu.commit.refs 45498427 # Number of memory references committed +system.cpu.commit.loads 24906127 # Number of loads committed +system.cpu.commit.membars 814995 # Number of memory barriers committed +system.cpu.commit.branches 26026646 # Number of branches committed system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120163713 # Number of committed integer instructions. -system.cpu.commit.function_calls 4884102 # Number of function calls committed. +system.cpu.commit.int_insts 120175202 # Number of committed integer instructions. +system.cpu.commit.function_calls 4885014 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91720354 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91728959 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112792 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -836,544 +839,544 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8577 0.01% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24903571 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24906127 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20592300 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction -system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389119868 # The number of ROB reads -system.cpu.rob.rob_writes 292294903 # The number of ROB writes -system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113100501 # Number of Instructions Simulated -system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads -system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155524954 # number of integer regfile reads -system.cpu.int_regfile_writes 88488761 # number of integer regfile writes -system.cpu.fp_regfile_reads 9529 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137348755 # Class of committed instruction +system.cpu.commit.bw_lim_events 1072317 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389160423 # The number of ROB reads +system.cpu.rob.rob_writes 292308325 # The number of ROB writes +system.cpu.timesIdled 890756 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7866030 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387322891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113111333 # Number of Instructions Simulated +system.cpu.committedOps 137193850 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.461870 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.461870 # CPI: Total CPI of All Threads +system.cpu.ipc 0.406195 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.406195 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155535200 # number of integer regfile reads +system.cpu.int_regfile_writes 88495253 # number of integer regfile writes +system.cpu.fp_regfile_reads 9528 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads -system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes -system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 838747 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 502191757 # number of cc regfile reads +system.cpu.cc_regfile_writes 53133619 # number of cc regfile writes +system.cpu.misc_regfile_reads 459496628 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521804 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 838109 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.925913 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40060330 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838621 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.769290 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.925913 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 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-system.cpu.dcache.WriteReq_misses::total 3607427 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177712 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177712 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 27363 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 27363 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179138470 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179138470 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23266826 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23266826 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542812 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542812 # number of WriteReq hits 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number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376308000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 376308000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 275000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 275000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 244375541692 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 244375541692 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 244375541692 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 244375541692 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23971033 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23971033 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19151419 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19151419 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523388 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523388 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468724 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468724 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460392 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460392 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43122452 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43122452 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43645840 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43645840 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029377 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029377 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188425 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188425 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339142 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339142 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058070 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100015 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100015 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102888 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102888 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16608.729688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16608.729688 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64446.980548 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.728794 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.728794 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55200 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55200 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56625.090682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56625.090682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.033598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54384.033598 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 871366 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.100013 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100013 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 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# average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56662.666577 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54422.781664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54422.781664 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 867732 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6856 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6871 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.095391 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 126.289041 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 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overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 833584 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713573 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713573 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 833015 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 833015 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26360397972 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26360397972 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28060310972 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28060310972 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276272000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276272000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276272000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276272000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015661 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015661 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228440 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228440 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018088 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018088 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6383877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6383877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19987260971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19987260971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1693165000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1693165000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126972500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126972500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 270000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26371138471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26371138471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064303471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28064303471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276254500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276254500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276254500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276254500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015665 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015665 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228209 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228209 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016559 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016559 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019100 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019100 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15422.073281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15422.073281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66600.233644 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66600.233644 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.123311 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.123311 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14983.604624 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14983.604624 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54200 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54200 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1886245 # number of replacements -system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1886757 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.927749 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016548 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016548 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019086 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019086 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15436.213171 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15436.213171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66622.426639 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66622.426639 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14175.624990 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1886431 # number of replacements +system.cpu.icache.tags.tagsinuse 511.154202 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64000082 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1886943 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.917337 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.154077 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.154202 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses -system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64013417 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64013417 # number of overall hits -system.cpu.icache.overall_hits::total 64013417 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1977977 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1977977 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1977977 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1977977 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1977977 # number of overall misses -system.cpu.icache.overall_misses::total 1977977 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28160163493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28160163493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28160163493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28160163493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28160163493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28160163493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65991394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65991394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65991394 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65991394 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65991394 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65991394 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029973 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029973 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029973 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029973 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029973 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029973 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.850829 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14236.850829 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14236.850829 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14236.850829 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6440 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 67865267 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67865267 # Number of data accesses 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+system.cpu.icache.overall_misses::total 1978185 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28158737492 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28158737492 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28158737492 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28158737492 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28158737492 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28158737492 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65978267 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65978267 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65978267 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65978267 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65978267 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65978267 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029982 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029982 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029982 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029982 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029982 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029982 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14234.633006 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14234.633006 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887147000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227214500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887129500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227197000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887147000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6227214500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000356 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.977706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.977706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887129500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6227197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000401 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.978617 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.978617 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455857 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455857 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010539 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024401 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024401 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060313 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060313 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127100 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68021.515263 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68021.515263 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119959.917496 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122544.732361 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456516 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.456516 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010548 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024468 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024468 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060426 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060426 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129553.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.381646 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.381646 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119832.402626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119832.402626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122449.228910 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122449.228910 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124710.607777 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124710.607777 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.418260 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.538849 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100267.900330 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.217396 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5483160 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757544 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 128619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557060 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 821637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1886431 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 149968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2806 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 542244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 541532 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665772 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640441 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8471013 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241517552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98498985 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5666337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2638583 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30857 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133499 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8469276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241541168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98417449 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340297169 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194360 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3054889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.024700 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.155211 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 231212 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340238093 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 194794 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 8145576 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3054607 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.024758 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.155386 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2979432 97.53% 97.53% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 75457 2.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2978982 97.52% 97.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 75625 2.48% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3054889 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5401923998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3054607 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5400960498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2834452098 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1304519551 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18799483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75755880 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30172 # Transaction distribution system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1570,66 +1574,66 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43093500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 43088500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 652000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 651500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33076500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33063500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187162988 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187149991 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.005857 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256506730000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005857 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062866 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062866 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328023 # Number of tag accesses system.iocache.tags.data_accesses 328023 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses system.iocache.ReadReq_misses::total 223 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1638,14 +1642,14 @@ system.iocache.demand_misses::realview.ide 36447 # system.iocache.demand_misses::total 36447 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36447 # number of overall misses system.iocache.overall_misses::total 36447 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28153877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28153877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4551268111 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4551268111 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4579421988 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4579421988 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4579421988 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4579421988 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28156877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28156877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4551348114 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4551348114 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4579504991 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4579504991 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4579504991 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4579504991 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1662,14 +1666,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126250.569507 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126250.569507 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125642.339637 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125642.339637 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125646.061075 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125646.061075 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126264.022422 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125648.338437 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125648.338437 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1686,14 +1690,14 @@ system.iocache.demand_mshr_misses::realview.ide 36447 system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17003877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17003877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738656099 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2738656099 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2755659976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2755659976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2755659976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2755659976 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17006877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17006877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738747578 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2738747578 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2755754455 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2755754455 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2755754455 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2755754455 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1702,83 +1706,84 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34132 # Transaction distribution -system.membus.trans_dist::ReadResp 67490 # Transaction distribution +system.membus.trans_dist::ReadResp 67530 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::WritebackDirty 125412 # Transaction distribution -system.membus.trans_dist::CleanEvict 7777 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4588 # Transaction distribution +system.membus.trans_dist::WritebackDirty 125486 # Transaction distribution +system.membus.trans_dist::CleanEvict 7993 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4611 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 133639 # Transaction distribution -system.membus.trans_dist::ReadExResp 133639 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33359 # Transaction distribution +system.membus.trans_dist::ReadExReq 133874 # Transaction distribution +system.membus.trans_dist::ReadExResp 133874 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33399 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558073 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 451368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558936 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 630948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 631811 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16433756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16597145 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16456092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16619481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18914265 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18936601 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 487 # Total snoops (count) -system.membus.snoop_fanout::samples 402739 # Request fanout histogram +system.membus.snoopTraffic 31040 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 403324 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402739 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 403324 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402739 # Request fanout histogram -system.membus.reqLayer0.occupancy 83678000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 403324 # Request fanout histogram +system.membus.reqLayer0.occupancy 83656500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1737499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1736499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 875953366 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 876921354 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 978576250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 979994750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1810,29 +1815,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 9d9d131ca..25914c016 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -107,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -125,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -146,12 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -170,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -194,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -210,9 +240,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -223,12 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -247,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -306,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -322,9 +372,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -339,6 +394,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -356,6 +412,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -384,9 +444,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -400,9 +465,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.isa] @@ -455,9 +525,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -471,9 +546,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -491,6 +571,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -535,12 +616,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=true system=system +threadPolicy=RoundRobin tracer=system.cpu2.tracer workload= @@ -586,9 +672,14 @@ walker=system.cpu2.dstage2_mmu.stage2_tlb.walker [system.cpu2.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.dtb] @@ -602,9 +693,14 @@ walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.executeFuncUnits] @@ -1040,9 +1136,14 @@ walker=system.cpu2.istage2_mmu.stage2_tlb.walker [system.cpu2.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.itb] @@ -1056,9 +1157,14 @@ walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.tracer] @@ -1089,6 +1195,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -1127,6 +1234,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -1196,9 +1307,14 @@ walker=system.cpu3.dstage2_mmu.stage2_tlb.walker [system.cpu3.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.dtb] @@ -1212,9 +1328,14 @@ walker=system.cpu3.dtb.walker [system.cpu3.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.fuPool] @@ -1574,9 +1695,14 @@ walker=system.cpu3.istage2_mmu.stage2_tlb.walker [system.cpu3.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.itb] @@ -1590,9 +1716,14 @@ walker=system.cpu3.itb.walker [system.cpu3.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.tracer] @@ -1623,9 +1754,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1639,12 +1775,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1663,8 +1804,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1675,12 +1821,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1699,8 +1850,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -1708,10 +1864,15 @@ size=4194304 type=CoherentXBar children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 @@ -1725,11 +1886,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1781,6 +1947,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1792,7 +1959,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1835,10 +2006,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1919,14 +2095,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1935,13 +2116,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -2022,10 +2208,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -2105,17 +2296,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -2141,13 +2337,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -2155,14 +2356,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2248,14 +2454,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2264,13 +2475,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2279,13 +2495,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2293,11 +2514,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2311,11 +2537,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2329,12 +2560,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -2402,10 +2638,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2414,11 +2655,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2428,21 +2674,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2452,12 +2708,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2466,10 +2727,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2479,12 +2745,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2494,26 +2765,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2522,10 +2803,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2533,10 +2819,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2544,21 +2835,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2572,11 +2873,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2587,11 +2893,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2599,10 +2910,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2618,10 +2934,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index e34805b0d..3ab4a9e43 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -2,6 +2,10 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR @@ -31,6 +35,9 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: ClockedObject: Already in the requested power state, request ignored +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] @@ -38,22 +45,22 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +WARNING: Bank is already active! +Command: 0, Timestamp: 10945, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 10462, Bank: 2 -warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 10621, Bank: 7 -WARNING: Bank is already active! -Command: 0, Timestamp: 11318, Bank: 7 +Command: 0, Timestamp: 11030, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr @@ -65,8 +72,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 8588, Bank: 0 warn: CP14 unimplemented crn[10], opc1[0], crm[4], opc2[3] warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -86,12 +93,13 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2] warn: instruction 'mcr bpiall' unimplemented warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -100,20 +108,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -124,3 +126,11 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index c39f9b6f7..ff911276c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:52:46 -gem5 executing on phenom, pid 15993 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:25 +gem5 executing on e108600-lin, pid 23095 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3d5089040..58986be27 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,173 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823729 # Number of seconds simulated -sim_ticks 2823728611500 # Number of ticks simulated -final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823751 # Number of seconds simulated +sim_ticks 2823750824500 # Number of ticks simulated +final_tick 2823750824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236626 # Simulator instruction rate (inst/s) -host_op_rate 287030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5437492370 # Simulator tick rate (ticks/s) -host_mem_usage 592088 # Number of bytes of host memory used -host_seconds 519.31 # Real time elapsed on the host -sim_insts 122881667 # Number of instructions simulated -sim_ops 149056790 # Number of ops (including micro ops) simulated +host_inst_rate 186823 # Simulator instruction rate (inst/s) +host_op_rate 226618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4292269892 # Simulator tick rate (ticks/s) +host_mem_usage 585968 # Number of bytes of host memory used +host_seconds 657.87 # Real time elapsed on the host +sim_insts 122905142 # Number of instructions simulated +sim_ops 149084969 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 538276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3140708 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 542180 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3155236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 897088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 122688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 900352 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 339840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2003776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 341632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1990912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4736 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 386816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3512832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 381248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3510400 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10950024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 538276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 339840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 386816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10952712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 542180 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 122688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 341632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 381248 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1387748 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8235776 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8236736 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8253300 # Number of bytes written to this memory +system.physmem.bytes_written::total 8254260 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 49593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 49820 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 70 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 74 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 54888 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 54850 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180067 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128684 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180109 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128699 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133065 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133080 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1112256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 192007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1117392 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 317696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 318850 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 120352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 709621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 120985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 705059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1677 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 136988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1244040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 135015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1243169 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3877860 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190626 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43494 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 120352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 136988 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2916632 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3878781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 120985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 135015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2916949 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2922838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2916632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2923155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2916949 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1118462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1123598 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 317696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 318850 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 120352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 709621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 120985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 705059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1677 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 136988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1244040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 135015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1243169 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6800697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 113588 # Number of read requests accepted -system.physmem.writeReqs 68931 # Number of write requests accepted -system.physmem.readBursts 113588 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 68931 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7262464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 4410816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7269632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4411584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6801936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 113342 # Number of read requests accepted +system.physmem.writeReqs 68762 # Number of write requests accepted +system.physmem.readBursts 113342 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 68762 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7247168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 4399872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7253888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4400768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7537 # Per bank write bursts -system.physmem.perBankRdBursts::1 6789 # Per bank write bursts -system.physmem.perBankRdBursts::2 7399 # Per bank write bursts -system.physmem.perBankRdBursts::3 7485 # Per bank write bursts -system.physmem.perBankRdBursts::4 7337 # Per bank write bursts -system.physmem.perBankRdBursts::5 7010 # Per bank write bursts -system.physmem.perBankRdBursts::6 7617 # Per bank write bursts -system.physmem.perBankRdBursts::7 7715 # Per bank write bursts +system.physmem.perBankRdBursts::0 7506 # Per bank write bursts +system.physmem.perBankRdBursts::1 6787 # Per bank write bursts +system.physmem.perBankRdBursts::2 7407 # Per bank write bursts +system.physmem.perBankRdBursts::3 7543 # Per bank write bursts +system.physmem.perBankRdBursts::4 7335 # Per bank write bursts +system.physmem.perBankRdBursts::5 7022 # Per bank write bursts +system.physmem.perBankRdBursts::6 7619 # Per bank write bursts +system.physmem.perBankRdBursts::7 7707 # Per bank write bursts system.physmem.perBankRdBursts::8 6869 # Per bank write bursts -system.physmem.perBankRdBursts::9 7528 # Per bank write bursts -system.physmem.perBankRdBursts::10 7086 # Per bank write bursts -system.physmem.perBankRdBursts::11 6373 # Per bank write bursts +system.physmem.perBankRdBursts::9 7531 # Per bank write bursts +system.physmem.perBankRdBursts::10 6987 # Per bank write bursts +system.physmem.perBankRdBursts::11 6354 # Per bank write bursts system.physmem.perBankRdBursts::12 6401 # Per bank write bursts -system.physmem.perBankRdBursts::13 7208 # Per bank write bursts -system.physmem.perBankRdBursts::14 6839 # Per bank write bursts -system.physmem.perBankRdBursts::15 6283 # Per bank write bursts -system.physmem.perBankWrBursts::0 4402 # Per bank write bursts -system.physmem.perBankWrBursts::1 3960 # Per bank write bursts -system.physmem.perBankWrBursts::2 4483 # Per bank write bursts -system.physmem.perBankWrBursts::3 4623 # Per bank write bursts -system.physmem.perBankWrBursts::4 4313 # Per bank write bursts -system.physmem.perBankWrBursts::5 4310 # Per bank write bursts -system.physmem.perBankWrBursts::6 4616 # Per bank write bursts -system.physmem.perBankWrBursts::7 4482 # Per bank write bursts -system.physmem.perBankWrBursts::8 4162 # Per bank write bursts +system.physmem.perBankRdBursts::13 7189 # Per bank write bursts +system.physmem.perBankRdBursts::14 6831 # Per bank write bursts +system.physmem.perBankRdBursts::15 6149 # Per bank write bursts +system.physmem.perBankWrBursts::0 4366 # Per bank write bursts +system.physmem.perBankWrBursts::1 3966 # Per bank write bursts +system.physmem.perBankWrBursts::2 4487 # Per bank write bursts +system.physmem.perBankWrBursts::3 4689 # Per bank write bursts +system.physmem.perBankWrBursts::4 4379 # Per bank write bursts +system.physmem.perBankWrBursts::5 4312 # Per bank write bursts +system.physmem.perBankWrBursts::6 4615 # Per bank write bursts +system.physmem.perBankWrBursts::7 4485 # Per bank write bursts +system.physmem.perBankWrBursts::8 4160 # Per bank write bursts system.physmem.perBankWrBursts::9 4849 # Per bank write bursts -system.physmem.perBankWrBursts::10 4455 # Per bank write bursts -system.physmem.perBankWrBursts::11 3923 # Per bank write bursts -system.physmem.perBankWrBursts::12 3821 # Per bank write bursts -system.physmem.perBankWrBursts::13 4641 # Per bank write bursts -system.physmem.perBankWrBursts::14 4142 # Per bank write bursts -system.physmem.perBankWrBursts::15 3737 # Per bank write bursts +system.physmem.perBankWrBursts::10 4371 # Per bank write bursts +system.physmem.perBankWrBursts::11 3905 # Per bank write bursts +system.physmem.perBankWrBursts::12 3814 # Per bank write bursts +system.physmem.perBankWrBursts::13 4615 # Per bank write bursts +system.physmem.perBankWrBursts::14 4128 # Per bank write bursts +system.physmem.perBankWrBursts::15 3607 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2822156484500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 2822178697500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 113588 # Read request sizes (log2) +system.physmem.readPktSize::6 113342 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68931 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 24551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68762 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 24487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -195,130 +191,131 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 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req see +system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39396 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.306224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.340600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.184189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15747 39.97% 39.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9259 23.50% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3829 9.72% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2133 5.41% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1523 3.87% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 982 2.49% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 643 1.63% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 644 1.63% 88.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4636 11.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39396 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3632 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.238987 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 631.062126 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3630 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 39262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.647547 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.649192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.383393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15575 39.67% 39.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9414 23.98% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3760 9.58% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2064 5.26% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1515 3.86% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1018 2.59% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 639 1.63% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 658 1.68% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4619 11.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39262 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 31.293256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 632.321482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3616 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3632 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.975496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.811099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.084616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 8 0.22% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 6 0.17% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3236 89.10% 89.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 53 1.46% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 53 1.46% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 39 1.07% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 77 2.12% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 40 1.10% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.25% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.28% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.17% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.17% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.08% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.08% 97.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 57 1.57% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.06% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.08% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.14% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3632 # Writes before turning the bus around for reads -system.physmem.totQLat 1343214500 # Total ticks spent queuing -system.physmem.totMemAccLat 3470889500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 567380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11836.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3618 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.001658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.828073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.498575 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.06% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3234 89.39% 89.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 43 1.19% 90.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 55 1.52% 92.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 37 1.02% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 88 2.43% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 33 0.91% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 11 0.30% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.30% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 5 0.14% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.19% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.06% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.14% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 54 1.49% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.08% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.11% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3618 # Writes before turning the bus around for reads +system.physmem.totQLat 1331922750 # Total ticks spent queuing +system.physmem.totMemAccLat 3455116500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 566185000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11762.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30586.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30512.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.57 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.57 # Average system read bandwidth in MiByte/s @@ -328,42 +325,42 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.43 # Average write queue length when enqueuing -system.physmem.readRowHits 93570 # Number of row buffer hits during reads -system.physmem.writeRowHits 49429 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.71 # Row buffer hit rate for writes -system.physmem.avgGap 15462261.38 # Average gap between requests -system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 157845240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85919625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 459334200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 228024720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71920006785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621544131500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1874104092150 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.482602 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2641247054000 # Time in different power states -system.physmem_0.memoryStateTime::REF 91875680000 # Time in different power states +system.physmem.avgWrQLen 19.94 # Average write queue length when enqueuing +system.physmem.readRowHits 93386 # Number of row buffer hits during reads +system.physmem.writeRowHits 49336 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.75 # Row buffer hit rate for writes +system.physmem.avgGap 15497620.58 # Average gap between requests +system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 157701600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85878375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 459622800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 228737520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72061196355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1617839664000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1870543156410 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.633364 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2641056208250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91876460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18345210500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18550863000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139988520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76201125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 425778600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 218570400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71085141180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1620445714500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1872100224405 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.494295 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642466740000 # Time in different power states -system.physmem_1.memoryStateTime::REF 91875680000 # Time in different power states +system.physmem_1.actEnergy 139119120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 75726750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 423618000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 216749520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71208324450 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1622163329250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1873937222850 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.425184 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2642291372250 # Time in different power states +system.physmem_1.memoryStateTime::REF 91876460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17119297500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17320352000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -376,9 +373,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -386,7 +383,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -416,49 +413,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 4971 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4971 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4971 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4971 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4971 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.265788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15117011624 -26.58% -26.58% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993152250 126.58% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56876140626 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2795 68.19% 68.19% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1304 31.81% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4099 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4971 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 4996 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4996 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4996 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4996 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4996 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.265666 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15111501624 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993152000 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56881650376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2808 68.21% 68.21% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1309 31.79% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4117 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4996 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4971 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4099 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4996 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4117 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4099 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9070 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4117 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9113 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12098971 # DTB read hits -system.cpu0.dtb.read_misses 4249 # DTB read misses -system.cpu0.dtb.write_hits 9143699 # DTB write hits +system.cpu0.dtb.read_hits 12099084 # DTB read hits +system.cpu0.dtb.read_misses 4274 # DTB read misses +system.cpu0.dtb.write_hits 9151888 # DTB write hits system.cpu0.dtb.write_misses 722 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2759 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2772 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 830 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 821 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12103220 # DTB read accesses -system.cpu0.dtb.write_accesses 9144421 # DTB write accesses +system.cpu0.dtb.perms_faults 173 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12103358 # DTB read accesses +system.cpu0.dtb.write_accesses 9152610 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21242670 # DTB hits -system.cpu0.dtb.misses 4971 # DTB misses -system.cpu0.dtb.accesses 21247641 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 21250972 # DTB hits +system.cpu0.dtb.misses 4996 # DTB misses +system.cpu0.dtb.accesses 21255968 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,660 +485,660 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2431 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2431 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2431 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.265790 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15117125624 -26.58% -26.58% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993266250 126.58% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56876140626 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1312 74.72% 74.72% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 444 25.28% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1756 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 2442 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2442 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2442 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2442 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2442 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.265668 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15111616124 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993266500 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56881650376 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1322 74.86% 74.86% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 444 25.14% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1766 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2431 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2431 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2442 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2442 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1756 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1756 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4187 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56920666 # ITB inst hits -system.cpu0.itb.inst_misses 2431 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1766 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1766 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4208 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56923800 # ITB inst hits +system.cpu0.itb.inst_misses 2442 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1695 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1703 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56923097 # ITB inst accesses -system.cpu0.itb.hits 56920666 # DTB hits -system.cpu0.itb.misses 2431 # DTB misses -system.cpu0.itb.accesses 56923097 # DTB accesses -system.cpu0.numPwrStateTransitions 2544 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1272 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2140717570.690252 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 53412982832.831551 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1258 98.90% 98.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10 0.79% 99.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 56926242 # ITB inst accesses +system.cpu0.itb.hits 56923800 # DTB hits +system.cpu0.itb.misses 2442 # DTB misses +system.cpu0.itb.accesses 56926242 # DTB accesses +system.cpu0.numPwrStateTransitions 2560 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1280 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2127325768.303125 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 53245910996.367020 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1265 98.83% 98.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 11 0.86% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.77% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.08% 99.84% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.08% 99.92% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 1 0.08% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1799910941001 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1272 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 100735861582 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722992749918 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 68768248 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1799911049001 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1280 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 100773841072 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976983428 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 68778258 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3086 # number of quiesce instructions executed -system.cpu0.committedInsts 55456471 # Number of instructions committed -system.cpu0.committedOps 67221308 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58995481 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4380 # Number of float alu accesses -system.cpu0.num_func_calls 5787158 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7357632 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58995481 # number of integer instructions -system.cpu0.num_fp_insts 4380 # number of float instructions -system.cpu0.num_int_register_reads 108769217 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41129875 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read +system.cpu0.committedInsts 55461787 # Number of instructions committed +system.cpu0.committedOps 67232154 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59006752 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4424 # Number of float alu accesses +system.cpu0.num_func_calls 5784619 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7357566 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59006752 # number of integer instructions +system.cpu0.num_fp_insts 4424 # number of float instructions +system.cpu0.num_int_register_reads 108790658 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41133474 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3383 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 204568240 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24713959 # number of times the CC registers were written -system.cpu0.num_mem_refs 21830038 # number of memory refs -system.cpu0.num_load_insts 12248052 # Number of load instructions -system.cpu0.num_store_insts 9581986 # Number of store instructions -system.cpu0.num_idle_cycles 64949431.464966 # Number of idle cycles -system.cpu0.num_busy_cycles 3818816.535034 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055532 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944468 # Percentage of idle cycles -system.cpu0.Branches 13461051 # Number of branches fetched +system.cpu0.num_cc_register_reads 204599031 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24717436 # number of times the CC registers were written +system.cpu0.num_mem_refs 21838245 # number of memory refs +system.cpu0.num_load_insts 12248234 # Number of load instructions +system.cpu0.num_store_insts 9590011 # Number of store instructions +system.cpu0.num_idle_cycles 64958382.766609 # Number of idle cycles +system.cpu0.num_busy_cycles 3819875.233391 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055539 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944461 # Percentage of idle cycles +system.cpu0.Branches 13458694 # Number of branches fetched system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46425629 67.96% 67.96% # Class of executed instruction -system.cpu0.op_class::IntMult 50781 0.07% 68.04% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3880 0.01% 68.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 46427379 67.95% 67.96% # Class of executed instruction +system.cpu0.op_class::IntMult 50783 0.07% 68.03% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3883 0.01% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::MemRead 12248052 17.93% 85.97% # Class of executed instruction -system.cpu0.op_class::MemWrite 9581986 14.03% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12248234 17.93% 85.96% # Class of executed instruction +system.cpu0.op_class::MemWrite 9590011 14.04% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68312506 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 833701 # number of replacements +system.cpu0.op_class::total 68322468 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 833257 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45908566 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834213 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.032187 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 45925455 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833769 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.081749 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.062806 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.552141 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.736312 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.645453 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941529 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022563 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009251 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026651 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.041518 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.532588 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.805161 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.617445 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941487 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022525 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009385 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026597 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193086177 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193086177 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6693191 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25812079 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8805127 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2681872 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3150720 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 4155645 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18793364 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178315 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56771 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67457 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 85993 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 388536 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 216736 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75016 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70705 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 88525 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450982 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 217763 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76661 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73616 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92634 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20271941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6285887 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7198779 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10848836 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44605443 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20450256 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6342658 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7266236 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10934829 # number of overall hits -system.cpu0.dcache.overall_hits::total 44993979 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170779 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 51895 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 83860 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 219596 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 526130 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 112315 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 34838 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 103940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1226727 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1477820 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53930 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19459 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19330 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42725 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135444 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3695 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2338 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3825 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8068 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17926 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 27 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 283094 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 86733 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 187800 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1446323 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2003950 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 337024 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 106192 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 207130 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1489048 # number of overall misses -system.cpu0.dcache.overall_misses::total 2139394 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 835936000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1210061000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3349856000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5395853000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1273084500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5046790496 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 61121825312 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67441700308 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28644500 # number of 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overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16098.086903 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14546.422110 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15206.326995 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10214.182170 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36539.438713 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48814.196996 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49582.195398 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45437.858814 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12242.237346 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14975.855665 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13738.383589 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10962.073007 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 22525 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21452.380952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24299.707602 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 34021.446398 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44337.605217 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36235.438935 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19824.480575 # average overall miss latency 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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3415870000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238246500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2646664500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4858846947 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8743757947 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 247386000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 228071000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457588500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 933045500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8958000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27255500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 37981000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74194500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 588000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 588000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2020879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3667244000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6471504447 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12159627947 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2268265500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3895315000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6929092947 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13092673447 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 601507000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1484874500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1676185500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762567000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 601507000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1484874500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1676185500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762567000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014166 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018233 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016254 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009093 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012824 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017931 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.250885 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.182838 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230869 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123497 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008985 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019791 # mshr miss rate for LoadLockedReq accesses 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mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019204 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010428 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15111.370701 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13547.035946 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14352.211137 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14263.100756 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35542.984672 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47288.043381 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50343.441853 # average WriteReq mshr miss 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15415.437357 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21777.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21777.777778 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23327.979083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27929.203001 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30982.369753 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28489.490540 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21448.507858 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26467.592561 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29041.354548 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26637.058126 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175673.773364 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 208696.345748 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215171.437741 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205279.447869 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.332694 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 120633.235844 # average overall mshr uncacheable latency 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SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64564 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 698 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2779 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4928 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 20 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 87106 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 130184 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 208891 # number of demand (read+write) MSHR misses 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(read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12130918419 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2280366500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3871484000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6910229919 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13062080419 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 605119000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1489074500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1668784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762977500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 605119000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1489074500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1668784000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014260 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018147 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016236 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009089 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012863 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017049 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009210 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.252406 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.180557 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230420 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123190 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009027 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019499 # mshr miss rate for LoadLockedReq accesses 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mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019173 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010410 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15100.287825 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13584.883115 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14343.554899 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14270.934603 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35539.438713 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47579.738066 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50179.726270 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46666.418983 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12907.041017 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14340.300038 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15456.211159 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14422.309646 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13027.220630 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18903.170227 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14367.218424 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15512.987013 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21525 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21525 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23310.816706 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28020.371167 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30889.805779 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28464.240356 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21419.132289 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26556.666804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28973.831836 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26616.838519 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175447.665990 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209522.231603 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215021.775544 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205436.343288 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96188.046416 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121092.502236 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119284.060043 # average overall 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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12853.016945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12937.646203 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12853.016945 # average overall mshr miss latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 1969655 # number of writebacks +system.cpu0.icache.writebacks::total 1969655 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 42373 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 42373 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 42373 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 42373 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 42373 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 42373 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 212939 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 469858 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 543716 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1226513 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 212939 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 469858 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 543716 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1226513 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 212939 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 469858 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 543716 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1226513 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2702402500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6037100500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7028496990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 15767999990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2702402500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6037100500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7028496990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15767999990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2702402500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6037100500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7028496990 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15767999990 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012897 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012897 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012897 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12855.958306 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12855.958306 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12855.958306 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1171,63 +1168,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 2016 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2016 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 564 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1452 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2016 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2016 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2016 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1645 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12118.844985 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10271.833283 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6851.972198 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 2014 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2014 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 554 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1460 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2014 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2014 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2014 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1648 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12287.621359 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10419.476914 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6887.691629 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.91% 0.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 468 28.45% 29.36% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 121 7.36% 36.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 510 31.00% 67.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 106 6.44% 74.16% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 70 4.26% 78.42% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 79.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 321 19.51% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.34% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1645 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 458 27.79% 28.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 116 7.04% 35.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 507 30.76% 66.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 107 6.49% 73.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 75 4.55% 77.55% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 78.28% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 336 20.39% 98.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.33% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1648 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1089 66.20% 66.20% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 556 33.80% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1645 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2016 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1102 66.87% 66.87% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 546 33.13% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1648 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2014 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2016 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1645 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2014 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1648 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1645 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3661 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1648 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3662 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3812918 # DTB read hits -system.cpu1.dtb.read_misses 1745 # DTB read misses -system.cpu1.dtb.write_hits 2796286 # DTB write hits -system.cpu1.dtb.write_misses 271 # DTB write misses -system.cpu1.dtb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3812187 # DTB read hits +system.cpu1.dtb.read_misses 1742 # DTB read misses +system.cpu1.dtb.write_hits 2799792 # DTB write hits +system.cpu1.dtb.write_misses 272 # DTB write misses +system.cpu1.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1245 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1235 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 243 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 87 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3814663 # DTB read accesses -system.cpu1.dtb.write_accesses 2796557 # DTB write accesses +system.cpu1.dtb.perms_faults 89 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3813929 # DTB read accesses +system.cpu1.dtb.write_accesses 2800064 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6609204 # DTB hits -system.cpu1.dtb.misses 2016 # DTB misses -system.cpu1.dtb.accesses 6611220 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 6611979 # DTB hits +system.cpu1.dtb.misses 2014 # DTB misses +system.cpu1.dtb.accesses 6613993 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1257,148 +1254,148 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1033 # Table walker walks requested system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 205 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 828 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 201 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 832 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walkWaitTime::samples 1033 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0 1033 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1033 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 765 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12816.993464 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10782.034364 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7152.863364 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 258 33.73% 33.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 199 26.01% 59.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 58 7.58% 67.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 58 7.58% 74.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 75.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 23.92% 98.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 8 1.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 765 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::samples 763 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12903.669725 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10877.320310 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7130.133618 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 252 33.03% 33.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 198 25.95% 58.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 53 6.95% 65.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 68 8.91% 74.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 74.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 185 24.25% 99.21% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 6 0.79% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 763 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 560 73.20% 73.20% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 205 26.80% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 765 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 562 73.66% 73.66% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 201 26.34% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 763 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1033 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1033 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 765 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 765 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1798 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17860427 # ITB inst hits +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 763 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 763 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1796 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17843952 # ITB inst hits system.cpu1.itb.inst_misses 1033 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 732 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 730 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17861460 # ITB inst accesses -system.cpu1.itb.hits 17860427 # DTB hits +system.cpu1.itb.inst_accesses 17844985 # ITB inst accesses +system.cpu1.itb.hits 17843952 # DTB hits system.cpu1.itb.misses 1033 # DTB misses -system.cpu1.itb.accesses 17861460 # DTB accesses -system.cpu1.numPwrStateTransitions 700 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 350 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 887126528.134286 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 11718884453.100866 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 345 98.57% 98.57% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.86% 99.43% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 17844985 # DTB accesses +system.cpu1.numPwrStateTransitions 704 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 352 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 882103975.423295 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 11685879500.755745 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 347 98.58% 98.58% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.85% 99.43% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.57% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 156797355001 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 350 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2513234326653 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 310494284847 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 143797366 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 156798535501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 352 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2513250225151 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 310500599349 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 143831015 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17268414 # Number of instructions committed -system.cpu1.committedOps 20827213 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18584422 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1582 # Number of float alu accesses -system.cpu1.num_func_calls 1992181 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2177842 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18584422 # number of integer instructions -system.cpu1.num_fp_insts 1582 # number of float instructions -system.cpu1.num_int_register_reads 34431709 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13029372 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1129 # number of times the floating registers were read +system.cpu1.committedInsts 17251961 # Number of instructions committed +system.cpu1.committedOps 20817165 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18580086 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1666 # Number of float alu accesses +system.cpu1.num_func_calls 1994134 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2173480 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18580086 # number of integer instructions +system.cpu1.num_fp_insts 1666 # number of float instructions +system.cpu1.num_int_register_reads 34429785 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13026660 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1213 # number of times the floating registers were read system.cpu1.num_fp_register_writes 454 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75826477 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7417953 # number of times the CC registers were written -system.cpu1.num_mem_refs 6811480 # number of memory refs -system.cpu1.num_load_insts 3856412 # Number of load instructions -system.cpu1.num_store_insts 2955068 # Number of store instructions -system.cpu1.num_idle_cycles 136802879.005961 # Number of idle cycles -system.cpu1.num_busy_cycles 6994486.994039 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048641 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951359 # Percentage of idle cycles -system.cpu1.Branches 4283216 # Number of branches fetched -system.cpu1.op_class::No_OpClass 49 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14611363 68.15% 68.15% # Class of executed instruction -system.cpu1.op_class::IntMult 16029 0.07% 68.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 979 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::MemRead 3856412 17.99% 86.22% # Class of executed instruction -system.cpu1.op_class::MemWrite 2955068 13.78% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 75796626 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7400275 # number of times the CC registers were written +system.cpu1.num_mem_refs 6814833 # number of memory refs +system.cpu1.num_load_insts 3855659 # Number of load instructions +system.cpu1.num_store_insts 2959174 # Number of store instructions +system.cpu1.num_idle_cycles 136834040.067403 # Number of idle cycles +system.cpu1.num_busy_cycles 6996974.932597 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048647 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951353 # Percentage of idle cycles +system.cpu1.Branches 4280023 # Number of branches fetched +system.cpu1.op_class::No_OpClass 48 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14598901 68.12% 68.12% # Class of executed instruction +system.cpu1.op_class::IntMult 16055 0.07% 68.20% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 990 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu1.op_class::MemRead 3855659 17.99% 86.19% # Class of executed instruction +system.cpu1.op_class::MemWrite 2959174 13.81% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21439900 # Class of executed instruction -system.cpu2.branchPred.lookups 5566129 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2825980 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 493463 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3182486 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 1660276 # Number of BTB hits +system.cpu1.op_class::total 21430827 # Class of executed instruction +system.cpu2.branchPred.lookups 5563915 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2829451 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 493242 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3244476 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 1661186 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 52.169153 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1582499 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 327011 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 671898 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 638941 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 32957 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 21982 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu2.branchPred.BTBHitPct 51.200440 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1571960 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 328162 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 674670 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 641704 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 32966 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 22004 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1428,59 +1425,59 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 11822 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 11822 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7337 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4485 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 11822 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 11822 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 11822 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2048 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12710.205078 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10939.246339 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6922.657260 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 574 28.03% 28.03% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1046 51.07% 79.10% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 414 20.21% 99.32% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 12 0.59% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.walker.walks 11911 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 11911 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7385 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4526 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 11911 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 11911 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 11911 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2027 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12784.410459 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 11026.371953 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6894.594481 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 547 26.99% 26.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1059 52.24% 79.23% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 401 19.78% 99.01% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 18 0.89% 99.90% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2048 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000043000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000043000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000043000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1270 62.01% 62.01% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 778 37.99% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2048 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11822 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkCompletionTime::total 2027 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000042500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000042500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000042500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 1245 61.42% 61.42% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 782 38.58% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2027 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11911 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11822 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2048 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11911 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2027 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2048 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 13870 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2027 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 13938 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4336552 # DTB read hits -system.cpu2.dtb.read_misses 10662 # DTB read misses -system.cpu2.dtb.write_hits 3355101 # DTB write hits -system.cpu2.dtb.write_misses 1160 # DTB write misses -system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4327855 # DTB read hits +system.cpu2.dtb.read_misses 10705 # DTB read misses +system.cpu2.dtb.write_hits 3342614 # DTB write hits +system.cpu2.dtb.write_misses 1206 # DTB write misses +system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1416 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 270 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1399 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 245 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 127 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4347214 # DTB read accesses -system.cpu2.dtb.write_accesses 3356261 # DTB write accesses +system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4338560 # DTB read accesses +system.cpu2.dtb.write_accesses 3343820 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7691653 # DTB hits -system.cpu2.dtb.misses 11822 # DTB misses -system.cpu2.dtb.accesses 7703475 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.hits 7670469 # DTB hits +system.cpu2.dtb.misses 11911 # DTB misses +system.cpu2.dtb.accesses 7682380 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1510,139 +1507,140 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 1331 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1331 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 253 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1078 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1331 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1331 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1331 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 850 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12864.705882 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11157.048638 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6541.427390 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 256 30.12% 30.12% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 237 27.88% 58.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 63 7.41% 65.41% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 116 13.65% 79.06% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.71% 99.76% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.itb.walker.walks 1348 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1348 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 252 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1096 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1348 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1348 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 848 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 13074.292453 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11434.302344 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6448.856060 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 28.30% 28.30% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::6144-8191 2 0.24% 28.54% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 28.42% 56.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 61 7.19% 64.15% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 126 14.86% 79.01% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.75% 99.76% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.24% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 850 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000028500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000028500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000028500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 607 71.41% 71.41% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 243 28.59% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 850 # Table walker page sizes translated +system.cpu2.itb.walker.walkCompletionTime::total 848 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000028000 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000028000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000028000 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 600 70.75% 70.75% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 248 29.25% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 848 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1331 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1331 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1348 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1348 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 850 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 850 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2181 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10452986 # ITB inst hits -system.cpu2.itb.inst_misses 1331 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 848 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 848 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2196 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10441487 # ITB inst hits +system.cpu2.itb.inst_misses 1348 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 822 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 821 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1709 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1710 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10454317 # ITB inst accesses -system.cpu2.itb.hits 10452986 # DTB hits -system.cpu2.itb.misses 1331 # DTB misses -system.cpu2.itb.accesses 10454317 # DTB accesses -system.cpu2.numPwrStateTransitions 1086 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 543 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 5039016894.569060 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 41056292942.981247 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 498 91.71% 91.71% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.00% 98.71% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.18% 98.90% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.18% 99.08% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.18% 99.26% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.18% 99.45% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.82% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.18% 100.00% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 500052575501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 543 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 87542437749 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736186173751 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 141973763 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10442835 # ITB inst accesses +system.cpu2.itb.hits 10441487 # DTB hits +system.cpu2.itb.misses 1348 # DTB misses +system.cpu2.itb.accesses 10442835 # DTB accesses +system.cpu2.numPwrStateTransitions 1074 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 537 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 5095328839.376163 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 41281959005.190056 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 492 91.62% 91.62% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.08% 98.70% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.19% 98.88% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.19% 99.07% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.19% 99.26% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.19% 99.44% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.81% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.19% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::max_value 500052269001 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 537 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 87559237755 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736191586745 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 141974504 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19207375 # Number of instructions committed -system.cpu2.committedOps 23288496 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1385563 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 546 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 36865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.391628 # CPI: cycles per instruction -system.cpu2.ipc 0.135288 # IPC: instructions per cycle -system.cpu2.op_class_0::No_OpClass 48 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 15543125 66.74% 66.74% # Class of committed instruction -system.cpu2.op_class_0::IntMult 18693 0.08% 66.82% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 1356 0.01% 66.83% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu2.op_class_0::MemRead 4252165 18.26% 85.09% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 3473109 14.91% 100.00% # Class of committed instruction +system.cpu2.committedInsts 19185413 # Number of instructions committed +system.cpu2.committedOps 23254826 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1388377 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 540 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 36744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.400128 # CPI: cycles per instruction +system.cpu2.ipc 0.135133 # IPC: instructions per cycle +system.cpu2.op_class_0::No_OpClass 50 0.00% 0.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 15529839 66.78% 66.78% # Class of committed instruction +system.cpu2.op_class_0::IntMult 18571 0.08% 66.86% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.86% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 1326 0.01% 66.87% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction +system.cpu2.op_class_0::MemRead 4244552 18.25% 85.12% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 3460488 14.88% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 23288496 # Class of committed instruction +system.cpu2.op_class_0::total 23254826 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 41357618 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 100616145 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13553665 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7461562 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 296736 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8400664 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 4438644 # Number of BTB hits +system.cpu2.tickCycles 38692637 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 103281867 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13574263 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7472946 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 296816 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8409244 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 4443267 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 52.836823 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3086842 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16263 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2014355 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1952666 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 61689 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 18072 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu3.branchPred.BTBHitPct 52.837889 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3091382 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16244 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2018293 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1956673 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 61620 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 18086 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1672,91 +1670,92 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 34281 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 34281 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10962 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8120 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15199 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19082 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 497.143905 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3025.740716 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-8191 18625 97.61% 97.61% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::8192-16383 304 1.59% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-24575 96 0.50% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::24576-32767 29 0.15% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-40959 9 0.05% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::40960-49151 16 0.08% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.walker.walks 34289 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 34289 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10988 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8074 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 15227 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19062 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 480.983108 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 2977.429006 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-8191 18630 97.73% 97.73% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::8192-16383 285 1.50% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::24576-32767 31 0.16% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-40959 6 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::40960-49151 14 0.07% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::49152-57343 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19082 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6403 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 11721.380603 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 9562.982056 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7657.065586 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 2445 38.19% 38.19% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2784 43.48% 81.66% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 982 15.34% 97.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 97 1.51% 98.52% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 43 0.67% 99.19% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 36 0.56% 99.75% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-57343 11 0.17% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-73727 1 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkWaitTime::total 19062 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6433 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 11737.913882 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 9614.193609 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7621.962559 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 2432 37.81% 37.81% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2842 44.18% 81.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 955 14.85% 96.83% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 108 1.68% 98.51% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 45 0.70% 99.21% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 39 0.61% 99.81% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-57343 6 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-73727 2 0.03% 99.95% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6403 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8551346564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.449586 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.363024 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8598250064 100.55% 100.55% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 33569000 -0.39% 100.16% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 6441000 -0.08% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2603000 -0.03% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1836000 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 609000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 358000 -0.00% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 901500 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 248500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 75500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 42000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 21500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 24500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 20500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walkCompletionTime::total 6433 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8544248564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.589102 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.347038 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8589968064 100.54% 100.54% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 32103000 -0.38% 100.16% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6761500 -0.08% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2522000 -0.03% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1641500 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 647000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 437000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 926500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 267500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 118000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 41000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 32500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 26000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 29500 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::28-29 9000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 144500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8551346564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1841 71.89% 71.89% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 720 28.11% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2561 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34281 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walksPending::30-31 157500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8544248564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1826 71.78% 71.78% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 718 28.22% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34289 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34281 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2561 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34289 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 36842 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 36833 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7461865 # DTB read hits -system.cpu3.dtb.read_misses 28710 # DTB read misses -system.cpu3.dtb.write_hits 5703323 # DTB write hits -system.cpu3.dtb.write_misses 5571 # DTB write misses +system.cpu3.dtb.read_hits 7476077 # DTB read hits +system.cpu3.dtb.read_misses 28705 # DTB read misses +system.cpu3.dtb.write_hits 5707301 # DTB write hits +system.cpu3.dtb.write_misses 5584 # DTB write misses system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1649 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 376 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 696 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1654 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 379 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 711 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 324 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7490575 # DTB read accesses -system.cpu3.dtb.write_accesses 5708894 # DTB write accesses +system.cpu3.dtb.perms_faults 337 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7504782 # DTB read accesses +system.cpu3.dtb.write_accesses 5712885 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13165188 # DTB hits -system.cpu3.dtb.misses 34281 # DTB misses -system.cpu3.dtb.accesses 13199469 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.hits 13183378 # DTB hits +system.cpu3.dtb.misses 34289 # DTB misses +system.cpu3.dtb.accesses 13217667 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1786,394 +1785,389 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 4271 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4271 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1364 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2480 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 427 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 3844 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1432.232050 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 5712.962295 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3589 93.37% 93.37% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 172 4.47% 97.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 42 1.09% 98.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.49% 99.43% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.08% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 3 0.08% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.08% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 3844 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1607 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 11557.249533 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 9424.986938 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7716.115539 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-8191 693 43.12% 43.12% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-16383 628 39.08% 82.20% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-24575 248 15.43% 97.64% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-32767 18 1.12% 98.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.68% 99.44% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-49151 4 0.25% 99.69% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::49152-57343 2 0.12% 99.81% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-65535 2 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.itb.walker.walks 4253 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4253 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1354 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2463 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 436 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 3817 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1262.509824 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 4945.350323 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3591 94.08% 94.08% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 162 4.24% 98.32% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 27 0.71% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 17 0.45% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.16% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.03% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.10% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 3817 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1618 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 11355.377009 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 9318.464391 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7299.331906 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-8191 704 43.51% 43.51% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-16383 629 38.88% 82.39% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-24575 254 15.70% 98.08% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-32767 19 1.17% 99.26% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-40959 8 0.49% 99.75% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-49151 2 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::49152-57343 1 0.06% 99.94% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1607 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8760206064 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.998053 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.036484 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -15003296 0.17% 0.17% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -8746780268 99.85% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1238500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 234500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 77000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 27500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8760206064 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 845 71.61% 71.61% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 335 28.39% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated +system.cpu3.itb.walker.walkCompletionTime::total 1618 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -4448372768 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.737414 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.439006 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1166371868 26.22% 26.22% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -3283428900 73.81% 100.03% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1175000 -0.03% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 224000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 29000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -4448372768 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 844 71.40% 71.40% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 338 28.60% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1182 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4271 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4271 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4253 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4253 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5451 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9881110 # ITB inst hits -system.cpu3.itb.inst_misses 4271 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1182 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1182 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5435 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9894210 # ITB inst hits +system.cpu3.itb.inst_misses 4253 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1130 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1133 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 688 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 703 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9885381 # ITB inst accesses -system.cpu3.itb.hits 9881110 # DTB hits -system.cpu3.itb.misses 4271 # DTB misses -system.cpu3.itb.accesses 9885381 # DTB accesses -system.cpu3.numPwrStateTransitions 1752 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 876 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 24094343.119863 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 642903034.341614 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 861 98.29% 98.29% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.71% 100.00% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 18909601804 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 876 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 2802621966927 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 21106644573 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 55785273 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9898463 # ITB inst accesses +system.cpu3.itb.hits 9894210 # DTB hits +system.cpu3.itb.misses 4253 # DTB misses +system.cpu3.itb.accesses 9898463 # DTB accesses +system.cpu3.numPwrStateTransitions 1744 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 872 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 24195228.891055 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 644254106.585039 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 857 98.28% 98.28% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.72% 100.00% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::max_value 18906661340 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 872 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 2802652584907 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 21098239593 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 55802582 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20908000 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 53885903 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13553665 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9478152 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32386357 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1568366 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 62842 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 205 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 111743 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 71140 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9879793 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 204446 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2275 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54325636 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.196451 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.331637 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20935031 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 53976458 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13574263 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9491322 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32368112 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1569845 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 63704 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 1342 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 208 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 113598 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 71390 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9892868 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 204224 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2239 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54338522 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.198008 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.332788 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39861224 73.37% 73.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1851185 3.41% 76.78% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1193872 2.20% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3684209 6.78% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 942616 1.74% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 608186 1.12% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2968602 5.46% 94.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 642558 1.18% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2573184 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39853023 73.34% 73.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1853402 3.41% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1194631 2.20% 78.95% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3690685 6.79% 85.74% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 942938 1.74% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 608116 1.12% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2975810 5.48% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 643271 1.18% 95.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2576646 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54325636 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.242961 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.965952 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14640847 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 30019695 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7950688 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1013386 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 700819 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1055619 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 84442 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 46804905 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 276831 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 700819 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15165703 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3026847 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21377967 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8430788 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5623288 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 44934013 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 688 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1185922 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 108960 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3941702 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 46859874 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 206319060 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 50493308 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 4028 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39227152 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7632722 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 719514 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 667644 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5723010 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7961881 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6281202 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1151665 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1548744 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43283738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 518690 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41211324 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 55538 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6082655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14072346 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54325636 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.758598 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.457345 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54338522 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.243255 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.967275 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14662616 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29996417 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7962115 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1015455 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 701676 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1056216 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 84320 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 46882791 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 277439 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 701676 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15188976 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3032843 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21357872 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8442903 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5613994 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45010257 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 711 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1193798 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 109598 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 3924436 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 46943427 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 206658226 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 50584429 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3918 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39299455 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7643972 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 719812 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 667882 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5739952 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7978184 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6284983 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1159177 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1675680 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43355264 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 518308 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41274077 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 55092 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6092748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14109869 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54644 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54338522 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.759573 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.457624 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 38109289 70.15% 70.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5329887 9.81% 79.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4096392 7.54% 87.50% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3334775 6.14% 93.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1373146 2.53% 96.17% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 820032 1.51% 97.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 873869 1.61% 99.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 257598 0.47% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 130648 0.24% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 38089201 70.10% 70.10% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5343903 9.83% 79.93% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4107112 7.56% 87.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3342238 6.15% 93.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1372760 2.53% 96.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 822455 1.51% 97.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871489 1.60% 99.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 257925 0.47% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 131439 0.24% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54325636 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54338522 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 64574 10.28% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 290075 46.19% 56.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 273387 43.53% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 64295 10.27% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 1 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 288567 46.11% 56.39% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 272927 43.61% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27512260 66.76% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 31067 0.08% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.83% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7676579 18.63% 85.47% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5989018 14.53% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 61 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27558257 66.77% 66.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 31168 0.08% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7689945 18.63% 85.48% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5992314 14.52% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41211324 # Type of FU issued -system.cpu3.iq.rate 0.738749 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 628036 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015239 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 137423269 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 49907863 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40057337 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8589 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4965 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3611 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 41834624 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4674 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 172531 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41274077 # Type of FU issued +system.cpu3.iq.rate 0.739645 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 625790 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015162 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 137559378 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 49989246 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40120759 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8180 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4843 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3492 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 41895381 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4425 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 174238 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1192071 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1205 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28350 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 578135 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1195264 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1195 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28361 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 579365 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 104076 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 43928 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 104459 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 43794 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 700819 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2631101 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 281724 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 43863606 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 65733 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7961881 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6281202 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 267636 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 25569 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 250025 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28350 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 127807 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 129932 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 257739 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 40889941 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7546714 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 287190 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 701676 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2636383 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 282446 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 43936154 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 66826 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7978184 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6284983 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 267113 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 25993 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 250282 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28361 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 127792 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 130048 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 257840 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 40954158 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7560730 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 285711 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 61178 # number of nop insts executed -system.cpu3.iew.exec_refs 13479048 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7536415 # Number of branches executed -system.cpu3.iew.exec_stores 5932334 # Number of stores executed -system.cpu3.iew.exec_rate 0.732988 # Inst execution rate -system.cpu3.iew.wb_sent 40598229 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40060948 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21086851 # num instructions producing a value -system.cpu3.iew.wb_consumers 37255196 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.718128 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.566011 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6097168 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 464121 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 213352 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 53028005 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.712049 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.609623 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 62582 # number of nop insts executed +system.cpu3.iew.exec_refs 13496719 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7548230 # Number of branches executed +system.cpu3.iew.exec_stores 5935989 # Number of stores executed +system.cpu3.iew.exec_rate 0.733912 # Inst execution rate +system.cpu3.iew.wb_sent 40661575 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40124251 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21126058 # num instructions producing a value +system.cpu3.iew.wb_consumers 37308798 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.719039 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.566249 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 6107928 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 463664 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 213549 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 53039462 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.713065 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.610172 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38640353 72.87% 72.87% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6301176 11.88% 84.75% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3204030 6.04% 90.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1405492 2.65% 93.44% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 791558 1.49% 94.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 551411 1.04% 95.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 959183 1.81% 97.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 243959 0.46% 98.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 930843 1.76% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38622110 72.82% 72.82% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6314877 11.91% 84.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3213776 6.06% 90.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1409463 2.66% 93.44% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 790260 1.49% 94.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 551904 1.04% 95.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 961415 1.81% 97.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 244563 0.46% 98.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 931094 1.76% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 53028005 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 30988188 # Number of instructions committed -system.cpu3.commit.committedOps 37758554 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 53039462 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31045718 # Number of instructions committed +system.cpu3.commit.committedOps 37820561 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12472877 # Number of memory references committed -system.cpu3.commit.loads 6769810 # Number of loads committed -system.cpu3.commit.membars 181184 # Number of memory barriers committed -system.cpu3.commit.branches 7122308 # Number of branches committed -system.cpu3.commit.fp_insts 3347 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 32924881 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1244375 # Number of function calls committed. +system.cpu3.commit.refs 12488538 # Number of memory references committed +system.cpu3.commit.loads 6782920 # Number of loads committed +system.cpu3.commit.membars 181312 # Number of memory barriers committed +system.cpu3.commit.branches 7134012 # Number of branches committed +system.cpu3.commit.fp_insts 3283 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 32975843 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1245781 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25253254 66.88% 66.88% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 30097 0.08% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.96% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2326 0.01% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6769810 17.93% 84.90% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5703067 15.10% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25299473 66.89% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 30222 0.08% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2328 0.01% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.98% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6782920 17.93% 84.91% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5705618 15.09% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 37758554 # Class of committed instruction -system.cpu3.commit.bw_lim_events 930843 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90355963 # The number of ROB reads -system.cpu3.rob.rob_writes 89008957 # The number of ROB writes -system.cpu3.timesIdled 227178 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1459637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161855344 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 30949407 # Number of Instructions Simulated -system.cpu3.committedOps 37719773 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.802467 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.802467 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.554795 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.554795 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 44810788 # number of integer regfile reads -system.cpu3.int_regfile_writes 25112754 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14550 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12084 # number of floating regfile writes -system.cpu3.cc_regfile_reads 144202732 # number of cc regfile reads -system.cpu3.cc_regfile_writes 15932572 # number of cc regfile writes -system.cpu3.misc_regfile_reads 98044257 # number of misc regfile reads -system.cpu3.misc_regfile_writes 343753 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.cpu3.commit.op_class_0::total 37820561 # Class of committed instruction +system.cpu3.commit.bw_lim_events 931094 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90431014 # The number of ROB reads +system.cpu3.rob.rob_writes 89155949 # The number of ROB writes +system.cpu3.timesIdled 227288 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1464060 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161848397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31005981 # Number of Instructions Simulated +system.cpu3.committedOps 37780824 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.799736 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.799736 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.555637 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.555637 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 44884059 # number of integer regfile reads +system.cpu3.int_regfile_writes 25155589 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14375 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12072 # number of floating regfile writes +system.cpu3.cc_regfile_reads 144434496 # number of cc regfile reads +system.cpu3.cc_regfile_writes 15958517 # number of cc regfile writes +system.cpu3.misc_regfile_reads 98127938 # number of misc regfile reads +system.cpu3.misc_regfile_writes 343145 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2224,17 +2218,17 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 30018500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 29851500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 228500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) @@ -2242,32 +2236,32 @@ system.iobus.reqLayer19.occupancy 3000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3980500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 4026500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 22050500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 23286500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 72564537 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 72958030 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50308000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50254000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 14338000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.002475 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.002565 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248713478009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.002475 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062655 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062655 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248718527509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.002565 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062660 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062660 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2276,14 +2270,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 16064414 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 16064414 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1679848123 # number of WriteLineReq miss cycles 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-system.iocache.ReadReq_avg_miss_latency::total 73020.063636 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46373.899155 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 46373.899155 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 46534.752963 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 46534.752963 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 74072.327273 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 74072.327273 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46637.978081 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 46637.978081 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 46803.589891 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 46803.589891 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2316,771 +2310,744 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 14119 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 14119 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 14119 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 14119 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 9314414 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 9314414 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 979789535 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 979789535 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 989103949 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 989103949 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 989103949 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 989103949 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.613636 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.386042 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.386042 # mshr miss rate for WriteLineReq accesses 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average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70054.816134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70054.816134 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 100820 # number of replacements -system.l2c.tags.tagsinuse 65104.875407 # Cycle average of tags in use -system.l2c.tags.total_refs 5136861 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 165990 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.946810 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79348480000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49045.638268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902700 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.002962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4655.400387 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1832.462463 # Average occupied blocks per requestor +system.iocache.ReadReq_mshr_misses::realview.ide 137 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 137 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 14064 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 14064 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 14201 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 14201 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 14201 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 14201 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 9445912 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9445912 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 985358547 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 985358547 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 994804459 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 994804459 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 994804459 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 994804459 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.622727 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.622727 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.388251 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.388251 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.389666 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.389666 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.389666 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.389666 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68948.262774 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68948.262774 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70062.467790 # average WriteLineReq mshr miss latency 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of references to valid blocks. +system.l2c.tags.warmup_cycle 79359149000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 49022.002356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902695 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.002960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4655.957926 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1835.969861 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 777.111964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 859.577397 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.871513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2228.936773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 823.872322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 51.838280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 0.001832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2977.448230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1828.803519 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.748377 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 774.839390 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 858.475569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.852845 # Average occupied blocks per requestor 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occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.071044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011858 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013116 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013099 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000318 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.012571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000791 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034085 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.012678 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000858 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.045432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.027905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993422 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id 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-system.l2c.tags.occ_task_id_percent::1024 0.993515 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45392150 # Number of tag accesses -system.l2c.tags.data_accesses 45392150 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 4238 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2128 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1538 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 869 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 12508 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1155 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 20749 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 3773 # number of ReadReq hits -system.l2c.ReadReq_hits::total 46958 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 692418 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 692418 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1933833 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1933833 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1024::2 2141 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8201 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54725 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993469 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45365928 # Number of tag accesses +system.l2c.tags.data_accesses 45365928 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 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+system.l2c.overall_mshr_uncacheable_latency::total 3533959500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002191 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989496 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.979821 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.959264 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.584582 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.190476 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.346719 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.534448 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.533498 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.311499 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006708 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033462 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.023567 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.030243 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016676 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.134807 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.214420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.230466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.040194 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.134807 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.214420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.230466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.040194 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 75930.693069 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18974.789916 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18981.566820 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19021.709634 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18997.571342 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 32062.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 32062.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68568.532819 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67019.125313 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72527.572774 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70259.355515 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72841.782163 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74047.865727 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72685.714286 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78755.750399 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76035.126972 # average ReadSharedReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 80355.769231 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18969.214437 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19030.892449 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18987.671233 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18993.894994 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45125 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45125 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68565.346369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67280.427884 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72222.062251 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70179.447604 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73291.070677 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74053.002070 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73203.507153 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79058.105023 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76293.740237 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69486.823808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67688.234733 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73020.559181 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71012.363415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72762.226913 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71025.605108 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69486.823808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67688.234733 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73310.969557 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73020.559181 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71012.363415 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.224299 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196193.886156 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202667.586650 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192775.819739 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.484325 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113406.409944 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112384.716686 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 108356.220675 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 348991 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 146410 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72762.226913 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71025.605108 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162942.157147 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197019.980301 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202519.134132 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192933.313315 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89331.982197 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113866.878100 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112348.177269 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 108476.870894 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 349065 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 146440 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75609 # Transaction distribution +system.membus.trans_dist::ReadResp 75665 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 128684 # Transaction distribution -system.membus.trans_dist::CleanEvict 8545 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4547 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1834 # Transaction distribution -system.membus.trans_dist::ReadExReq 135487 # Transaction distribution -system.membus.trans_dist::ReadExResp 135487 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35495 # Transaction distribution +system.membus.trans_dist::WritebackDirty 128699 # Transaction distribution +system.membus.trans_dist::CleanEvict 8576 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4535 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1836 # Transaction distribution +system.membus.trans_dist::ReadExReq 135474 # Transaction distribution +system.membus.trans_dist::ReadExResp 135474 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35551 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 22240 # Transaction distribution +system.membus.trans_dist::InvalidateResp 22160 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 583891 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476553 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 584005 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95097 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95097 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 679102 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16891580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17054705 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19376305 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 335 # Total snoops (count) -system.membus.snoop_fanout::samples 342553 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015446 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.123318 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16895100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17058225 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2321472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19379697 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 340 # Total snoops (count) +system.membus.snoopTraffic 21632 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 342782 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015424 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.123231 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 337262 98.46% 98.46% # Request fanout histogram -system.membus.snoop_fanout::1 5291 1.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 337495 98.46% 98.46% # Request fanout histogram +system.membus.snoop_fanout::1 5287 1.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 342553 # Request fanout histogram -system.membus.reqLayer0.occupancy 56458000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 342782 # Request fanout histogram +system.membus.reqLayer0.occupancy 57572000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 682999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 694499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 493971550 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 502472051 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 649041000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 647767750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 721087 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 729588 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3112,84 +3079,85 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5640723 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2834949 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 44718 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5637070 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2833088 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 44773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 304 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 304 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 110723 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2619809 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 110855 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2618591 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 747367 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1971000 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 146335 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2812 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2841 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296829 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296829 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1971549 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537547 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5931996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2625304 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8681640 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252349880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97897081 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40868 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 174056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 350461885 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 123025 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4134650 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021870 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146260 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 746435 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1969655 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 146584 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2802 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296389 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296389 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1970201 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537545 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4503 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5927985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2623938 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99572 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8676800 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252179448 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97825081 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 175440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 350221073 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 122763 # Total snoops (count) +system.toL2Bus.snoopTraffic 6010036 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4133801 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021872 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146266 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4044224 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 90426 2.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4043386 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 90415 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4134650 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3415029456 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4133801 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3409727455 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 230913 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 234412 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1843284752 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1840405228 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 768457664 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 767451664 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10607473 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10602473 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47113721 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47179732 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 00e7e2739..439558bee 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -124,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -162,6 +173,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -221,12 +236,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -245,8 +265,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -269,9 +294,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -285,9 +315,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -605,12 +640,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -629,8 +669,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -688,9 +733,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -704,9 +754,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -738,6 +793,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -776,6 +832,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -845,9 +905,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -861,9 +926,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.fuPool] @@ -1223,9 +1293,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1239,9 +1314,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -1272,9 +1352,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1288,12 +1373,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1312,8 +1402,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1324,12 +1419,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1348,8 +1448,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -1357,10 +1462,15 @@ size=4194304 type=CoherentXBar children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 @@ -1374,11 +1484,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1430,6 +1545,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1441,7 +1557,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1484,10 +1604,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1568,14 +1693,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1584,13 +1714,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1671,10 +1806,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1754,17 +1894,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1790,13 +1935,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1804,14 +1954,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1897,14 +2052,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1913,13 +2073,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1928,13 +2093,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1942,11 +2112,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1960,11 +2135,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1978,12 +2158,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -2051,10 +2236,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2063,11 +2253,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2077,21 +2272,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2101,12 +2306,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2115,10 +2325,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2128,12 +2343,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2143,26 +2363,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2171,10 +2401,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2182,10 +2417,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2193,21 +2433,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2221,11 +2471,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2236,11 +2491,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2248,10 +2508,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2267,10 +2532,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 2c5672b0b..652b4376c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR @@ -40,24 +42,24 @@ warn: Ignoring write to miscreg pmintenclr warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[2] -warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2] warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5] warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3] warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3] warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0] -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[3] warn: instruction 'mcr dcisw' unimplemented +warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] +warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: instruction 'mcr bpiall' unimplemented warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: instruction 'mcr bpiall' unimplemented warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 43a8d7f1c..4e3f8e345 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:31 -gem5 executing on phenom, pid 15967 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:03:28 +gem5 executing on e108600-lin, pid 24169 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 5963d7bbb..6d5d200ba 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804580 # Number of seconds simulated -sim_ticks 2804580230500 # Number of ticks simulated -final_tick 2804580230500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804565 # Number of seconds simulated +sim_ticks 2804565276000 # Number of ticks simulated +final_tick 2804565276000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127171 # Simulator instruction rate (inst/s) -host_op_rate 154351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3050845926 # Simulator tick rate (ticks/s) -host_mem_usage 593120 # Number of bytes of host memory used -host_seconds 919.28 # Real time elapsed on the host -sim_insts 116905819 # Number of instructions simulated -sim_ops 141891765 # Number of ops (including micro ops) simulated +host_inst_rate 101255 # Simulator instruction rate (inst/s) +host_op_rate 122895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2428978767 # Simulator tick rate (ticks/s) +host_mem_usage 586736 # Number of bytes of host memory used +host_seconds 1154.63 # Real time elapsed on the host +sim_insts 116911386 # Number of instructions simulated +sim_ops 141898031 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 4032 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 685504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5032416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 692288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4777544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 684608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5013536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 686976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4780808 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11197032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 685504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 692288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1377792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8414016 # Number of bytes written to this memory +system.physmem.bytes_read::total 11175528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 684608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 686976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1371584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8423424 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8431540 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8440948 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 63 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 67 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10817 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 71 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74702 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175474 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131469 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175138 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131616 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135850 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1415 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135997 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 244423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1794356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 246842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1703479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 244105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1787634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 244949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1704652 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3992409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 244423 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 246842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3000098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3984763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 244105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 244949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 489054 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3003469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3006347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3000098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3009717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3003469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 244423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1800602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 246842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1703482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 244105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1793879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 244949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1704655 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6998756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175475 # Number of read requests accepted -system.physmem.writeReqs 135850 # Number of write requests accepted -system.physmem.readBursts 175475 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 135850 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11220480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue -system.physmem.bytesWritten 8444544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11197096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8431540 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6994480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175139 # Number of read requests accepted +system.physmem.writeReqs 135997 # Number of write requests accepted +system.physmem.readBursts 175139 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 135997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11199488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 8453504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11175592 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8440948 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11302 # Per bank write bursts -system.physmem.perBankRdBursts::1 11253 # Per bank write bursts -system.physmem.perBankRdBursts::2 11257 # Per bank write bursts -system.physmem.perBankRdBursts::3 10711 # Per bank write bursts -system.physmem.perBankRdBursts::4 11530 # Per bank write bursts -system.physmem.perBankRdBursts::5 11380 # Per bank write bursts -system.physmem.perBankRdBursts::6 12179 # Per bank write bursts -system.physmem.perBankRdBursts::7 12059 # Per bank write bursts -system.physmem.perBankRdBursts::8 10232 # Per bank write bursts -system.physmem.perBankRdBursts::9 10264 # Per bank write bursts -system.physmem.perBankRdBursts::10 10576 # Per bank write bursts -system.physmem.perBankRdBursts::11 9268 # Per bank write bursts -system.physmem.perBankRdBursts::12 10585 # Per bank write bursts -system.physmem.perBankRdBursts::13 11349 # Per bank write bursts -system.physmem.perBankRdBursts::14 10873 # Per bank write bursts -system.physmem.perBankRdBursts::15 10502 # Per bank write bursts -system.physmem.perBankWrBursts::0 8422 # Per bank write bursts -system.physmem.perBankWrBursts::1 8567 # Per bank write bursts -system.physmem.perBankWrBursts::2 8697 # Per bank write bursts -system.physmem.perBankWrBursts::3 8117 # Per bank write bursts -system.physmem.perBankWrBursts::4 8443 # Per bank write bursts -system.physmem.perBankWrBursts::5 8487 # Per bank write bursts -system.physmem.perBankWrBursts::6 9140 # Per bank write bursts -system.physmem.perBankWrBursts::7 9032 # Per bank write bursts -system.physmem.perBankWrBursts::8 7740 # Per bank write bursts -system.physmem.perBankWrBursts::9 7663 # Per bank write bursts -system.physmem.perBankWrBursts::10 7869 # Per bank write bursts -system.physmem.perBankWrBursts::11 6937 # Per bank write bursts -system.physmem.perBankWrBursts::12 8081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8671 # Per bank write bursts -system.physmem.perBankWrBursts::14 8306 # Per bank write bursts -system.physmem.perBankWrBursts::15 7774 # Per bank write bursts +system.physmem.perBankRdBursts::0 11119 # Per bank write bursts +system.physmem.perBankRdBursts::1 11081 # Per bank write bursts +system.physmem.perBankRdBursts::2 11640 # Per bank write bursts +system.physmem.perBankRdBursts::3 11194 # Per bank write bursts +system.physmem.perBankRdBursts::4 11361 # Per bank write bursts +system.physmem.perBankRdBursts::5 11364 # Per bank write bursts +system.physmem.perBankRdBursts::6 11912 # Per bank write bursts +system.physmem.perBankRdBursts::7 11778 # Per bank write bursts +system.physmem.perBankRdBursts::8 10214 # Per bank write bursts +system.physmem.perBankRdBursts::9 10385 # Per bank write bursts +system.physmem.perBankRdBursts::10 10562 # Per bank write bursts +system.physmem.perBankRdBursts::11 9757 # Per bank write bursts +system.physmem.perBankRdBursts::12 10332 # Per bank write bursts +system.physmem.perBankRdBursts::13 11401 # Per bank write bursts +system.physmem.perBankRdBursts::14 10617 # Per bank write bursts +system.physmem.perBankRdBursts::15 10275 # Per bank write bursts +system.physmem.perBankWrBursts::0 8313 # Per bank write bursts +system.physmem.perBankWrBursts::1 8440 # Per bank write bursts +system.physmem.perBankWrBursts::2 9041 # Per bank write bursts +system.physmem.perBankWrBursts::3 8539 # Per bank write bursts +system.physmem.perBankWrBursts::4 8335 # Per bank write bursts +system.physmem.perBankWrBursts::5 8538 # Per bank write bursts +system.physmem.perBankWrBursts::6 8956 # Per bank write bursts +system.physmem.perBankWrBursts::7 8814 # Per bank write bursts +system.physmem.perBankWrBursts::8 7742 # Per bank write bursts +system.physmem.perBankWrBursts::9 7782 # Per bank write bursts +system.physmem.perBankWrBursts::10 7931 # Per bank write bursts +system.physmem.perBankWrBursts::11 7392 # Per bank write bursts +system.physmem.perBankWrBursts::12 7874 # Per bank write bursts +system.physmem.perBankWrBursts::13 8749 # Per bank write bursts +system.physmem.perBankWrBursts::14 8038 # Per bank write bursts +system.physmem.perBankWrBursts::15 7602 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 2804580052000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 2804565097500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 174919 # Read request sizes (log2) +system.physmem.readPktSize::6 174583 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131469 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131616 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -163,180 +163,181 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 87 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 85 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 82 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4607 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 6324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.859343 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.384089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.204668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24461 37.67% 37.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15710 24.19% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6774 10.43% 72.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3704 5.70% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2837 4.37% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1544 2.38% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1096 1.69% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1046 1.61% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7759 11.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64931 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6660 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.324024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 478.772149 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6658 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::19 6955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9381 # What write queue length does an incoming req see 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# What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.173639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.438923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.896368 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24325 37.52% 37.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16003 24.69% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6580 10.15% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3580 5.52% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2814 4.34% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1563 2.41% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1120 1.73% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1064 1.64% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7775 11.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64824 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6666 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.249925 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 478.560077 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6664 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6660 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.811712 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.241865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.351487 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6666 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6666 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.814881 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.232650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.394597 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 11 0.17% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.12% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 5 0.08% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 7 0.11% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5729 86.02% 86.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 144 2.16% 88.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.23% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 58 0.87% 90.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 282 4.23% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 56 0.84% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.33% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.15% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.11% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.06% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 12 0.18% 0.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5751 86.27% 86.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 132 1.98% 88.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 86 1.29% 90.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.69% 90.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 272 4.08% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 61 0.92% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 24 0.36% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.21% 96.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 13 0.20% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.14% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 158 2.37% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.14% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.20% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 155 2.33% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.14% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.09% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.12% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.17% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6660 # Writes before turning the bus around for reads -system.physmem.totQLat 2657846750 # Total ticks spent queuing -system.physmem.totMemAccLat 5945096750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 876600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15159.97 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6666 # Writes before turning the bus around for reads +system.physmem.totQLat 2635898000 # Total ticks spent queuing +system.physmem.totMemAccLat 5916998000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 874960000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15062.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33909.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33812.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.98 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.41 # Average write queue length when enqueuing -system.physmem.readRowHits 144865 # Number of row buffer hits during reads -system.physmem.writeRowHits 97469 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.86 # Row buffer hit rate for writes -system.physmem.avgGap 9008528.23 # Average gap between requests -system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 258347880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140963625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 715026000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 446504400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183181277760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 78001831260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614323151750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1877067102675 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.287218 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685476419500 # Time in different power states -system.physmem_0.memoryStateTime::REF 93650960000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.88 # Average write queue length when enqueuing +system.physmem.readRowHits 144615 # Number of row buffer hits during reads +system.physmem.writeRowHits 97638 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.91 # Row buffer hit rate for writes +system.physmem.avgGap 9013952.41 # Average gap between requests +system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 258899760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 141264750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 713294400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 446964480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183180260640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 77917696695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614387610500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1877045991225 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.283406 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685583279000 # Time in different power states +system.physmem_0.memoryStateTime::REF 93650440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25452840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25331546500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 232530480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 126876750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652462200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 408505680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183181277760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 77069277630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615141181250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876812111750 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.196298 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2686837815500 # Time in different power states -system.physmem_1.memoryStateTime::REF 93650960000 # Time in different power states +system.physmem_1.actEnergy 231169680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 126134250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 651635400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 408952800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183180260640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 76668612660 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615483298250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876750063680 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.177890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2687409308250 # Time in different power states +system.physmem_1.memoryStateTime::REF 93650440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24087589500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23501044250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory @@ -349,30 +350,30 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 274 system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26564246 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13760083 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 495819 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 16217384 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8027247 # Number of BTB hits +system.cpu0.branchPred.lookups 26568186 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13757380 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 498035 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 15521852 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8027077 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 49.497792 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6609804 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28343 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4513554 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 4401782 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 111772 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 31942 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 51.714686 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6610878 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28698 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4514253 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 4401271 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 112982 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 32075 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -402,90 +403,95 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 58733 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 58733 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17793 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14688 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26252 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 32481 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 736.907731 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 4817.272185 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 32071 98.74% 98.74% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 298 0.92% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-49151 58 0.18% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-65535 24 0.07% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-81919 12 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-114687 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 32481 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13407.876285 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11117.462243 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8301.375847 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 9572 74.57% 74.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3010 23.45% 98.02% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 224 1.75% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 12 0.09% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-81919 3 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 11 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 80896428336 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.690430 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.489717 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 80813150336 99.90% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 56853500 0.07% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 12740500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4914000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2520000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1766000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1127000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1985000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 442000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 216500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 182000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 37500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 158000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 42500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 277000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 80896428336 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3537 69.35% 69.35% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1563 30.65% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5100 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58733 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 58842 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 58842 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17810 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14845 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 26187 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 32655 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 632.200276 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3881.293866 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 32316 98.96% 98.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 258 0.79% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 49 0.15% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-65535 18 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::147456-163839 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 32655 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12803 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12389.596188 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10179.754175 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7970.003099 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 4327 33.80% 33.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 5843 45.64% 79.43% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2208 17.25% 96.68% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 213 1.66% 98.34% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-40959 113 0.88% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::40960-49151 69 0.54% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-57343 10 0.08% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 7 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::90112-98303 4 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-106495 4 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 12803 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 80889831836 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.654695 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.499418 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 80811540336 99.90% 99.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 53922000 0.07% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 11918500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4370000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2811000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1565500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 964000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1576000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 313500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 197500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 119500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 36500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 186500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 25500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 24000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 261500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 80889831836 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3539 69.42% 69.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1559 30.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5098 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58842 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58733 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5100 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58842 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5098 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5100 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 63833 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5098 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 63940 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13760624 # DTB read hits -system.cpu0.dtb.read_misses 49633 # DTB read misses -system.cpu0.dtb.write_hits 10257954 # DTB write hits -system.cpu0.dtb.write_misses 9100 # DTB write misses +system.cpu0.dtb.read_hits 13766353 # DTB read hits +system.cpu0.dtb.read_misses 49364 # DTB read misses +system.cpu0.dtb.write_hits 10259633 # DTB write hits +system.cpu0.dtb.write_misses 9478 # DTB write misses system.cpu0.dtb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3389 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 823 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1310 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3387 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 892 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1297 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 671 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 13810257 # DTB read accesses -system.cpu0.dtb.write_accesses 10267054 # DTB write accesses +system.cpu0.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 13815717 # DTB read accesses +system.cpu0.dtb.write_accesses 10269111 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24018578 # DTB hits -system.cpu0.dtb.misses 58733 # DTB misses -system.cpu0.dtb.accesses 24077311 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 24025986 # DTB hits +system.cpu0.dtb.misses 58842 # DTB misses +system.cpu0.dtb.accesses 24084828 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -515,225 +521,227 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 7862 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7862 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2332 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4618 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 912 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 6950 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1524.460432 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 6004.169915 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 6494 93.44% 93.44% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 241 3.47% 96.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 125 1.80% 98.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 34 0.49% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 18 0.26% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 15 0.22% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 11 0.16% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 4 0.06% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 4 0.06% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::81920-90111 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 6950 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3241 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12408.053070 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10260.895484 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7472.988391 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1196 36.90% 36.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1364 42.09% 78.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 617 19.04% 98.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 36 1.11% 99.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 13 0.40% 99.54% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 9 0.28% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 4 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 7885 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7885 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2420 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4556 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 909 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 6976 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1209.934060 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 4914.790808 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 6588 94.44% 94.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 240 3.44% 97.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 86 1.23% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 32 0.46% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 14 0.20% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 8 0.11% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 3 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::81920-90111 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 6976 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3232 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11727.877475 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9548.081517 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7530.941401 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1404 43.44% 43.44% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1169 36.17% 79.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 601 18.60% 98.21% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.08% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 11 0.34% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 7 0.22% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.09% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3241 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 29351792784 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.620704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.485614 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 11137583928 37.95% 37.95% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 18210652356 62.04% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2700500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 701500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 154500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 29351792784 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1739 74.67% 74.67% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 590 25.33% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2329 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3232 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 33645212080 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.830268 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.375687 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 5713730428 16.98% 16.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 27928860152 83.01% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2282500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 253000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 59500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 33645212080 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1739 74.86% 74.86% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 584 25.14% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2323 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7862 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7862 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7885 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7885 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2329 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2329 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10191 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 19906259 # ITB inst hits -system.cpu0.itb.inst_misses 7862 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2323 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2323 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10208 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 19916742 # ITB inst hits +system.cpu0.itb.inst_misses 7885 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2225 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1249 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1235 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19914121 # ITB inst accesses -system.cpu0.itb.hits 19906259 # DTB hits -system.cpu0.itb.misses 7862 # DTB misses -system.cpu0.itb.accesses 19914121 # DTB accesses -system.cpu0.numPwrStateTransitions 3146 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1573 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 939647394.777495 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 18797497095.969948 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1537 97.71% 97.71% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.10% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 19924627 # ITB inst accesses +system.cpu0.itb.hits 19916742 # DTB hits +system.cpu0.itb.misses 7885 # DTB misses +system.cpu0.itb.accesses 19924627 # DTB accesses +system.cpu0.numPwrStateTransitions 3162 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1581 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 934903714.786211 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 18749967267.112076 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1545 97.72% 97.72% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.09% 99.81% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.13% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499976908600 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1573 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1326514878515 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478065351985 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 106457810 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499976755656 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1581 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1326482502923 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478082773077 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 106412241 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39783272 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 102334432 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26564246 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19038833 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 62110443 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3105656 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 111244 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 3727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 375 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 142235 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 122947 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 487 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 19904431 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 349445 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4054 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103827521 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.185827 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.289430 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39807667 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 102389396 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26568186 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19039226 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 62026637 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3110102 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 107465 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 3850 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 421 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 155531 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 127911 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 368 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 19914927 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 350256 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3998 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103784864 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.186876 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.290419 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75541763 72.76% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3812950 3.67% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2351578 2.26% 78.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7979154 7.69% 86.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1585790 1.53% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 993286 0.96% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6064061 5.84% 94.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1017530 0.98% 95.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4481409 4.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75488274 72.74% 72.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3815041 3.68% 76.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2353974 2.27% 78.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7979190 7.69% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1587719 1.53% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 994623 0.96% 88.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6057014 5.84% 94.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1019102 0.98% 95.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4489927 4.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103827521 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.249528 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.961267 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27452745 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58249830 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15282230 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1431597 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1410818 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1819259 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 143809 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 84470520 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 475057 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1410818 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28258375 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6709685 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43965251 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 15900516 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7582559 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 80840782 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 4307 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1036576 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 275166 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5563712 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 83242060 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 372803118 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 90148302 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 7047 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 70383329 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12858731 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1526779 # count of serializing insts renamed +system.cpu0.fetch.rateDist::total 103784864 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.249672 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.962196 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27473759 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58173812 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15291505 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1432841 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1412652 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1823499 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 144249 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 84520525 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 475248 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1412652 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28280194 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6736942 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43934801 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 15910349 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7509629 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 80887884 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3905 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1038108 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 267593 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5492226 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 83297539 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 373007231 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 90195870 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6961 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 70398676 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12898863 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1526830 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 1432825 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8314563 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14558964 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11309450 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1956443 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2653694 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 77893392 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1057864 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 74754554 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 90317 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10606810 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23150954 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 112541 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103827521 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.719988 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.414103 # Number of insts issued each cycle +system.cpu0.rename.skidInsts 8315442 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14569662 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11312381 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1968850 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2730392 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 77926980 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1058477 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 74778360 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 90763 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10627433 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23204178 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 112737 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103784864 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.720513 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.414461 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73904134 71.18% 71.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10009837 9.64% 80.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7641807 7.36% 88.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6354760 6.12% 94.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2280701 2.20% 96.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1455227 1.40% 97.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1486959 1.43% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 476638 0.46% 99.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 217458 0.21% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73826337 71.13% 71.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10059193 9.69% 80.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7635969 7.36% 88.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6342907 6.11% 94.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2283033 2.20% 96.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1456613 1.40% 97.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1481922 1.43% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 479341 0.46% 99.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 219549 0.21% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103827521 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103784864 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 96078 8.82% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 523068 47.99% 56.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 470781 43.19% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 96825 8.81% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 525523 47.82% 56.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 476662 43.37% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2193 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 49737115 66.53% 66.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57140 0.08% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2194 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 49752146 66.53% 66.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57180 0.08% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.61% # Type of FU issued @@ -756,100 +764,100 @@ system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.61% # Ty system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.61% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4360 0.01% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4372 0.01% 66.62% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.62% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.62% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14141290 18.92% 85.54% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10812453 14.46% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14148422 18.92% 85.54% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10814044 14.46% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 74754554 # Type of FU issued -system.cpu0.iq.rate 0.702199 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1089928 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014580 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 254501968 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 89602389 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 72535350 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14906 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 8959 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6549 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 75834268 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 8021 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 353131 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 74778360 # Type of FU issued +system.cpu0.iq.rate 0.702723 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1099011 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014697 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 254516336 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 89657321 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 72555337 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 15022 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 8945 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6550 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 75867097 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 8080 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 352646 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2046839 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2065 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54488 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1026130 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2054023 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2148 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54598 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1028244 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 203254 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 83583 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 203435 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 82087 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1410818 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5863644 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 637671 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 79075081 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107625 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14558964 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11309450 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 551514 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44441 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 581945 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54488 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 204716 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 218656 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 423372 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 74207157 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 13922405 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 488771 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1412652 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5873643 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 655367 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 79110277 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 106917 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14569662 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11312381 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 551702 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44436 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 599579 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54598 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 206066 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 219140 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 425206 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 74227613 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 13928296 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 492013 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 123825 # number of nop insts executed -system.cpu0.iew.exec_refs 24639289 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14032526 # Number of branches executed -system.cpu0.iew.exec_stores 10716884 # Number of stores executed -system.cpu0.iew.exec_rate 0.697057 # Inst execution rate -system.cpu0.iew.wb_sent 73693634 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 72541899 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 37717472 # num instructions producing a value -system.cpu0.iew.wb_consumers 65674853 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.681415 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574306 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10563486 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 945323 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 353772 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101400754 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.674795 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.564695 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 124820 # number of nop insts executed +system.cpu0.iew.exec_refs 24646290 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14030699 # Number of branches executed +system.cpu0.iew.exec_stores 10717994 # Number of stores executed +system.cpu0.iew.exec_rate 0.697548 # Inst execution rate +system.cpu0.iew.wb_sent 73714298 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 72561887 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 37730883 # num instructions producing a value +system.cpu0.iew.wb_consumers 65693607 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.681894 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574346 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10582820 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 945740 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 355599 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101354368 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.675249 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.564531 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74701679 73.67% 73.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12064783 11.90% 85.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6043507 5.96% 91.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2566010 2.53% 94.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1263544 1.25% 95.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 840996 0.83% 96.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1825672 1.80% 97.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 394773 0.39% 98.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1699790 1.68% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74626886 73.63% 73.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12088537 11.93% 85.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6044710 5.96% 91.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2569505 2.54% 94.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1279385 1.26% 95.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 839259 0.83% 96.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1807050 1.78% 97.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 395487 0.39% 98.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1703549 1.68% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101400754 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 56177531 # Number of instructions committed -system.cpu0.commit.committedOps 68424746 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101354368 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 56197107 # Number of instructions committed +system.cpu0.commit.committedOps 68439408 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 22795445 # Number of memory references committed -system.cpu0.commit.loads 12512125 # Number of loads committed -system.cpu0.commit.membars 380426 # Number of memory barriers committed -system.cpu0.commit.branches 13309453 # Number of branches committed -system.cpu0.commit.fp_insts 6093 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 59909497 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2612274 # Number of function calls committed. +system.cpu0.commit.refs 22799776 # Number of memory references committed +system.cpu0.commit.loads 12515639 # Number of loads committed +system.cpu0.commit.membars 380661 # Number of memory barriers committed +system.cpu0.commit.branches 13306067 # Number of branches committed +system.cpu0.commit.fp_insts 6109 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 59926267 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2612600 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 45569326 66.60% 66.60% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55618 0.08% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 45579664 66.60% 66.60% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55599 0.08% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.68% # Class of committed instruction @@ -873,457 +881,457 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.68% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.68% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4357 0.01% 66.69% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4369 0.01% 66.69% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.69% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.69% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.69% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12512125 18.29% 84.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10283320 15.03% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12515639 18.29% 84.97% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10284137 15.03% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 68424746 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1699790 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166301969 # The number of ROB reads -system.cpu0.rob.rob_writes 160402388 # The number of ROB writes -system.cpu0.timesIdled 400481 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2630289 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2956130676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56097231 # Number of Instructions Simulated -system.cpu0.committedOps 68344446 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.897737 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.897737 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.526943 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.526943 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 80771254 # number of integer regfile reads -system.cpu0.int_regfile_writes 46168447 # number of integer regfile writes -system.cpu0.fp_regfile_reads 17119 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13230 # number of floating regfile writes -system.cpu0.cc_regfile_reads 262483574 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27229221 # number of cc regfile writes -system.cpu0.misc_regfile_reads 188104262 # number of misc regfile reads -system.cpu0.misc_regfile_writes 725122 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 852281 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984445 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42339944 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 852793 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.648559 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 68439408 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1703549 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166286675 # The number of ROB reads +system.cpu0.rob.rob_writes 160474100 # The number of ROB writes +system.cpu0.timesIdled 401346 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2627377 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2956165518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 56115723 # Number of Instructions Simulated +system.cpu0.committedOps 68358024 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.896300 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.896300 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.527343 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.527343 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 80796649 # number of integer regfile reads +system.cpu0.int_regfile_writes 46187734 # number of integer regfile writes +system.cpu0.fp_regfile_reads 17075 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13292 # number of floating regfile writes +system.cpu0.cc_regfile_reads 262559417 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27235047 # number of cc regfile writes +system.cpu0.misc_regfile_reads 188033527 # number of misc regfile reads +system.cpu0.misc_regfile_writes 725405 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 851456 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984383 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42342080 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 851968 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.699144 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 92671500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.072113 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.912332 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359516 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.640454 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 183.852002 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.132381 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359086 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.640884 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999969 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 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miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 20032436812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11025750369 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10744583443 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21770333812 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3299950500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3004338000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304288500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3299950500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3004338000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304288500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016627 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015955 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016282 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016246 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014358 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015284 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.213427 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234730 # mshr miss rate for SoftPFReq accesses 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average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46720.179612 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46672.364942 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14046.929936 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14235.539263 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14150.904729 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12965.810968 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16800.661455 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15028.790166 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19580 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17337.209302 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18543.010753 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28072.019579 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27409.303027 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27745.234302 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26237.706771 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25305.697671 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25770.256973 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202176.882180 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202925.082978 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202531.740932 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102367.724868 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.026069 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107376.905520 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1934891 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.556955 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38705762 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1935403 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 19.998813 # Average number of references to valid blocks. +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015853 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018711 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017963 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018328 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14231.737196 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14430.873274 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14332.000699 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46539.816473 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46706.662365 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46619.709807 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14020.716318 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14240.995194 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14142.696712 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13042.175893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16944.149479 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15148.897464 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17837.209302 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18576.470588 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28000.781771 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27413.833897 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27711.252626 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26180.475963 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25302.924945 # average overall mshr miss latency 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demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 18870227 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19835535 # number of overall hits -system.cpu0.icache.overall_hits::total 38705762 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1033532 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1049601 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2083133 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1033532 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1049601 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2083133 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1033532 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1049601 # number of overall misses -system.cpu0.icache.overall_misses::total 2083133 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14014676985 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14269854487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28284531472 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14014676985 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14269854487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28284531472 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14014676985 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14269854487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28284531472 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19903759 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20885136 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40788895 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19903759 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20885136 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40788895 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19903759 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20885136 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40788895 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050256 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.051071 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051926 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050256 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.051071 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051926 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050256 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051071 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.983614 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.503898 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13577.880756 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.983614 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.503898 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13577.880756 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.983614 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.503898 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13577.880756 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 12686 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42723428 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42723428 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 18879325 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19827596 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38706921 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 18879325 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19827596 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38706921 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 18879325 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19827596 # number of overall hits +system.cpu0.icache.overall_hits::total 38706921 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1034931 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1047206 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2082137 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1034931 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1047206 # number of demand (read+write) misses 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of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14232269988 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28261939975 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19914256 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20874802 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40789058 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19914256 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20874802 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40789058 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19914256 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20874802 # number of overall (read+write) accesses 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639 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 623 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.852895 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.457464 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1934891 # number of writebacks -system.cpu0.icache.writebacks::total 1934891 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71394 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76196 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 147590 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 71394 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 76196 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 147590 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 71394 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 76196 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 147590 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 962138 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 973405 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1935543 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 962138 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 973405 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1935543 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 962138 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 973405 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1935543 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1933722 # number of writebacks +system.cpu0.icache.writebacks::total 1933722 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71718 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76048 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 147766 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 71718 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 76048 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 147766 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 71718 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 76048 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 147766 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 963213 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 971158 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1934371 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 963213 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 971158 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1934371 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 963213 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 971158 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1934371 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12396442988 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12601714991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 24998157979 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12396442988 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12601714991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 24998157979 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12396442988 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12601714991 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 24998157979 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12408483492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12567838491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 24976321983 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12408483492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12567838491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 24976321983 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12408483492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12567838491 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 24976321983 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 53482500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 53482500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 53482500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 53482500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048340 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046608 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047453 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048340 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046608 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047453 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048340 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046608 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047453 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12884.267109 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12946.014240 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12915.320393 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12884.267109 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12946.014240 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12915.320393 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12884.267109 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12946.014240 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12915.320393 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048368 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046523 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047424 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048368 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046523 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047424 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048368 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046523 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047424 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12882.387896 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12941.085272 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12911.857127 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12882.387896 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12941.085272 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12911.857127 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12882.387896 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12941.085272 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12911.857127 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 27798523 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14466350 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 520194 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17356776 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 8536168 # Number of BTB hits +system.cpu1.branchPred.lookups 27798204 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14470719 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 518667 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17368333 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 8539564 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 49.180608 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6850987 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 30102 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4615656 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 4505334 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 110322 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 32790 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 49.167436 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6849209 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29775 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4616738 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 4505967 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 110771 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 32761 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1353,93 +1361,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 58687 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58687 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18789 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14348 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25550 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33137 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 617.587591 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3984.391967 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 32762 98.87% 98.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 289 0.87% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 55 0.17% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 15 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::81920-98303 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 58826 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58826 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18872 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14273 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25681 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33145 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 585.865138 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3677.608561 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 32788 98.92% 98.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 287 0.87% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 48 0.14% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 12 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 7 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::114688-131071 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::147456-163839 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33137 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 12948 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13117.547112 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10856.155685 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7835.700834 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 3825 29.54% 29.54% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5982 46.20% 75.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2634 20.34% 96.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 274 2.12% 98.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 123 0.95% 99.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 98 0.76% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 2 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 12948 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 90160170928 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.682736 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.486637 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 90081870928 99.91% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 54780000 0.06% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 11436000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 4223000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2627000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1276500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 880500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 1864000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 368000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 150000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 136000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 188500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 289500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 3500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 47500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 90160170928 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3742 69.76% 69.76% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1622 30.24% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5364 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58687 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 33145 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 13049 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12961.567936 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10723.007113 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7830.239554 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 3942 30.21% 30.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 6071 46.52% 76.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2547 19.52% 96.25% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 256 1.96% 98.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 106 0.81% 99.03% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 110 0.84% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 9 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 13049 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 90145173428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.714972 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.473357 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 90067700428 99.91% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 53747000 0.06% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 11656000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 4441500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 2654000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1196000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 758000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 1848500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 266500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 153500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 119500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 164000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 321500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 35000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 104500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 90145173428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3714 69.38% 69.38% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1639 30.62% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5353 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58826 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58687 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5364 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58826 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5353 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5364 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 64051 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5353 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 64179 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14568202 # DTB read hits -system.cpu1.dtb.read_misses 50557 # DTB read misses -system.cpu1.dtb.write_hits 10638746 # DTB write hits -system.cpu1.dtb.write_misses 8130 # DTB write misses +system.cpu1.dtb.read_hits 14560023 # DTB read hits +system.cpu1.dtb.read_misses 50490 # DTB read misses +system.cpu1.dtb.write_hits 10636581 # DTB write hits +system.cpu1.dtb.write_misses 8336 # DTB write misses system.cpu1.dtb.flush_tlb 176 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3340 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 811 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1147 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3352 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 784 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1139 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 622 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14618759 # DTB read accesses -system.cpu1.dtb.write_accesses 10646876 # DTB write accesses +system.cpu1.dtb.perms_faults 621 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14610513 # DTB read accesses +system.cpu1.dtb.write_accesses 10644917 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25206948 # DTB hits -system.cpu1.dtb.misses 58687 # DTB misses -system.cpu1.dtb.accesses 25265635 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 25196604 # DTB hits +system.cpu1.dtb.misses 58826 # DTB misses +system.cpu1.dtb.accesses 25255430 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1469,341 +1475,338 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 7567 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7567 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2268 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4460 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 839 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6728 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1599.137931 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 7818.499814 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-16383 6550 97.35% 97.35% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-32767 110 1.63% 98.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-49151 34 0.51% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-65535 14 0.21% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-81919 4 0.06% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-98303 4 0.06% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-114687 5 0.07% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::114688-131071 3 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::147456-163839 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-180223 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6728 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 3154 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12204.343691 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9955.063689 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 8183.561503 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 2464 78.12% 78.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 661 20.96% 99.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 7718 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7718 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2370 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4511 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 837 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6881 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1585.234704 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6902.284757 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-16383 6686 97.17% 97.17% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-32767 129 1.87% 99.04% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-49151 34 0.49% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-65535 16 0.23% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-81919 8 0.12% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-98303 3 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-114687 3 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6881 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 3170 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12167.034700 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9891.169611 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 8057.359944 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 2478 78.17% 78.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 663 20.91% 99.09% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::32768-49151 24 0.76% 99.84% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::49152-65535 4 0.13% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::180224-196607 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 3154 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 25735525988 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.805879 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.396479 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 5001469876 19.43% 19.43% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 20730637612 80.55% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2251500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 605500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 237500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 189000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 78500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 56500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 25735525988 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1742 75.25% 75.25% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 573 24.75% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2315 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 3170 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 34310573580 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.816220 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.387901 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 6310834876 18.39% 18.39% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 27996313204 81.60% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2293000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 658500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 333500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 91000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 49500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 34310573580 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1756 75.27% 75.27% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 577 24.73% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7567 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7567 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7718 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7718 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2315 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2315 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 9882 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20887699 # ITB inst hits -system.cpu1.itb.inst_misses 7567 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10051 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20877340 # ITB inst hits +system.cpu1.itb.inst_misses 7718 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 176 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 472 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2181 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2200 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1369 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1355 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20895266 # ITB inst accesses -system.cpu1.itb.hits 20887699 # DTB hits -system.cpu1.itb.misses 7567 # DTB misses -system.cpu1.itb.accesses 20895266 # DTB accesses -system.cpu1.numPwrStateTransitions 2930 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1465 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 831651195.687372 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 15817593715.627289 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1430 97.61% 97.61% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 32 2.18% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 20885058 # ITB inst accesses +system.cpu1.itb.hits 20877340 # DTB hits +system.cpu1.itb.misses 7718 # DTB misses +system.cpu1.itb.accesses 20885058 # DTB accesses +system.cpu1.numPwrStateTransitions 2914 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1457 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 836230234.840082 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 15860875866.076208 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1422 97.60% 97.60% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 32 2.20% 99.79% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.07% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 499953823748 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1465 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 1586211228818 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218369001682 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 109802096 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 499953982692 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 1457 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 1586177823838 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218387452162 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 109746430 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40943144 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108514996 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27798523 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19892489 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 64235640 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3213335 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 105850 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 370 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 133652 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 123170 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 245 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20885138 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 363282 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3860 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 107155901 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.215568 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.316644 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40895986 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108462285 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27798204 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19894740 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 64228270 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3210503 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 105636 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 364 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 136679 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 127439 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20874803 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 362169 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3960 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 107107154 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.215557 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.316339 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 77413551 72.24% 72.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3964796 3.70% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2490827 2.32% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8243216 7.69% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1613766 1.51% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1187087 1.11% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6283183 5.86% 94.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1186163 1.11% 95.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4773312 4.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 77373213 72.24% 72.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3963895 3.70% 75.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2490638 2.33% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8243801 7.70% 85.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1611366 1.50% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1186347 1.11% 88.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6289453 5.87% 94.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1183134 1.10% 95.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4765307 4.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 107155901 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253169 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.988278 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27961508 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 60068174 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15895892 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1769487 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1460540 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 2002899 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 148049 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90324512 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 490358 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1460540 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28915970 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 5237096 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 47181010 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16703954 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7656988 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 86483131 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 1983 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1745149 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 215112 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 4898057 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89702997 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 398140635 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 96368391 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6135 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 76284271 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13418710 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1604439 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1503267 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10222597 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15399417 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11771402 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2211738 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2954385 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 83351812 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1152022 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 80024674 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91529 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10956511 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24682043 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 103513 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 107155901 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.746806 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.429727 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 107107154 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253295 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.988299 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27921866 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 60067662 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15890093 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1767595 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1459620 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1999442 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 147513 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 90274906 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 488786 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1459620 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28874792 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 5214847 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 47170555 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16697712 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7689265 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 86435062 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2196 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1738246 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 216044 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 4936698 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89654559 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 397922384 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 96312255 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6119 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 76275352 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13379191 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1604332 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1503289 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10206476 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15384658 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11766815 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2187303 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2806337 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 83309557 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1151208 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 79998202 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91456 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10920754 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24595973 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 103002 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 107107154 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.746899 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.431011 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74986719 69.98% 69.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10856192 10.13% 80.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8181836 7.64% 87.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6800942 6.35% 94.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2507542 2.34% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1554150 1.45% 97.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1528598 1.43% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 489898 0.46% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 250024 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 75017466 70.04% 70.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10766554 10.05% 80.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8172110 7.63% 87.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6817962 6.37% 94.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2501926 2.34% 96.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1553712 1.45% 97.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1535084 1.43% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 491946 0.46% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 250394 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 107155901 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 107107154 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 115019 9.97% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 7 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 527702 45.75% 55.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 510821 44.28% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 114052 9.86% 9.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 7 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 527984 45.67% 55.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 514092 44.47% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 144 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53744043 67.16% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59080 0.07% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 3 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4215 0.01% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 143 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53728973 67.16% 67.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59111 0.07% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4201 0.01% 67.24% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 67.24% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14957838 18.69% 85.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11259342 14.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14948674 18.69% 85.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11257095 14.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 80024674 # Type of FU issued -system.cpu1.iq.rate 0.728808 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1153549 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014415 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 268436998 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 95502900 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77720615 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13329 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7517 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5775 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 81170860 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7219 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 353138 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 79998202 # Type of FU issued +system.cpu1.iq.rate 0.728937 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1156135 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014452 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 268337940 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 95424057 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77696965 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13209 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7523 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5720 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 81147055 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7139 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 351994 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2111745 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1994 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 51136 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1016819 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2099522 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2035 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 51133 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1012143 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 193347 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 111137 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 193136 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 112329 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1460540 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4234573 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 751343 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84621300 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 108802 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15399417 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11771402 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 582328 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 44713 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 693944 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 51136 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 222391 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 227484 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 449875 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79460848 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14731272 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 505307 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1459620 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4216196 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 746434 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84577573 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 108382 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15384658 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11766815 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 582249 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44240 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 689439 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 51133 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 222163 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 226496 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 448659 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79436293 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14722883 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 503246 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 117466 # number of nop insts executed -system.cpu1.iew.exec_refs 25893193 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14803387 # Number of branches executed -system.cpu1.iew.exec_stores 11161921 # Number of stores executed -system.cpu1.iew.exec_rate 0.723673 # Inst execution rate -system.cpu1.iew.wb_sent 78896446 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77726390 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 41030059 # num instructions producing a value -system.cpu1.iew.wb_consumers 71721300 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.707877 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.572076 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 10985590 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1048509 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 374030 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 104641106 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703566 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.592412 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 116808 # number of nop insts executed +system.cpu1.iew.exec_refs 25882990 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14805311 # Number of branches executed +system.cpu1.iew.exec_stores 11160107 # Number of stores executed +system.cpu1.iew.exec_rate 0.723817 # Inst execution rate +system.cpu1.iew.wb_sent 78872387 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77702685 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 41015418 # num instructions producing a value +system.cpu1.iew.wb_consumers 71702227 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.708020 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.572024 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 10950045 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1048206 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 372999 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 104597545 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703779 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.594224 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 76039975 72.67% 72.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12757270 12.19% 84.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6567840 6.28% 91.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2747077 2.63% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1449083 1.38% 95.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 932804 0.89% 96.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1855484 1.77% 97.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 438097 0.42% 98.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1853476 1.77% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 76066046 72.72% 72.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12690674 12.13% 84.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6559681 6.27% 91.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2745344 2.62% 93.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1426512 1.36% 95.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 937004 0.90% 96.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1881396 1.80% 97.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 439088 0.42% 98.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1851800 1.77% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 104641106 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60883193 # Number of instructions committed -system.cpu1.commit.committedOps 73621924 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 104597545 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60869184 # Number of instructions committed +system.cpu1.commit.committedOps 73613528 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 24042255 # Number of memory references committed -system.cpu1.commit.loads 13287672 # Number of loads committed -system.cpu1.commit.membars 433805 # Number of memory barriers committed -system.cpu1.commit.branches 14065238 # Number of branches committed -system.cpu1.commit.fp_insts 5335 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 64517791 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2723455 # Number of function calls committed. +system.cpu1.commit.refs 24039808 # Number of memory references committed +system.cpu1.commit.loads 13285136 # Number of loads committed +system.cpu1.commit.membars 433641 # Number of memory barriers committed +system.cpu1.commit.branches 14069734 # Number of branches committed +system.cpu1.commit.fp_insts 5319 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 64506591 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2723384 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 49518046 67.26% 67.26% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57411 0.08% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 49512063 67.26% 67.26% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57459 0.08% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.34% # Class of committed instruction @@ -1827,36 +1830,36 @@ system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.34% # system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4212 0.01% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4198 0.01% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13287672 18.05% 85.39% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10754583 14.61% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13285136 18.05% 85.39% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10754672 14.61% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 73621924 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1853476 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 174663739 # The number of ROB reads -system.cpu1.rob.rob_writes 171729340 # The number of ROB writes -system.cpu1.timesIdled 397158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2646195 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2436737979 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60808588 # Number of Instructions Simulated -system.cpu1.committedOps 73547319 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.805700 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.805700 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.553802 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.553802 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 86393465 # number of integer regfile reads -system.cpu1.int_regfile_writes 49554201 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16619 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13036 # number of floating regfile writes -system.cpu1.cc_regfile_reads 280625358 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29714417 # number of cc regfile writes -system.cpu1.misc_regfile_reads 196041210 # number of misc regfile reads -system.cpu1.misc_regfile_writes 794463 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.cpu1.commit.op_class_0::total 73613528 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1851800 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 174575850 # The number of ROB reads +system.cpu1.rob.rob_writes 171636243 # The number of ROB writes +system.cpu1.timesIdled 396046 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2639276 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2436774880 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60795663 # Number of Instructions Simulated +system.cpu1.committedOps 73540007 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.805169 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.805169 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.553965 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.553965 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 86363747 # number of integer regfile reads +system.cpu1.int_regfile_writes 49530768 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16607 # number of floating regfile reads +system.cpu1.fp_regfile_writes 12960 # number of floating regfile writes +system.cpu1.cc_regfile_reads 280533576 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29711691 # number of cc regfile writes +system.cpu1.misc_regfile_reads 195918297 # number of misc regfile reads +system.cpu1.misc_regfile_writes 794253 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1907,66 +1910,66 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 49488500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 49485500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 336500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 87500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 631000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 623500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6424000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6415000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38406000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38220500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187814627 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187814925 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 0.981800 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.981737 # Cycle average of tags in use system.iocache.tags.total_refs 30 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234298498000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.981800 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061363 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061363 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 234297107000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.981737 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061359 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061359 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328227 # Number of tag accesses system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits @@ -1981,14 +1984,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31228377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31228377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4281194250 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4281194250 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4312422627 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4312422627 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4312422627 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4312422627 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31227677 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31227677 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4282542248 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4282542248 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4313769925 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4313769925 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4313769925 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4313769925 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2005,19 +2008,19 @@ system.iocache.demand_miss_rate::realview.ide 0.999205 system.iocache.demand_miss_rate::total 0.999205 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 0.999205 # miss rate for overall accesses system.iocache.overall_miss_rate::total 0.999205 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125415.168675 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125415.168675 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118281.371736 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118281.371736 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118330.112693 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118330.112693 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118330.112693 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118330.112693 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125412.357430 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125412.357430 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118318.614394 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118318.614394 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118367.081687 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118367.081687 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118367.081687 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118367.081687 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 191 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 95.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36160 # number of writebacks system.iocache.writebacks::total 36160 # number of writebacks @@ -2029,14 +2032,14 @@ system.iocache.demand_mshr_misses::realview.ide 36444 system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18778377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18778377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2469323520 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2469323520 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2488101897 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2488101897 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2488101897 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2488101897 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18777677 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18777677 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2470659836 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2470659836 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2489437513 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2489437513 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2489437513 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2489437513 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses @@ -2045,541 +2048,542 @@ system.iocache.demand_mshr_miss_rate::realview.ide 0.999205 system.iocache.demand_mshr_miss_rate::total 0.999205 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 0.999205 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.999205 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75415.168675 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75415.168675 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68222.779942 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68222.779942 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68271.921222 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68271.921222 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 104355 # number of replacements -system.l2c.tags.tagsinuse 65128.328748 # Cycle average of tags in use -system.l2c.tags.total_refs 5134809 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169609 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.274390 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75412.357430 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75412.357430 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68259.699848 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68259.699848 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68308.569669 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68308.569669 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68308.569669 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68308.569669 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 104028 # number of replacements +system.l2c.tags.tagsinuse 65127.134110 # Cycle average of tags in use +system.l2c.tags.total_refs 5124806 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169274 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.275211 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49028.426520 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.557440 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48520.895373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 39.974246 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4778.977549 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2180.200854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 47.031162 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5874.261984 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3173.872988 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.748114 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000695 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4816.133274 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2437.796190 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 54.318644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5831.963518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3426.052612 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.740370 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000610 # Average percentage of cache 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3222 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8987 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52579 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001190 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994507 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45400104 # Number of tag accesses -system.l2c.tags.data_accesses 45400104 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 35642 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36349 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6520 # number of ReadReq hits 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0.001963 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001600 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.953734 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.957037 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.955292 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.209302 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.247059 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.467831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477052 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.472247 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010429 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010744 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.026094 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.028051 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027102 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001797 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010429 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.187256 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001963 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.177061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061346 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001797 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010429 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.187256 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.177061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061346 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 79011.538462 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19025.488827 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19006.163328 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19016.300366 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 22500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 26062.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23687.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74553.909896 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73446.855402 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74020.277063 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72792.254723 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74047.051303 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73442.493725 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77301.849360 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80238.908689 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78877.563196 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 75203.703704 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19032.224532 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19005.417957 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19019.561243 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 25333.333333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24571.428571 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74496.032404 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73403.230565 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73967.357949 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72763.092194 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73971.355473 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73387.314067 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76326.381122 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80231.339564 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78408.731544 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72792.254723 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74796.357899 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74047.051303 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74176.500099 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74373.150825 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82887.096774 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72763.092194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74658.033027 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73971.355473 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74125.984304 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74279.429720 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76317.460317 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72792.254723 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74796.357899 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75507.462687 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74047.051303 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74176.500099 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74373.150825 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72763.092194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74658.033027 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74239.436620 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73971.355473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74125.984304 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74279.429720 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189673.215595 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190421.628395 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.323331 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189612.604888 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190492.027027 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187399.839529 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96036.774034 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106516.918005 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 100342.054263 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 356400 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 150200 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96002.883989 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106532.723700 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 100343.401563 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 355735 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 149872 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 31794 # Transaction distribution -system.membus.trans_dist::ReadResp 68215 # Transaction distribution +system.membus.trans_dist::ReadResp 68005 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131469 # Transaction distribution -system.membus.trans_dist::CleanEvict 9295 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131616 # Transaction distribution +system.membus.trans_dist::CleanEvict 8821 # Transaction distribution system.membus.trans_dist::UpgradeReq 4625 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 24 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 21 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138363 # Transaction distribution -system.membus.trans_dist::ReadExResp 138363 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36422 # Transaction distribution +system.membus.trans_dist::ReadExReq 138237 # Transaction distribution +system.membus.trans_dist::ReadExResp 138237 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36212 # Transaction distribution system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468971 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 576543 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 467969 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 575541 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648409 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 768 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17313372 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17477405 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17301276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17465309 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19792605 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19780509 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 523 # Total snoops (count) -system.membus.snoop_fanout::samples 275008 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019225 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137315 # Request fanout histogram +system.membus.snoopTraffic 33344 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 274669 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019252 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137411 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 269721 98.08% 98.08% # Request fanout histogram -system.membus.snoop_fanout::1 5287 1.92% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 269381 98.07% 98.07% # Request fanout histogram +system.membus.snoop_fanout::1 5288 1.93% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 275008 # Request fanout histogram -system.membus.reqLayer0.occupancy 95651000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 274669 # Request fanout histogram +system.membus.reqLayer0.occupancy 95445000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1705498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 922033211 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 921900685 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1008880500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1007122750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1321623 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1322824 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2611,84 +2615,85 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5615830 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2827503 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 47677 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5612083 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2825755 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 47584 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804580230500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 149204 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2640969 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 149636 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2639439 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 797793 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1934891 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 158843 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2863 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2955 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296757 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296757 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1935543 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 556294 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4761 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5806892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2681408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 36148 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 166774 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8691222 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247723648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99732765 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 53568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 288480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 347798461 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 141834 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3081573 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027702 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.164119 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 797877 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1933722 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 157607 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2864 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 85 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2948 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296722 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296722 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1934371 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 555503 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4762 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5803440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2678918 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 36089 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 166154 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8684601 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247577728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99675933 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 52660 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 284944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 347591265 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 142991 # Total snoops (count) +system.toL2Bus.snoopTraffic 6276420 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 3079674 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027770 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.164315 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2996206 97.23% 97.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 85367 2.77% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2994150 97.22% 97.22% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 85524 2.78% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3081573 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5532917883 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3079674 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5529901884 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 308377 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 310676 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2906129853 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2904308481 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1326155422 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1324888971 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 22791427 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 22963918 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 95110077 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 95377065 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index 30060be32..ce640090c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -24,12 +25,12 @@ exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -59,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -87,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -109,6 +121,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -153,12 +166,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu0.tracer workload= dcache_port=system.cpu0.dcache.cpu_side @@ -174,11 +192,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu0.dcache] type=Cache @@ -187,12 +212,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -211,8 +241,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -235,9 +270,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -251,9 +291,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -647,12 +692,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -671,8 +721,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -730,9 +785,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -746,9 +806,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -759,12 +824,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -782,6 +852,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -792,6 +863,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -808,8 +883,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -817,10 +897,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -852,6 +937,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -896,12 +982,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu1.tracer workload= dcache_port=system.cpu1.dcache.cpu_side @@ -917,11 +1008,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu1.dcache] type=Cache @@ -930,12 +1028,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -954,8 +1057,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -978,9 +1086,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -994,9 +1107,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -1390,12 +1508,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -1414,8 +1537,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1473,9 +1601,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1489,9 +1622,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -1502,12 +1640,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -1525,6 +1668,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -1535,6 +1679,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -1551,8 +1699,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -1560,10 +1713,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1608,9 +1766,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1624,12 +1787,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1648,8 +1816,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1660,12 +1833,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1684,21 +1862,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1710,11 +1898,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1725,6 +1918,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -1759,6 +1959,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1770,7 +1971,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1813,10 +2018,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1897,14 +2107,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1913,13 +2128,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1929,6 +2149,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1999,10 +2220,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -2082,17 +2308,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -2118,12 +2349,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -2131,14 +2368,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2224,14 +2466,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2240,13 +2487,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2255,13 +2507,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2269,11 +2526,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2287,11 +2549,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2305,19 +2572,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -2363,14 +2636,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2379,11 +2667,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2393,21 +2686,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2417,12 +2720,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2431,10 +2739,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2444,12 +2757,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2459,26 +2777,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2487,10 +2815,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2498,10 +2831,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2509,21 +2847,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2537,11 +2885,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2552,11 +2905,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2564,10 +2922,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2583,10 +2946,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr index 3c2cf37c0..8786c1b6c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr @@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout index 9920acce4..2aa1c9ae0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:31 -gem5 executing on phenom, pid 15970 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:03:52 +gem5 executing on e108600-lin, pid 24173 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47454492026000 because m5_exit instruction encountered +Exiting @ tick 47445489241000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index f2d1708bd..864e3d209 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.355903 # Number of seconds simulated -sim_ticks 47355903328000 # Number of ticks simulated -final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.445489 # Number of seconds simulated +sim_ticks 47445489241000 # Number of ticks simulated +final_tick 47445489241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170836 # Simulator instruction rate (inst/s) -host_op_rate 200933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9157476763 # Simulator tick rate (ticks/s) -host_mem_usage 772600 # Number of bytes of host memory used -host_seconds 5171.28 # Real time elapsed on the host -sim_insts 883443630 # Number of instructions simulated -sim_ops 1039082168 # Number of ops (including micro ops) simulated +host_inst_rate 208966 # Simulator instruction rate (inst/s) +host_op_rate 245756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10881126125 # Simulator tick rate (ticks/s) +host_mem_usage 759660 # Number of bytes of host memory used +host_seconds 4360.35 # Real time elapsed on the host +sim_insts 911162440 # Number of instructions simulated +sim_ops 1071583187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory -system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 163648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 157696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8375360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16685256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 18550592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 100224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 74048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2844864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7994832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10895744 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory +system.physmem.bytes_read::total 66279064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8375360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2844864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11220224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78621824 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory -system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78642408 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 130865 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 260720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 289853 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1566 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 124932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 170246 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1035636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1228466 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1231040 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 176526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 351672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 390987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 168506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 229648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1396952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 176526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 236487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1657098 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 977362 # Number of read requests accepted -system.physmem.writeReqs 1184351 # Number of write requests accepted -system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue -system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1657532 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1657098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 176526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 352106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 390987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 168506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 229648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3054484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1035636 # Number of read requests accepted +system.physmem.writeReqs 1231040 # Number of write requests accepted +system.physmem.readBursts 1035636 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1231040 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 66252160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 28544 # Total number of bytes read from write queue +system.physmem.bytesWritten 78640192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66279064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78642408 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 446 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54912 # Per bank write bursts -system.physmem.perBankRdBursts::1 56908 # Per bank write bursts -system.physmem.perBankRdBursts::2 51582 # Per bank write bursts -system.physmem.perBankRdBursts::3 63469 # Per bank write bursts -system.physmem.perBankRdBursts::4 61411 # Per bank write bursts -system.physmem.perBankRdBursts::5 61841 # Per bank write bursts -system.physmem.perBankRdBursts::6 57272 # Per bank write bursts -system.physmem.perBankRdBursts::7 62841 # Per bank write bursts -system.physmem.perBankRdBursts::8 51834 # Per bank write bursts -system.physmem.perBankRdBursts::9 112088 # Per bank write bursts -system.physmem.perBankRdBursts::10 55237 # Per bank write bursts -system.physmem.perBankRdBursts::11 58857 # Per bank write bursts -system.physmem.perBankRdBursts::12 56745 # Per bank write bursts -system.physmem.perBankRdBursts::13 58205 # Per bank write bursts -system.physmem.perBankRdBursts::14 53859 # Per bank write bursts -system.physmem.perBankRdBursts::15 59928 # Per bank write bursts -system.physmem.perBankWrBursts::0 69820 # Per bank write bursts -system.physmem.perBankWrBursts::1 73385 # Per bank write bursts -system.physmem.perBankWrBursts::2 70846 # Per bank write bursts -system.physmem.perBankWrBursts::3 76844 # Per bank write bursts -system.physmem.perBankWrBursts::4 76655 # Per bank write bursts -system.physmem.perBankWrBursts::5 78828 # Per bank write bursts -system.physmem.perBankWrBursts::6 72793 # Per bank write bursts -system.physmem.perBankWrBursts::7 76848 # Per bank write bursts -system.physmem.perBankWrBursts::8 69899 # Per bank write bursts -system.physmem.perBankWrBursts::9 74878 # Per bank write bursts -system.physmem.perBankWrBursts::10 69893 # Per bank write bursts -system.physmem.perBankWrBursts::11 73658 # Per bank write bursts -system.physmem.perBankWrBursts::12 73258 # Per bank write bursts -system.physmem.perBankWrBursts::13 76164 # Per bank write bursts -system.physmem.perBankWrBursts::14 72361 # Per bank write bursts -system.physmem.perBankWrBursts::15 75956 # Per bank write bursts +system.physmem.perBankRdBursts::0 59521 # Per bank write bursts +system.physmem.perBankRdBursts::1 66808 # Per bank write bursts +system.physmem.perBankRdBursts::2 62154 # Per bank write bursts +system.physmem.perBankRdBursts::3 70128 # Per bank write bursts +system.physmem.perBankRdBursts::4 60732 # Per bank write bursts +system.physmem.perBankRdBursts::5 72109 # Per bank write bursts +system.physmem.perBankRdBursts::6 58717 # Per bank write bursts +system.physmem.perBankRdBursts::7 62140 # Per bank write bursts +system.physmem.perBankRdBursts::8 50595 # Per bank write bursts +system.physmem.perBankRdBursts::9 107916 # Per bank write bursts +system.physmem.perBankRdBursts::10 54809 # Per bank write bursts +system.physmem.perBankRdBursts::11 63010 # Per bank write bursts +system.physmem.perBankRdBursts::12 57730 # Per bank write bursts +system.physmem.perBankRdBursts::13 64314 # Per bank write bursts +system.physmem.perBankRdBursts::14 61474 # Per bank write bursts +system.physmem.perBankRdBursts::15 63033 # Per bank write bursts +system.physmem.perBankWrBursts::0 75175 # Per bank write bursts +system.physmem.perBankWrBursts::1 80913 # Per bank write bursts +system.physmem.perBankWrBursts::2 75568 # Per bank write bursts +system.physmem.perBankWrBursts::3 82272 # Per bank write bursts +system.physmem.perBankWrBursts::4 75546 # Per bank write bursts +system.physmem.perBankWrBursts::5 83102 # Per bank write bursts +system.physmem.perBankWrBursts::6 75765 # Per bank write bursts +system.physmem.perBankWrBursts::7 76740 # Per bank write bursts +system.physmem.perBankWrBursts::8 69114 # Per bank write bursts +system.physmem.perBankWrBursts::9 73138 # Per bank write bursts +system.physmem.perBankWrBursts::10 71733 # Per bank write bursts +system.physmem.perBankWrBursts::11 77960 # Per bank write bursts +system.physmem.perBankWrBursts::12 74616 # Per bank write bursts +system.physmem.perBankWrBursts::13 78881 # Per bank write bursts +system.physmem.perBankWrBursts::14 78631 # Per bank write bursts +system.physmem.perBankWrBursts::15 79599 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 28 # Number of times write queue was full causing retry -system.physmem.totGap 47355901307500 # Total gap between requests +system.physmem.numWrRetry 48 # Number of times write queue was full causing retry +system.physmem.totGap 47445487151500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 977332 # Read request sizes (log2) +system.physmem.readPktSize::6 1035606 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1181777 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1228466 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 692790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45775 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 30940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 28399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 26620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 20889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,226 +189,224 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 27376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 68512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 70877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 79365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 82384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 78677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 77306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 73265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 67472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 64363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 144 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1012110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 143.157878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 97.072288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 192.644368 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 686114 67.79% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 195882 19.35% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 47037 4.65% 91.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20980 2.07% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15295 1.51% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9865 0.97% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6724 0.66% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5499 0.54% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24714 2.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1012110 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60277 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.173764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.670576 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60274 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60277 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60277 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.385105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.691366 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.394945 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 52026 86.31% 86.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2335 3.87% 90.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 778 1.29% 91.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 614 1.02% 92.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 994 1.65% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 490 0.81% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 334 0.55% 95.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 282 0.47% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 206 0.34% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 170 0.28% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 135 0.22% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 158 0.26% 97.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 477 0.79% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 137 0.23% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 123 0.20% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 110 0.18% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 87 0.14% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 84 0.14% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 91 0.15% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 102 0.17% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 72 0.12% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 71 0.12% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 64 0.11% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 59 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 43 0.07% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 45 0.07% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 41 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 40 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 47 0.08% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 20 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 11 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads -system.physmem.totQLat 32578317305 # Total ticks spent queuing -system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::156-159 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60277 # Writes before turning the bus around for reads +system.physmem.totQLat 35377622933 # Total ticks spent queuing +system.physmem.totMemAccLat 54787435433 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5175950000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34175.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52925.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing -system.physmem.readRowHits 734277 # Number of row buffer hits during reads -system.physmem.writeRowHits 451275 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes -system.physmem.avgGap 21906655.19 # Average gap between requests -system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.658673 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states +system.physmem.avgWrQLen 27.61 # Average write queue length when enqueuing +system.physmem.readRowHits 780044 # Number of row buffer hits during reads +system.physmem.writeRowHits 471783 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.39 # Row buffer hit rate for writes +system.physmem.avgGap 20931746.38 # Average gap between requests +system.physmem.pageHitRate 55.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3937837680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2148621750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3995955600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4050479520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1191842451045 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27421814259750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31726697931105 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.697958 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45618359398995 # Time in different power states +system.physmem_0.memoryStateTime::REF 1584308960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states +system.physmem_0.memoryStateTime::ACT 242820245005 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.651183 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states +system.physmem_1.actEnergy 3713615640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2026278375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4078440600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3911723280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1186342158240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27426639078000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31725619619895 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.675231 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45626361005854 # Time in different power states +system.physmem_1.memoryStateTime::REF 1584308960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states +system.physmem_1.memoryStateTime::ACT 234814164146 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 145452632 # Number of BP lookups -system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 160314756 # Number of BP lookups +system.cpu0.branchPred.condPredicted 112651620 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7238532 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 119384108 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 83018284 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 69.538807 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19042266 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1248322 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4272460 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2939923 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1332537 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 468796 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -438,63 +436,63 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 298304 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 329365 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 329365 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11619 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95372 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 329365 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 329365 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 329365 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 106991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23090.091690 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21491.120734 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15706.739319 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 105441 98.55% 98.55% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1327 1.24% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 42 0.04% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 69 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 106991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95372 89.14% 89.14% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11619 10.86% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106991 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 329365 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 329365 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106991 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 436356 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 93899745 # DTB read hits -system.cpu0.dtb.read_misses 250404 # DTB read misses -system.cpu0.dtb.write_hits 82108561 # DTB write hits -system.cpu0.dtb.write_misses 47900 # DTB write misses +system.cpu0.dtb.read_hits 103710651 # DTB read hits +system.cpu0.dtb.read_misses 276993 # DTB read misses +system.cpu0.dtb.write_hits 90811723 # DTB write hits +system.cpu0.dtb.write_misses 52372 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42132 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2205 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 11314 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 94150149 # DTB read accesses -system.cpu0.dtb.write_accesses 82156461 # DTB write accesses +system.cpu0.dtb.perms_faults 11590 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 103987644 # DTB read accesses +system.cpu0.dtb.write_accesses 90864095 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176008306 # DTB hits -system.cpu0.dtb.misses 298304 # DTB misses -system.cpu0.dtb.accesses 176306610 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 194522374 # DTB hits +system.cpu0.dtb.misses 329365 # DTB misses +system.cpu0.dtb.accesses 194851739 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -524,904 +522,912 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 65048 # Table walker walks requested -system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 72209 # Table walker walks requested +system.cpu0.itb.walker.walksLong 72209 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 611 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59557 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 72209 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 72209 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 72209 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 60168 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25971.338585 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23756.230706 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17963.019846 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 55134 91.63% 91.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3439 5.72% 97.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 6 0.01% 97.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1442 2.40% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 60168 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59557 98.98% 98.98% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 611 1.02% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60168 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 72209 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 72209 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 259203584 # ITB inst hits -system.cpu0.itb.inst_misses 65048 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60168 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 132377 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 285203366 # ITB inst hits +system.cpu0.itb.inst_misses 72209 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 30424 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 190431 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses -system.cpu0.itb.hits 259203584 # DTB hits -system.cpu0.itb.misses 65048 # DTB misses -system.cpu0.itb.accesses 259268632 # DTB accesses -system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 1023758481 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 285275575 # ITB inst accesses +system.cpu0.itb.hits 285203366 # DTB hits +system.cpu0.itb.misses 72209 # DTB misses +system.cpu0.itb.accesses 285275575 # DTB accesses +system.cpu0.numPwrStateTransitions 26302 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13151 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3564690271.200593 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 65409151988.663887 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3759 28.58% 28.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9361 71.18% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 2 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1988779311380 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13151 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 566247484441 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46879241756559 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 1132534446 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 483101155 # Number of instructions committed -system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.119139 # CPI: cycles per instruction -system.cpu0.ipc 0.471890 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction +system.cpu0.committedInsts 532076805 # Number of instructions committed +system.cpu0.committedOps 624758290 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 52154793 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4664 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93759282538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.128517 # CPI: cycles per instruction +system.cpu0.ipc 0.469811 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 432780145 69.27% 69.27% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1412970 0.23% 69.50% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 69899 0.01% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 79522 0.01% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.op_class_0::MemRead 99981749 16.00% 85.52% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 90434005 14.48% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 567019823 # Class of committed instruction +system.cpu0.op_class_0::total 624758290 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed -system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6026209 # number of replacements -system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 13151 # number of quiesce instructions executed +system.cpu0.tickCycles 847175236 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 285359210 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6574289 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.066535 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 184992173 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6574801 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.136543 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.066535 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992317 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992317 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits -system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses -system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 392594755 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 392594755 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 95401287 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 95401287 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 84287466 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 84287466 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321965 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 321965 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 280846 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 280846 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2060188 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2060188 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2061125 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2061125 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 179969599 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 179969599 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 180291564 # number of overall hits +system.cpu0.dcache.overall_hits::total 180291564 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3840217 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3840217 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2718306 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2718306 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 733729 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 733729 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 858022 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 858022 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 199658 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 199658 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197397 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 197397 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 7416545 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7416545 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 8150274 # number of overall misses +system.cpu0.dcache.overall_misses::total 8150274 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 59779296000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 59779296000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54754909500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 54754909500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 28457275000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 28457275000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2995014000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2995014000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4953933500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4953933500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3818500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3818500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 142991480500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 142991480500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 142991480500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 142991480500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 99241504 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 99241504 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 87005772 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 87005772 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1055694 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1055694 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1138868 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1138868 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2259846 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2259846 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2258522 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2258522 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 187386144 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 187386144 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 188441838 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 188441838 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038696 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038696 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031243 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031243 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.695021 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.695021 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.753399 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.753399 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088350 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088350 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.087401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.087401 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039579 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.039579 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.043251 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.043251 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15566.645322 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15566.645322 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20143.026392 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20143.026392 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33166.136766 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33166.136766 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15000.721233 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15000.721233 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25096.295790 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25096.295790 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19280.066460 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19280.066460 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17544.377097 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17544.377097 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks -system.cpu0.dcache.writebacks::total 6026220 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6574291 # number of writebacks +system.cpu0.dcache.writebacks::total 6574291 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 237792 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 237792 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1117306 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1117306 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 48445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 48445 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 60 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 60 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1355188 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1355188 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1355188 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1355188 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3602425 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3602425 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1601000 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1601000 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732137 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 732137 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 857932 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 857932 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 151213 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 151213 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197337 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 197337 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 6061357 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 6061357 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6793494 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6793494 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29793 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59193 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50925119500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50925119500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31536308500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 31536308500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16544300500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16544300500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 27594364000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 27594364000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1964885000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1964885000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4754516500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4754516500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110055792000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 110055792000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 126600092500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 126600092500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5675765000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5675765000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675765000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5675765000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036300 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036300 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018401 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018401 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.693513 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.693513 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753320 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753320 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.066913 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.066913 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.087374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.087374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032347 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032347 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036051 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036051 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14136.344129 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14136.344129 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19697.881636 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19697.881636 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22597.274144 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22597.274144 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32163.812517 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32163.812517 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12994.153942 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12994.153942 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24093.385934 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24093.385934 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 9817579 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18156.955942 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18156.955942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18635.490441 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18635.490441 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190506.662639 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190506.662639 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95885.746625 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95885.746625 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 10998491 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932591 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 274007938 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10999003 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.912070 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22037323000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932591 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits -system.cpu0.icache.overall_hits::total 249208397 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses -system.cpu0.icache.overall_misses::total 9818101 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 581012885 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 581012885 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 274007938 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 274007938 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 274007938 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 274007938 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 274007938 # number of overall hits +system.cpu0.icache.overall_hits::total 274007938 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 10999003 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 10999003 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 10999003 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 10999003 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 10999003 # number of overall misses +system.cpu0.icache.overall_misses::total 10999003 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 111429437000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 111429437000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 111429437000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 111429437000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 111429437000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 111429437000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 285006941 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 285006941 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 285006941 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 285006941 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 285006941 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 285006941 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038592 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.038592 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038592 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.038592 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038592 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.038592 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10130.867043 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10130.867043 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10130.867043 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10130.867043 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 9817579 # number of writebacks -system.cpu0.icache.writebacks::total 9817579 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9818101 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9818101 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9818101 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9818101 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9818101 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9818101 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 52299 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 52299 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94093068000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 94093068000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94093068000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 94093068000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94093068000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 94093068000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4837195500 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 105929935500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038592 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038592 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038592 # 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average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8833822 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8835143 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1166 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2829183 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 60.708141 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 787.823770 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.931229 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003513 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003705 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048085 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986532 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1356 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14748 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 1192777 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 3147716 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16192.217188 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 27546589 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3163437 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.707804 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15379.701531 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.199902 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 67.449935 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 674.865820 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.938702 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004285 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004117 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.041191 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.988295 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1251 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14390 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 7 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 574 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 643 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1176 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 611 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 933174 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 933174 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9093916 # 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number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 9093916 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4006713 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13829162 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12299 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8468 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 20767 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256901 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 256901 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195411 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 195411 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 279617 # 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number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 824986 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1402100 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 884711 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 3134926 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 82093 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59193 # 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number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3269289499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2944999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2944999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11923656997 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11923656997 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23030463500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23030463500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33712054495 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33712054495 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20896498500 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20896498500 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 349787000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23030463500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 45635711492 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 69451225992 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 349787000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23030463500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 45635711492 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 42685466504 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 112136692496 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5437142000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9855526500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5437142000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9855526500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027663 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997596 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997596 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215232 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215232 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075006 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248615 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248615 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734031 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734031 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.127464 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177578 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33942.280254 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48247.921077 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20579.127566 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20579.127566 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16567.541334 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16567.541334 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 588999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588999.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41547.435606 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41547.435606 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27916.187063 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30232.016808 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30232.016808 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33273.354564 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33273.354564 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30864.262300 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35770.124238 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182497.298023 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 120053.189675 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91854.476036 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 88395.921717 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 36072564 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 18399437 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3515 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2427957 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2427386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 1003133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 16585926 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::WriteReq 29400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 29400 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6083435 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 13283967 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 3350152 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1133444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 490495 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347636 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 543136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1366077 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1342549 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10999003 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5499511 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 903440 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 855584 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 33101096 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21166131 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 412052 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1345098 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 56024377 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1411186752 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 800229141 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1569912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5118984 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 2218104789 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7999072 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 122429440 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 26916994 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.103450 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.304616 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 24132997 89.66% 89.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2783426 10.34% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 571 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 26916994 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 35963769502 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 196401052 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 16580139110 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9441182874 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 215851922 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 705346257 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 123875539 # Number of BP lookups -system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits +system.cpu1.branchPred.lookups 118915951 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85033049 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5367569 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 89750040 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 63411692 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 70.653664 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 13468810 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 887929 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3084567 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 1998882 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1085685 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 396796 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1451,63 +1457,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 255224 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 246313 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 246313 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8582 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75463 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 246313 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 246313 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 246313 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84045 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22346.070557 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21064.042846 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 12361.258067 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 79296 94.35% 94.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 4004 4.76% 99.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 175 0.21% 99.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 458 0.54% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 22 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 27 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84045 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -766256056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -766256056 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -766256056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 75463 89.79% 89.79% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8582 10.21% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84045 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 246313 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 246313 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84045 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84045 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 330358 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 78594683 # DTB read hits -system.cpu1.dtb.read_misses 208094 # DTB read misses -system.cpu1.dtb.write_hits 69544419 # DTB write hits -system.cpu1.dtb.write_misses 47130 # DTB write misses +system.cpu1.dtb.read_hits 74020776 # DTB read hits +system.cpu1.dtb.read_misses 200548 # DTB read misses +system.cpu1.dtb.write_hits 65603987 # DTB write hits +system.cpu1.dtb.write_misses 45765 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34845 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6796 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 78802777 # DTB read accesses -system.cpu1.dtb.write_accesses 69591549 # DTB write accesses +system.cpu1.dtb.perms_faults 11277 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 74221324 # DTB read accesses +system.cpu1.dtb.write_accesses 65649752 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 148139102 # DTB hits -system.cpu1.dtb.misses 255224 # DTB misses -system.cpu1.dtb.accesses 148394326 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 139624763 # DTB hits +system.cpu1.dtb.misses 246313 # DTB misses +system.cpu1.dtb.accesses 139871076 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1537,911 +1549,899 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 62177 # Table walker walks requested -system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 60327 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60327 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52409 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60327 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60327 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60327 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 52954 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24879.980738 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23402.458623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13318.614145 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 48523 91.63% 91.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 3764 7.11% 98.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 13 0.02% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 577 1.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 8 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 52954 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -766782556 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -766782556 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -766782556 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 52409 98.97% 98.97% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 545 1.03% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 52954 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60327 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60327 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 219337574 # ITB inst hits -system.cpu1.itb.inst_misses 62177 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52954 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52954 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 113281 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 210682225 # ITB inst hits +system.cpu1.itb.inst_misses 60327 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24520 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 163777 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses -system.cpu1.itb.hits 219337574 # DTB hits -system.cpu1.itb.misses 62177 # DTB misses -system.cpu1.itb.accesses 219399751 # DTB accesses -system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 838096745 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 210742552 # ITB inst accesses +system.cpu1.itb.hits 210682225 # DTB hits +system.cpu1.itb.misses 60327 # DTB misses +system.cpu1.itb.accesses 210742552 # DTB accesses +system.cpu1.numPwrStateTransitions 10392 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5196 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9053828227.255966 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 188730440437.234528 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3531 67.96% 67.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1645 31.66% 99.62% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 9 0.17% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 7 0.13% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7351146453012 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5196 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 401797772178 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47043691468822 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 803603609 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 400342475 # Number of instructions committed -system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.093449 # CPI: cycles per instruction -system.cpu1.ipc 0.477681 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction -system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction +system.cpu1.committedInsts 379085635 # Number of instructions committed +system.cpu1.committedOps 446824897 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 44295367 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4823 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 94088042190 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.119847 # CPI: cycles per instruction +system.cpu1.ipc 0.471732 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 309274392 69.22% 69.22% # Class of committed instruction +system.cpu1.op_class_0::IntMult 866353 0.19% 69.41% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 49212 0.01% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 34424 0.01% 69.43% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.op_class_0::MemRead 71272038 15.95% 85.38% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 65328435 14.62% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 472062345 # Class of committed instruction +system.cpu1.op_class_0::total 446824897 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed -system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 4810857 # number of replacements -system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits -system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses -system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5196 # number of quiesce instructions executed +system.cpu1.tickCycles 627540865 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 176062744 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 4660684 # number of replacements +system.cpu1.dcache.tags.tagsinuse 434.489996 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 132775101 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4661196 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.485200 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8377585211000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.489996 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848613 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.848613 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 281793929 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 281793929 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 67965873 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 67965873 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 61015488 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 61015488 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190971 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 190971 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 44349 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 44349 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1561438 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1561438 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1518539 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1518539 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 129025710 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 129025710 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 129216681 # number of overall hits +system.cpu1.dcache.overall_hits::total 129216681 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2729495 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2729495 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2149690 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2149690 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 616052 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 616052 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 399927 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 399927 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 143085 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 143085 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 184951 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 184951 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5279112 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5279112 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5895164 # number of overall misses +system.cpu1.dcache.overall_misses::total 5895164 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39717227000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 39717227000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40094025500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 40094025500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9755721000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 9755721000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2101168500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2101168500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4571201000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4571201000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4144500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4144500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 89566973500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 89566973500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 89566973500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 89566973500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 70695368 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 70695368 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 63165178 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 63165178 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807023 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 807023 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 444276 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 444276 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1704523 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1704523 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1703490 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1703490 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 134304822 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 134304822 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 135111845 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 135111845 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038609 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038609 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034033 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034033 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763364 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763364 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.900177 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.900177 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083944 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083944 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108572 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108572 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039307 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.039307 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043632 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043632 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14551.126490 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14551.126490 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18651.073178 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18651.073178 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24393.754360 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24393.754360 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14684.757312 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14684.757312 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24715.740926 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24715.740926 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16966.295373 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16966.295373 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.296319 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15193.296319 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks -system.cpu1.dcache.writebacks::total 4810864 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4660691 # number of writebacks +system.cpu1.dcache.writebacks::total 4660691 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 132278 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 132278 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 894898 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 894898 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 69 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 69 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37558 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37558 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 59 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1027245 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1027245 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1027245 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1027245 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2597217 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2597217 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1254792 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1254792 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 615702 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 615702 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 399858 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 399858 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105527 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105527 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 184892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 184892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4251867 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4251867 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4867569 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4867569 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8793 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17884 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34245614000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34245614000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22880344500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22880344500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13431113500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13431113500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9350661500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9350661500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1405417000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1405417000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4384302500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4384302500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3898500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3898500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66476620000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 66476620000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79907733500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 79907733500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1305175500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1305175500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1305175500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1305175500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036738 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036738 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762930 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762930 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.900022 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.900022 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061910 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108537 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108537 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031658 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031658 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036026 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036026 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13185.503560 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13185.503560 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18234.372310 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18234.372310 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21814.308708 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21814.308708 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23384.955409 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23384.955409 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13318.079733 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.079733 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23712.775566 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23712.775566 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 8744967 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15634.689420 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15634.689420 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16416.353523 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16416.353523 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148433.469806 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 148433.469806 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 72980.065981 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 72980.065981 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 8014386 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.062567 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 202497896 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8014898 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.265187 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8368004575000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.062567 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990357 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990357 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits -system.cpu1.icache.overall_hits::total 210419103 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8745479 # number of overall misses -system.cpu1.icache.overall_misses::total 8745479 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88268174500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 88268174500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 88268174500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 88268174500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 88268174500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 88268174500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 219164582 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 219164582 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 219164582 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 219164582 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 429040515 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 429040515 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 202497896 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 202497896 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 202497896 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 202497896 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 202497896 # number of overall hits +system.cpu1.icache.overall_hits::total 202497896 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8014908 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8014908 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8014908 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8014908 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8014908 # number of overall misses +system.cpu1.icache.overall_misses::total 8014908 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 81330977500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 81330977500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 81330977500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 81330977500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 81330977500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 81330977500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 210512804 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 210512804 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 210512804 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 210512804 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 210512804 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 210512804 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038073 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.038073 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038073 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.038073 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038073 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.038073 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10147.462391 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10147.462391 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10147.462391 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10147.462391 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks -system.cpu1.icache.writebacks::total 8744967 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.writebacks::writebacks 8014386 # number of writebacks +system.cpu1.icache.writebacks::total 8014386 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8014908 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8014908 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8014908 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8014908 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8014908 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8014908 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77323524000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 77323524000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77323524000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 77323524000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77323524000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 77323524000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8766500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8766500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8766500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8766500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038073 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.038073 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.038073 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9647.462454 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92278.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92278.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6532358 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6532555 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 172 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2218428 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 44.102544 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.983954 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.763922 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003868 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002692 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048583 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.819065 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14164 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 771 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 263 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 457671450 # 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number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 40977863991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 63751744491 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 429270500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 326619000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22017991000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 40977863991 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 63751744491 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 506121 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169302 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 675423 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3026489 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3026489 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 10527431 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 10527431 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 221065 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 221065 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192879 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 192879 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 55 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1161 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5545 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7510 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 574 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 428778233 # 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mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029644 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998037 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998037 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998117 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998117 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # 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mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239653 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080980 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.272149 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.272149 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584803 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584803 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139801 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.192823 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28725.610709 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38948.299055 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20841.626813 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20841.626813 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16189.657767 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16189.657767 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 372944.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 372944.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31574.707002 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31574.707002 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26112.486981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25163.535220 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25163.535220 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26480.228622 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26480.228622 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26415.677887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29861.857270 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140420.846128 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139820.769577 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69040.511071 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 69121.030091 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 26150144 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13381244 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1969364 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1969026 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 338 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 732517 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12156991 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 9091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 9091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4007359 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 9735300 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2694691 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 886167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 430328 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337223 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 468486 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1067899 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1044213 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8014908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4433895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 458319 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 398059 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24044391 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15175224 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 343569 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1027712 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 40590896 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1025880832 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 583383788 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1306120 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3875096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1614445836 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6456023 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75189768 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 20132697 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.112928 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.316558 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 17859482 88.71% 88.71% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2272877 11.29% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 338 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 20132697 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 25974578977 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 179053447 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12025219550 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 6952751265 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 180351405 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 543399850 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40337 # Transaction distribution -system.iobus.trans_dist::ReadResp 40337 # Transaction distribution -system.iobus.trans_dist::WriteReq 136616 # Transaction distribution -system.iobus.trans_dist::WriteResp 136616 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40387 # Transaction distribution +system.iobus.trans_dist::ReadResp 40387 # Transaction distribution +system.iobus.trans_dist::WriteReq 136979 # Transaction distribution +system.iobus.trans_dist::WriteResp 136979 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2452,15 +2452,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231702 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231702 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47828 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2471,105 +2471,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513211 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42458502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 311001 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26063002 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34444001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570734934 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92958000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148142000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115611 # number of replacements -system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115832 # number of replacements +system.iocache.tags.tagsinuse 11.305903 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115848 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9127528857000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.833923 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.471980 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239620 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706619 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040883 # Number of tag accesses -system.iocache.tags.data_accesses 1040883 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1043016 # Number of tag accesses +system.iocache.tags.data_accesses 1043016 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses -system.iocache.demand_misses::total 115654 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115851 # number of demand (read+write) misses +system.iocache.demand_misses::total 115891 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115614 # number of overall misses -system.iocache.overall_misses::total 115654 # number of overall misses +system.iocache.overall_misses::realview.ide 115851 # number of overall misses +system.iocache.overall_misses::total 115891 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1647274031 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1652472031 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12886794903 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12886794903 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14534068934 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14539635934 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14534068934 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14539635934 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115851 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115891 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115851 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115891 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2584,52 +2584,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185775.801398 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185587.604560 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120455.347557 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120455.347557 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125459.577827 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125459.577827 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32243 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3515 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.172973 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106950 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2644,662 +2644,659 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135775.801398 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135587.604560 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70374.605950 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70374.605950 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1371243 # number of replacements -system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use -system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21329.379338 # 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Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79235647 # Number of tag accesses -system.l2c.tags.data_accesses 79235647 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 170119 # 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number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1934 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 66055 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 143274 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1578 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 52043 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 103878 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 792686 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 465421 # 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Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 197 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49413 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 3598 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 6999 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 179 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2209 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 15374 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31482 # 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average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.262097 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318773 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.286593 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.211304 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225618 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.217588 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595463 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.451567 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.535333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.206892 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.125236 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.206266 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.775396 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.429860 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.684337 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.225148 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.225148 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21504.428630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21588.308809 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21544.753533 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.736546 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.311801 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24602.095240 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78922.059614 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72763.810098 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76751.364510 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79262.094163 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83037.216747 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98969.705542 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20911.097724 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20861.825980 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20902.941631 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164491.491592 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122437.265840 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102255.861386 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82791.799858 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60191.589531 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 71855.534201 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3914348 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2362357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2871 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 91033 # Transaction distribution -system.membus.trans_dist::ReadResp 892432 # Transaction distribution -system.membus.trans_dist::WriteReq 38505 # Transaction distribution -system.membus.trans_dist::WriteResp 38505 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution -system.membus.trans_dist::CleanEvict 252869 # Transaction distribution -system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution -system.membus.trans_dist::UpgradeResp 22 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 90979 # Transaction distribution +system.membus.trans_dist::ReadResp 948459 # Transaction distribution +system.membus.trans_dist::WriteReq 38491 # Transaction distribution +system.membus.trans_dist::WriteResp 38491 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1228466 # Transaction distribution +system.membus.trans_dist::CleanEvict 265252 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443986 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 298688 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 143945 # Transaction distribution -system.membus.trans_dist::ReadExResp 126263 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution -system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 608511 # Total snoops (count) -system.membus.snoop_fanout::samples 2484071 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram +system.membus.trans_dist::ReadExReq 145286 # Transaction distribution +system.membus.trans_dist::ReadExResp 128554 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 857480 # Transaction distribution +system.membus.trans_dist::InvalidateReq 675140 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25980 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4768940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4917924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5156472 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 137639872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 137849185 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7281600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 145130785 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 603530 # Total snoops (count) +system.membus.snoopTraffic 179328 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2550056 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011955 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108685 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram -system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2519569 98.80% 98.80% # Request fanout histogram +system.membus.snoop_fanout::1 30487 1.20% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2484071 # Request fanout histogram -system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2550056 # Request fanout histogram +system.membus.reqLayer0.occupancy 103375494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21768496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8632891321 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5537724663 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45395946 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3342,78 +3339,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2830390 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12809826 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6934559 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2124865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 137043 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 124917 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 12126 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 90981 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4987806 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38491 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38491 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3972958 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 3104635 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 749262 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 382090 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1131352 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 306540 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 306540 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4897318 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 863164 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 835591 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11082342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7735233 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18817575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276628165 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 188875292 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 465503457 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2889580 # Total snoops (count) +system.toL2Bus.snoopTraffic 125478224 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8764836 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.360858 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.483121 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5614105 64.05% 64.05% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3138605 35.81% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 12126 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8764836 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9763497454 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2559907 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5082599079 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3859782501 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal index 049b0949c..74f9afa7a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000028] Console: colour dummy device 80x25
-[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000032] pid_max: default: 32768 minimum: 301
-[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000199] hw perfevents: no hardware support available
-[ 0.060051] CPU1: Booted secondary processor
-[ 1.080085] CPU2: failed to come online
-[ 2.100161] CPU3: failed to come online
-[ 2.100164] Brought up 2 CPUs
-[ 2.100165] SMP: Total of 2 processors activated.
-[ 2.100234] devtmpfs: initialized
-[ 2.100742] atomic64_test: passed
-[ 2.100794] regulator-dummy: no parameters
-[ 2.101157] NET: Registered protocol family 16
-[ 2.101296] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101304] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.102113] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.102117] Serial: AMBA PL011 UART driver
-[ 2.102318] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.102358] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.102933] console [ttyAMA0] enabled
-[ 2.103072] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.103132] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.103192] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.103250] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140336] 3V3: 3300 mV
-[ 2.140383] vgaarb: loaded
-[ 2.140429] SCSI subsystem initialized
-[ 2.140466] libata version 3.00 loaded.
-[ 2.140524] usbcore: registered new interface driver usbfs
-[ 2.140543] usbcore: registered new interface driver hub
-[ 2.140567] usbcore: registered new device driver usb
-[ 2.140593] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140621] PTP clock support registered
-[ 2.140762] Switched to clocksource arch_sys_counter
-[ 2.141783] NET: Registered protocol family 2
-[ 2.141863] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.141880] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.141897] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.141925] TCP: reno registered
-[ 2.141932] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141945] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141981] NET: Registered protocol family 1
-[ 2.142034] RPC: Registered named UNIX socket transport module.
-[ 2.142044] RPC: Registered udp transport module.
-[ 2.142052] RPC: Registered tcp transport module.
-[ 2.142061] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.142073] PCI: CLS 0 bytes, default 64
-[ 2.142235] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.142334] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.144468] fuse init (API version 7.23)
-[ 2.144588] msgmni has been set to 469
-[ 2.144697] io scheduler noop registered
-[ 2.144749] io scheduler cfq registered (default)
-[ 2.145214] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.145228] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.145239] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.145252] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.145262] pci_bus 0000:00: scanning bus
-[ 2.145274] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.145288] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.145302] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145340] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.145352] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.145363] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.145373] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.145384] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.145395] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.145406] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145441] pci_bus 0000:00: fixups for bus
-[ 2.145450] pci_bus 0000:00: bus scan returning with max=00
-[ 2.145462] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.145483] pci 0000:00:00.0: fixup irq: got 33
-[ 2.145492] pci 0000:00:00.0: assigning IRQ 33
-[ 2.145502] pci 0000:00:01.0: fixup irq: got 34
-[ 2.145511] pci 0000:00:01.0: assigning IRQ 34
-[ 2.145524] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.145538] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.145551] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.145564] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.145576] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.145587] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.145599] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.145610] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.146274] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.146553] ata_piix 0000:00:01.0: version 2.13
-[ 2.146565] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.146593] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.146864] scsi0 : ata_piix
-[ 2.146948] scsi1 : ata_piix
-[ 2.146979] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.146991] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.147095] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.147108] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.147123] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.147134] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290805] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290816] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290846] ata1.00: configured for UDMA/33
-[ 2.290909] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.291028] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.291029] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.291056] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.291067] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.291092] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.291248] sda: sda1
-[ 2.291370] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.411068] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.411082] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.411104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.411115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.411135] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.411147] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411217] usbcore: registered new interface driver usb-storage
-[ 2.411286] mousedev: PS/2 mouse device common for all mice
-[ 2.411453] usbcore: registered new interface driver usbhid
-[ 2.411463] usbhid: USB HID core driver
-[ 2.411495] TCP: cubic registered
-[ 2.411502] NET: Registered protocol family 17
- -[ 2.411975] devtmpfs: mounted
-[ 2.412025] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000023] Console: colour dummy device 80x25
+[ 0.000025] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000027] pid_max: default: 32768 minimum: 301
+[ 0.000038] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000039] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000155] hw perfevents: no hardware support available
+[ 0.060041] CPU1: Booted secondary processor
+[ 1.080079] CPU2: failed to come online
+[ 2.100151] CPU3: failed to come online
+[ 2.100154] Brought up 2 CPUs
+[ 2.100155] SMP: Total of 2 processors activated.
+[ 2.100226] devtmpfs: initialized
+[ 2.100722] atomic64_test: passed
+[ 2.100767] regulator-dummy: no parameters
+[ 2.101110] NET: Registered protocol family 16
+[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.101651] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.101655] Serial: AMBA PL011 UART driver
+[ 2.101841] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.101878] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.102452] console [ttyAMA0] enabled
+[ 2.102605] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.102668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.102733] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.102790] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140329] 3V3: 3300 mV
+[ 2.140389] vgaarb: loaded
+[ 2.140455] SCSI subsystem initialized
+[ 2.140504] libata version 3.00 loaded.
+[ 2.140588] usbcore: registered new interface driver usbfs
+[ 2.140613] usbcore: registered new interface driver hub
+[ 2.140641] usbcore: registered new device driver usb
+[ 2.140687] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140698] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140722] PTP clock support registered
+[ 2.140900] Switched to clocksource arch_sys_counter
+[ 2.142431] NET: Registered protocol family 2
+[ 2.142518] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.142535] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.142552] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.142574] TCP: reno registered
+[ 2.142581] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142593] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142627] NET: Registered protocol family 1
+[ 2.142670] RPC: Registered named UNIX socket transport module.
+[ 2.142681] RPC: Registered udp transport module.
+[ 2.142689] RPC: Registered tcp transport module.
+[ 2.142698] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.142710] PCI: CLS 0 bytes, default 64
+[ 2.142942] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.143052] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.145204] fuse init (API version 7.23)
+[ 2.145320] msgmni has been set to 469
+[ 2.145427] io scheduler noop registered
+[ 2.145479] io scheduler cfq registered (default)
+[ 2.145859] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.145872] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.145883] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.145896] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.145906] pci_bus 0000:00: scanning bus
+[ 2.145917] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.145930] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.145945] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.145979] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.145991] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.146002] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.146013] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.146024] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.146035] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.146046] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.146081] pci_bus 0000:00: fixups for bus
+[ 2.146089] pci_bus 0000:00: bus scan returning with max=00
+[ 2.146101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.146121] pci 0000:00:00.0: fixup irq: got 33
+[ 2.146129] pci 0000:00:00.0: assigning IRQ 33
+[ 2.146140] pci 0000:00:01.0: fixup irq: got 34
+[ 2.146149] pci 0000:00:01.0: assigning IRQ 34
+[ 2.146160] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.146173] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.146186] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.146199] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.146211] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.146222] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.146234] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.146245] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.146902] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.147174] ata_piix 0000:00:01.0: version 2.13
+[ 2.147184] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.147208] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.147469] scsi0 : ata_piix
+[ 2.147563] scsi1 : ata_piix
+[ 2.147592] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.147605] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.147706] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.147719] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.147733] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.147745] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290935] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290946] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290974] ata1.00: configured for UDMA/33
+[ 2.291028] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.291135] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.291142] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291184] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.291194] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.291214] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.291351] sda: sda1
+[ 2.291468] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.411201] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411215] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411238] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.411249] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411270] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.411282] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.411355] usbcore: registered new interface driver usb-storage
+[ 2.411408] mousedev: PS/2 mouse device common for all mice
+[ 2.411558] usbcore: registered new interface driver usbhid
+[ 2.411568] usbhid: USB HID core driver
+[ 2.411600] TCP: cubic registered
+[ 2.411608] NET: Registered protocol family 17
+ +[ 2.411985] devtmpfs: mounted
+[ 2.412018] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.460540] udevd[609]: starting version 182
+[ 2.450547] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.553667] random: dd urandom read with 18 bits of entropy available
+[ 2.513635] random: dd urandom read with 17 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.680995] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.641130] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini index 06d6a4eac..72828743e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -108,6 +121,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -152,12 +166,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu.tracer workload= dcache_port=system.cpu.dcache.cpu_side @@ -173,11 +192,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -186,13 +212,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -211,8 +241,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -235,9 +270,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -251,9 +291,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -647,13 +692,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -672,8 +721,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -731,9 +785,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -747,9 +806,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -760,13 +824,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -785,8 +853,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -794,9 +867,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -841,9 +920,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -857,13 +941,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -882,8 +970,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -891,9 +984,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -907,11 +1006,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -956,6 +1060,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -967,7 +1072,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1010,10 +1119,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1094,14 +1208,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1110,13 +1229,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1126,6 +1250,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1196,10 +1321,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1279,17 +1409,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1315,12 +1450,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1328,14 +1469,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1421,14 +1567,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1437,13 +1588,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1452,13 +1608,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1466,11 +1627,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1484,11 +1650,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1502,19 +1673,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1560,14 +1737,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1576,11 +1768,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1590,21 +1787,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1614,12 +1821,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1628,10 +1840,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1641,12 +1858,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1656,26 +1878,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1684,10 +1916,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1695,10 +1932,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1706,21 +1948,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1734,11 +1986,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1749,11 +2006,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1761,10 +2023,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr index 3c2cf37c0..082803b1b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr @@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout index 38e9235d4..0ddf66a62 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 13:24:25 -gem5 executing on e104799-lin, pid 9941 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:41:22 +gem5 executing on e108600-lin, pid 23124 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51667481628000 because m5_exit instruction encountered +Exiting @ tick 51660717372000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index d15bd2bbc..d21e89078 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.660653 # Number of seconds simulated -sim_ticks 51660652947000 # Number of ticks simulated -final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.660717 # Number of seconds simulated +sim_ticks 51660717372000 # Number of ticks simulated +final_tick 51660717372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170651 # Simulator instruction rate (inst/s) -host_op_rate 200523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9485631865 # Simulator tick rate (ticks/s) -host_mem_usage 683504 # Number of bytes of host memory used -host_seconds 5446.20 # Real time elapsed on the host -sim_insts 929398934 # Number of instructions simulated -sim_ops 1092086880 # Number of ops (including micro ops) simulated +host_inst_rate 187164 # Simulator instruction rate (inst/s) +host_op_rate 219920 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10422609624 # Simulator tick rate (ticks/s) +host_mem_usage 677216 # Number of bytes of host memory used +host_seconds 4956.60 # Real time elapsed on the host +sim_insts 927696922 # Number of instructions simulated +sim_ops 1090057089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory -system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 89631104 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 368128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 311744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10118784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 60722568 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 418176 # Number of bytes read from this memory +system.physmem.bytes_read::total 71939400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10118784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10118784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 88730048 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 89651684 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5915 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159842 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 964409 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1141233 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1400486 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 88750628 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 158106 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 948803 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1124066 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1386407 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1403059 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 198021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1194746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1413805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1734998 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1388980 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 195870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1175411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1392536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 195870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 195870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1717554 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1735396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1734998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1195144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3149201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1141233 # Number of read requests accepted -system.physmem.writeReqs 1403059 # Number of write requests accepted -system.physmem.readBursts 1141233 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1403059 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72990656 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48256 # Total number of bytes read from write queue -system.physmem.bytesWritten 89651072 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 73038088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 89651684 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 754 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1717952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1717554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 195870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1175809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3110488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1124066 # Number of read requests accepted +system.physmem.writeReqs 1388980 # Number of write requests accepted +system.physmem.readBursts 1124066 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1388980 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 71890560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue +system.physmem.bytesWritten 88748928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 71939400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 88750628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69460 # Per bank write bursts -system.physmem.perBankRdBursts::1 75077 # Per bank write bursts -system.physmem.perBankRdBursts::2 69733 # Per bank write bursts -system.physmem.perBankRdBursts::3 63631 # Per bank write bursts -system.physmem.perBankRdBursts::4 66485 # Per bank write bursts -system.physmem.perBankRdBursts::5 73840 # Per bank write bursts -system.physmem.perBankRdBursts::6 65699 # Per bank write bursts -system.physmem.perBankRdBursts::7 65290 # Per bank write bursts -system.physmem.perBankRdBursts::8 63012 # Per bank write bursts -system.physmem.perBankRdBursts::9 121917 # Per bank write bursts -system.physmem.perBankRdBursts::10 71008 # Per bank write bursts -system.physmem.perBankRdBursts::11 72120 # Per bank write bursts -system.physmem.perBankRdBursts::12 67529 # Per bank write bursts -system.physmem.perBankRdBursts::13 67730 # Per bank write bursts -system.physmem.perBankRdBursts::14 61491 # Per bank write bursts -system.physmem.perBankRdBursts::15 66457 # Per bank write bursts -system.physmem.perBankWrBursts::0 88448 # Per bank write bursts -system.physmem.perBankWrBursts::1 89667 # Per bank write bursts -system.physmem.perBankWrBursts::2 88153 # Per bank write bursts -system.physmem.perBankWrBursts::3 85223 # Per bank write bursts -system.physmem.perBankWrBursts::4 87614 # Per bank write bursts -system.physmem.perBankWrBursts::5 91670 # Per bank write bursts -system.physmem.perBankWrBursts::6 83331 # Per bank write bursts -system.physmem.perBankWrBursts::7 85393 # Per bank write bursts -system.physmem.perBankWrBursts::8 84672 # Per bank write bursts -system.physmem.perBankWrBursts::9 89835 # Per bank write bursts -system.physmem.perBankWrBursts::10 89185 # Per bank write bursts -system.physmem.perBankWrBursts::11 91387 # Per bank write bursts -system.physmem.perBankWrBursts::12 86991 # Per bank write bursts -system.physmem.perBankWrBursts::13 87934 # Per bank write bursts -system.physmem.perBankWrBursts::14 84251 # Per bank write bursts -system.physmem.perBankWrBursts::15 87044 # Per bank write bursts +system.physmem.perBankRdBursts::0 65344 # Per bank write bursts +system.physmem.perBankRdBursts::1 73127 # Per bank write bursts +system.physmem.perBankRdBursts::2 68334 # Per bank write bursts +system.physmem.perBankRdBursts::3 62589 # Per bank write bursts +system.physmem.perBankRdBursts::4 65747 # Per bank write bursts +system.physmem.perBankRdBursts::5 73971 # Per bank write bursts +system.physmem.perBankRdBursts::6 66723 # Per bank write bursts +system.physmem.perBankRdBursts::7 65172 # Per bank write bursts +system.physmem.perBankRdBursts::8 63356 # Per bank write bursts +system.physmem.perBankRdBursts::9 122297 # Per bank write bursts +system.physmem.perBankRdBursts::10 70526 # Per bank write bursts +system.physmem.perBankRdBursts::11 71466 # Per bank write bursts +system.physmem.perBankRdBursts::12 64199 # Per bank write bursts +system.physmem.perBankRdBursts::13 65172 # Per bank write bursts +system.physmem.perBankRdBursts::14 60121 # Per bank write bursts +system.physmem.perBankRdBursts::15 65146 # Per bank write bursts +system.physmem.perBankWrBursts::0 84316 # Per bank write bursts +system.physmem.perBankWrBursts::1 87030 # Per bank write bursts +system.physmem.perBankWrBursts::2 86821 # Per bank write bursts +system.physmem.perBankWrBursts::3 84154 # Per bank write bursts +system.physmem.perBankWrBursts::4 87756 # Per bank write bursts +system.physmem.perBankWrBursts::5 92254 # Per bank write bursts +system.physmem.perBankWrBursts::6 85357 # Per bank write bursts +system.physmem.perBankWrBursts::7 85828 # Per bank write bursts +system.physmem.perBankWrBursts::8 86266 # Per bank write bursts +system.physmem.perBankWrBursts::9 90537 # Per bank write bursts +system.physmem.perBankWrBursts::10 89139 # Per bank write bursts +system.physmem.perBankWrBursts::11 90914 # Per bank write bursts +system.physmem.perBankWrBursts::12 83868 # Per bank write bursts +system.physmem.perBankWrBursts::13 84845 # Per bank write bursts +system.physmem.perBankWrBursts::14 82305 # Per bank write bursts +system.physmem.perBankWrBursts::15 85312 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 34 # Number of times write queue was full causing retry -system.physmem.totGap 51660651059000 # Total gap between requests +system.physmem.numWrRetry 29 # Number of times write queue was full causing retry +system.physmem.totGap 51660715485000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1141218 # Read request sizes (log2) +system.physmem.readPktSize::6 1124051 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1400486 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1073017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1386407 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1060868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,168 +160,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 34323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 78472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 82705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 81025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 81933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 85813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 81235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 82570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 85921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 85182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 80817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 79743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648791 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.683724 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.960276 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 285.693480 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 280366 43.21% 43.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 167406 25.80% 69.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61019 9.41% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 33573 5.17% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23084 3.56% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16255 2.51% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11383 1.75% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9506 1.47% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46199 7.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648791 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 76825 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.845063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.168306 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 76822 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 33876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 77727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 79574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 81890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 80157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 81104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 84995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 84344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 80623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 81914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 84683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 81947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 83786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 79897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 78990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 78233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 638647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.530251 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.310832 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 286.508507 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 275744 43.18% 43.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 164283 25.72% 68.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60231 9.43% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 32872 5.15% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22951 3.59% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16028 2.51% 89.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11191 1.75% 91.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9395 1.47% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 45952 7.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 638647 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 75991 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.781369 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 142.935713 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 75988 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 76825 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 76825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.233622 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.685886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.065993 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64901 84.48% 84.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9488 12.35% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 481 0.63% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 307 0.40% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 57 0.07% 97.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 121 0.16% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 251 0.33% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 28 0.04% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 303 0.39% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 81 0.11% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 29 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 51 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 317 0.41% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 31 0.04% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 113 0.15% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 181 0.24% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 75991 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 75991 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.248240 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.695683 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.085121 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 64109 84.36% 84.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9386 12.35% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 485 0.64% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 369 0.49% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 63 0.08% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 114 0.15% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 258 0.34% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 31 0.04% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 303 0.40% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 66 0.09% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 30 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 60 0.08% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 313 0.41% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 41 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 27 0.04% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 117 0.15% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 162 0.21% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 21 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 76825 # Writes before turning the bus around for reads -system.physmem.totQLat 16555348236 # Total ticks spent queuing -system.physmem.totMemAccLat 37939329486 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5702395000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14516.14 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 75991 # Writes before turning the bus around for reads +system.physmem.totQLat 16312474093 # Total ticks spent queuing +system.physmem.totMemAccLat 37374161593 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5616450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14522.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33266.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.74 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 33272.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing -system.physmem.readRowHits 872195 # Number of row buffer hits during reads -system.physmem.writeRowHits 1020290 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.84 # Row buffer hit rate for writes -system.physmem.avgGap 20304529.14 # Average gap between requests -system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2468362680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1346824875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4283830200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4532753520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1318333461255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29839955813250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34545143413140 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.693578 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49640663734133 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725062560000 # Time in different power states +system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing +system.physmem.readRowHits 859362 # Number of row buffer hits during reads +system.physmem.writeRowHits 1011981 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.98 # Row buffer hit rate for writes +system.physmem.avgGap 20557011.49 # Average gap between requests +system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2420719560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1320829125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4219854600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4493983680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1315006290315 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29842911750000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34544599863120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682250 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49645601262378 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725064640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 294925880867 # Time in different power states +system.physmem_0.memoryStateTime::ACT 290044177622 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2436497280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1329438000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4611859200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4544417520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1316960739945 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.695937 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states +system.physmem_1.actEnergy 2407451760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1313589750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4541752800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4491845280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1315022855940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29842897218750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34544901150120 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.688082 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49645554021211 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725064640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states +system.physmem_1.memoryStateTime::ACT 290092863289 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -338,30 +334,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 256209592 # Number of BP lookups -system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12215343 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 188533609 # Number of BTB lookups -system.cpu.branchPred.BTBHits 127068742 # Number of BTB hits +system.cpu.branchPred.lookups 256052360 # Number of BP lookups +system.cpu.branchPred.condPredicted 178125867 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12215850 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 188334497 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126943208 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 67.403057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31309548 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2129742 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7077002 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5011250 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2065752 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 841782 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,65 +387,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 561578 # Table walker walks requested -system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 200160 98.78% 98.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2084 1.03% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 75 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 137 0.07% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 55 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 85 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 202628 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 181762 89.70% 89.70% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20867 10.30% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 202629 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561578 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 558947 # Table walker walks requested +system.cpu.dtb.walker.walksLong 558947 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 19870 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181727 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 558947 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 558947 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 558947 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 201597 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 27104.207900 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22942.325413 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21051.309840 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 199234 98.83% 98.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2010 1.00% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 59 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 201597 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -1569310592 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1569310592 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -1569310592 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 181728 90.14% 90.14% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 19870 9.86% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 201598 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 558947 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561578 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202629 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 558947 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 201598 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202629 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 764207 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 201598 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 760545 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 179568747 # DTB read hits -system.cpu.dtb.read_misses 462708 # DTB read misses -system.cpu.dtb.write_hits 159223685 # DTB write hits -system.cpu.dtb.write_misses 98870 # DTB write misses +system.cpu.dtb.read_hits 179275780 # DTB read hits +system.cpu.dtb.read_misses 461379 # DTB read misses +system.cpu.dtb.write_hits 158920483 # DTB write hits +system.cpu.dtb.write_misses 97568 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78930 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 78530 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1411 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14509 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 180031455 # DTB read accesses -system.cpu.dtb.write_accesses 159322555 # DTB write accesses +system.cpu.dtb.perms_faults 22879 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 179737159 # DTB read accesses +system.cpu.dtb.write_accesses 159018051 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 338792432 # DTB hits -system.cpu.dtb.misses 561578 # DTB misses -system.cpu.dtb.accesses 339354010 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 338196263 # DTB hits +system.cpu.dtb.misses 558947 # DTB misses +system.cpu.dtb.accesses 338755210 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -479,68 +475,69 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 133823 # Table walker walks requested -system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30581.308427 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 115208 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 97.65% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2538 2.15% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 65 0.06% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 122 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 18 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 134834 # Table walker walks requested +system.cpu.itb.walker.walksLong 134834 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117333 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 134834 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 134834 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 134834 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118400 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30431.579392 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25904.631312 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24094.406061 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 115676 97.70% 97.70% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5 0.00% 97.70% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2464 2.08% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.10% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 17 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 117989 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 116932 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1057 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 117989 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118400 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1570341092 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1570341092 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1570341092 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 117333 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1067 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118400 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 133823 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 133823 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134834 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 134834 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 117989 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 117989 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 251812 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 442793055 # ITB inst hits -system.cpu.itb.inst_misses 133823 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118400 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118400 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 253234 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 442741882 # ITB inst hits +system.cpu.itb.inst_misses 134834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56526 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 56540 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 318606 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 442926878 # ITB inst accesses -system.cpu.itb.hits 442793055 # DTB hits -system.cpu.itb.misses 133823 # DTB misses -system.cpu.itb.accesses 442926878 # DTB accesses -system.cpu.numPwrStateTransitions 33032 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16516 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3050356912.427888 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59773934276.156128 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7219 43.71% 43.71% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.08% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 442876716 # ITB inst accesses +system.cpu.itb.hits 442741882 # DTB hits +system.cpu.itb.misses 134834 # DTB misses +system.cpu.itb.accesses 442876716 # DTB accesses +system.cpu.numPwrStateTransitions 33004 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16502 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3052827188.483881 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59796953066.006256 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7205 43.66% 43.66% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.13% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state @@ -551,563 +548,561 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988777743356 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16516 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1280958181341 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50379694765659 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2561963341 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988777699120 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16502 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1282963107639 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50377754264361 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2565980290 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 929398934 # Number of instructions committed -system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed -system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.756581 # CPI: cycles per instruction -system.cpu.ipc 0.362768 # IPC: instructions per cycle +system.cpu.committedInsts 927696922 # Number of instructions committed +system.cpu.committedOps 1090057089 # Number of ops (including micro ops) committed +system.cpu.discardedOps 94830796 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7642 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100756547271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.765968 # CPI: cycles per instruction +system.cpu.ipc 0.361537 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 756821893 69.30% 69.30% # Class of committed instruction -system.cpu.op_class_0::IntMult 2277263 0.21% 69.51% # Class of committed instruction -system.cpu.op_class_0::IntDiv 98455 0.01% 69.52% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 109444 0.01% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::MemRead 174118935 15.94% 85.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 755349201 69.29% 69.29% # Class of committed instruction +system.cpu.op_class_0::IntMult 2273269 0.21% 69.50% # Class of committed instruction +system.cpu.op_class_0::IntDiv 98990 0.01% 69.51% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 109509 0.01% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu.op_class_0::MemRead 173855507 15.95% 85.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 158370570 14.53% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1092086880 # Class of committed instruction +system.cpu.op_class_0::total 1090057089 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed -system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked -system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 10826762 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 16502 # number of quiesce instructions executed +system.cpu.tickCycles 1756726391 # Number of cycles that the object actually ticked +system.cpu.idleCycles 809253899 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 10800470 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930063 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322845784 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10800982 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.890410 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7088310500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930063 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148654336 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 515490 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 515490 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336587 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336587 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3899601 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3899601 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4208890 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4208890 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 314122591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 314122591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 314638081 # number of overall hits -system.cpu.dcache.overall_hits::total 314638081 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6423881 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6423881 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4177328 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4177328 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1420881 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1420881 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1240100 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1240100 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 311002 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 311002 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 11841309 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11841309 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13262190 # number of overall misses -system.cpu.dcache.overall_misses::total 13262190 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 119203222500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 119203222500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 206322817500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 206322817500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53471775500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 53471775500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5200645500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5200645500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 378997815500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 378997815500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 378997815500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 378997815500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 171555549 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 171555549 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 152831664 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 152831664 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1936371 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1936371 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576687 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1576687 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4210603 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4210603 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4208892 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4208892 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 325963900 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 325963900 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 327900271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 327900271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037445 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037445 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027333 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027333 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733786 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.733786 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786523 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786523 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073862 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073862 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1354272764 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1354272764 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 165477998 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 165477998 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148389977 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148389977 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 514152 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 514152 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336855 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336855 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3884412 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3884412 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4194010 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4194010 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 314204830 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 314204830 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 314718982 # number of overall hits +system.cpu.dcache.overall_hits::total 314718982 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5939711 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5939711 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4167073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4167073 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1413293 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1413293 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1239143 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1239143 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 311310 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 311310 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 11345927 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11345927 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12759220 # number of overall misses +system.cpu.dcache.overall_misses::total 12759220 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 110013337000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 110013337000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 204497661000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 204497661000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53262030500 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 53262030500 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5161319000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5161319000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 367773028500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 367773028500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 367773028500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 367773028500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 171417709 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 171417709 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 152557050 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 152557050 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1927445 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1927445 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1575998 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1575998 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4195722 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4195722 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4194011 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4194011 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 325550757 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 325550757 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 327478202 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 327478202 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034651 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.034651 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027315 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027315 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.733247 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.733247 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786259 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786259 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074197 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074197 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036327 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036327 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040446 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040446 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18556.262562 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18556.262562 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49391.098209 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16722.225259 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16722.225259 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32006.412087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32006.412087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28577.317585 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28577.317585 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.034851 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034851 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038962 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038962 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18521.664943 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18521.664943 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49074.652880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49074.652880 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42982.957173 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42982.957173 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16579.354984 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16579.354984 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32414.542108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32414.542108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28824.099631 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28824.099631 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8312311 # number of writebacks -system.cpu.dcache.writebacks::total 8312311 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778551 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 778551 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1841560 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1841560 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 166 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 166 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69564 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69564 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2620277 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2620277 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2620277 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2620277 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5645330 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5645330 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2335768 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2335768 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1413353 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1413353 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239934 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1239934 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241438 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 241438 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9221032 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9221032 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 10634385 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 10634385 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 8297164 # number of writebacks +system.cpu.dcache.writebacks::total 8297164 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 307308 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 307308 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1836532 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1836532 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 159 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 159 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69724 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 69724 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2143999 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2143999 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2143999 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2143999 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5632403 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5632403 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2330541 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2330541 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1405812 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1405812 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238984 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1238984 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241586 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 241586 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9201928 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9201928 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 10607740 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 10607740 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97557432500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 97557432500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109336281500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109336281500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26901290500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26901290500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52221764000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52221764000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3529658500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3529658500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 259115478000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 259115478000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286016768500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 286016768500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197628500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197628500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197628500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197628500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032907 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032907 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729898 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729898 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786417 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786417 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057340 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057340 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96403190500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 96403190500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108391524000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 108391524000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26704093000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26704093000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 52015388000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 52015388000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3504907500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3504907500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256810102500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 256810102500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283514195500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 283514195500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197989500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197989500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6197989500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6197989500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032858 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032858 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.729366 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.729366 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786158 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786158 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057579 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057579 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028289 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028289 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032432 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17281.085871 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17281.085871 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46809.563921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46809.563921 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19033.667102 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19033.667102 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 42116.567495 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 42116.567495 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14619.316346 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14619.316346 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28100.485716 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28100.485716 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26895.468661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26895.468661 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24339101 # number of replacements -system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24339613 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.178953 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 32773385500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.885333 # Average occupied blocks per requestor +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028266 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032392 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032392 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17115.819039 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17115.819039 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46509.168472 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46509.168472 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18995.493708 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18995.493708 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41982.291942 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41982.291942 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14507.908157 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14507.908157 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27908.292969 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27908.292969 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26727.106386 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26727.106386 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183932.976229 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183932.976229 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91954.208270 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91954.208270 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24348068 # number of replacements +system.cpu.icache.tags.tagsinuse 511.885312 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 418063563 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24348580 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.169936 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 32786837500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.885312 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses -system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 418129059 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 418129059 # number of overall hits -system.cpu.icache.overall_hits::total 418129059 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24339623 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24339623 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24339623 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24339623 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24339623 # number of overall misses -system.cpu.icache.overall_misses::total 24339623 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329768536500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329768536500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329768536500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329768536500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329768536500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329768536500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 442468682 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 442468682 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 442468682 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 442468682 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 442468682 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 442468682 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13539.147257 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13539.147257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13539.147257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24339101 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305428914500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 305428914500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055009 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.055009 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.055009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12548.629636 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12548.629636 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12548.629636 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12548.629636 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1529682 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1592715 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 41.651953 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10458336000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36843.538434 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 325.022996 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 386.025396 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8031.083741 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19745.157287 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.562188 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004959 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005890 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.301287 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996869 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 238 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62795 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 461 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2479 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5541 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54260 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8312311 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8312311 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 24335620 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 24335620 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 10528 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 10528 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1643656 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1643656 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24232057 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712542500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5935856500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5776686000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11712542500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782932 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782932 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782369 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782369 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281473 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281473 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004419 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044081 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044081 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.433198 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.433198 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030853 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030853 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127272.008692 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.417428 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.417428 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122748.217880 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122748.217880 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122464.475999 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122464.475999 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125035.706823 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125035.706823 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.462277 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.462277 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123444.210366 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85698.351705 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97838.144881 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.278818 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.278818 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004346 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043089 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043089 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.431195 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.431195 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030370 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030370 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126911.936364 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67985.168034 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67985.168034 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122812.641665 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122812.641665 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122437.282746 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122437.282746 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124905.908758 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124905.908758 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69672.880744 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69672.880744 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.275692 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136182.853522 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85703.692714 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97839.335238 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 71038022 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35888421 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4192 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2302 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2302 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1730261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33359239 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9712830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24339101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2759131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 48504 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 48506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2287534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2287534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24339623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7308730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1346598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1239934 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73122960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32713992 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 682590 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2171018 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 108690560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3118785792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1145820498 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2260056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7404048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4274270394 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2199102 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 38741497 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018274 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133941 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 9683600 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24348068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2741013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 48305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 48306 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2282432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2282432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24348590 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7288491 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1345648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1238984 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73149864 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32634714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 686896 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 108635282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3119933760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1143229458 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2270312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7381280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4272814810 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2178284 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 92284400 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 38701577 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018037 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133086 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38033532 98.17% 98.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 707965 1.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38003503 98.20% 98.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 698074 1.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 38741497 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 68741576495 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 38701577 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 68717300491 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1462889 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1477390 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36594790182 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36605927318 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15076717704 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15037927648 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 400149367 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 403140932 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1241184926 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40324 # Transaction distribution -system.iobus.trans_dist::ReadResp 40324 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40331 # Transaction distribution +system.iobus.trans_dist::ReadResp 40331 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1318,11 +1314,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231020 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231020 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353804 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1337,102 +1333,102 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334512 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37107000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37711500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25573000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25249000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34140500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36460500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567103107 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567164602 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147780000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115492 # number of replacements +system.iocache.tags.tagsinuse 10.441393 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115508 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153318095000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.521307 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.919947 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13153371816000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.521310 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.920084 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432505 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652587 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039884 # Number of tag accesses -system.iocache.tags.data_accesses 1039884 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039947 # Number of tag accesses +system.iocache.tags.data_accesses 1039947 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8846 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8883 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115503 # number of demand (read+write) misses -system.iocache.demand_misses::total 115543 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115510 # number of demand (read+write) misses +system.iocache.demand_misses::total 115550 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115503 # number of overall misses -system.iocache.overall_misses::total 115543 # number of overall misses +system.iocache.overall_misses::realview.ide 115510 # number of overall misses +system.iocache.overall_misses::total 115550 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1644126101 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1649196101 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1687962584 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1693032584 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13411893006 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13411893006 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13411761018 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13411761018 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15056019107 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15061440107 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15099723602 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15105144602 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15056019107 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15061440107 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15099723602 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15105144602 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8883 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115503 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115543 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115510 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115550 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115503 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115543 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115510 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115550 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1447,52 +1443,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185803.977129 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 190816.480217 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190592.433187 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125738.403004 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125738.403004 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130353.548956 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130723.882319 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130351.758024 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130353.548956 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130723.882319 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34055 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3409 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.989733 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8883 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115503 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115543 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115510 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115550 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115503 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115543 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115510 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115550 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1245662584 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1248882584 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073418582 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8073418582 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9275723962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9279144962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9319081166 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9322502166 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9275723962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9279144962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9319081166 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9322502166 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1507,87 +1503,88 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140816.480217 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140592.433187 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75690.191461 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75690.191461 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 535040 # Transaction distribution +system.membus.trans_dist::ReadResp 525005 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution -system.membus.trans_dist::CleanEvict 243574 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 643252 # Transaction distribution -system.membus.trans_dist::ReadExResp 643252 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 449034 # Transaction distribution -system.membus.trans_dist::InvalidateReq 643674 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1386407 # Transaction distribution +system.membus.trans_dist::CleanEvict 236604 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38552 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 635760 # Transaction distribution +system.membus.trans_dist::ReadExResp 635760 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 438999 # Transaction distribution +system.membus.trans_dist::InvalidateReq 640771 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4380248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4509900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4747095 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4321043 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4450695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4688271 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155470700 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155641106 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7219072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7219072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 162860178 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3374 # Total snoops (count) -system.membus.snoop_fanout::samples 3538498 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 153447468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 153617874 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7242560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 160860434 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3013 # Total snoops (count) +system.membus.snoopTraffic 192384 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 3496836 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3538498 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3496836 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3538498 # Request fanout histogram -system.membus.reqLayer0.occupancy 97241000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3496836 # Request fanout histogram +system.membus.reqLayer0.occupancy 99852500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5639000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5614500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9317752261 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9224879373 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6128850630 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6035081327 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44925690 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1630,28 +1627,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal index 9a18d3243..5bd114d12 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000032] Console: colour dummy device 80x25
-[ 0.000035] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000037] pid_max: default: 32768 minimum: 301
-[ 0.000053] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000054] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000248] hw perfevents: no hardware support available
+[ 0.000031] Console: colour dummy device 80x25
+[ 0.000034] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000036] pid_max: default: 32768 minimum: 301
+[ 0.000052] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000053] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000228] hw perfevents: no hardware support available
[ 1.060097] CPU1: failed to come online
-[ 2.080186] CPU2: failed to come online
-[ 3.100276] CPU3: failed to come online
-[ 3.100280] Brought up 1 CPUs
-[ 3.100282] SMP: Total of 1 processors activated.
+[ 2.080187] CPU2: failed to come online
+[ 3.100278] CPU3: failed to come online
+[ 3.100282] Brought up 1 CPUs
+[ 3.100283] SMP: Total of 1 processors activated.
[ 3.100367] devtmpfs: initialized
-[ 3.101026] atomic64_test: passed
-[ 3.101090] regulator-dummy: no parameters
-[ 3.101671] NET: Registered protocol family 16
-[ 3.101853] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101865] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.103085] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.103092] Serial: AMBA PL011 UART driver
-[ 3.103368] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.103418] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.103982] console [ttyAMA0] enabled
-[ 3.104097] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.104134] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.104172] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.104207] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130720] 3V3: 3300 mV
+[ 3.101019] atomic64_test: passed
+[ 3.101081] regulator-dummy: no parameters
+[ 3.101652] NET: Registered protocol family 16
+[ 3.101829] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101840] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.102554] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.102561] Serial: AMBA PL011 UART driver
+[ 3.102830] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.102879] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.103440] console [ttyAMA0] enabled
+[ 3.103555] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.103592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.103630] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.103665] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130723] 3V3: 3300 mV
[ 3.130781] vgaarb: loaded
[ 3.130844] SCSI subsystem initialized
[ 3.130897] libata version 3.00 loaded.
-[ 3.130958] usbcore: registered new interface driver usbfs
-[ 3.130980] usbcore: registered new interface driver hub
-[ 3.131022] usbcore: registered new device driver usb
-[ 3.131056] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131065] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131086] PTP clock support registered
-[ 3.131251] Switched to clocksource arch_sys_counter
-[ 3.132743] NET: Registered protocol family 2
-[ 3.132852] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.132877] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.132908] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.132927] TCP: reno registered
-[ 3.132934] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132951] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.133006] NET: Registered protocol family 1
-[ 3.133062] RPC: Registered named UNIX socket transport module.
-[ 3.133072] RPC: Registered udp transport module.
-[ 3.133081] RPC: Registered tcp transport module.
-[ 3.133089] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.133102] PCI: CLS 0 bytes, default 64
-[ 3.133312] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.133481] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.135738] fuse init (API version 7.23)
-[ 3.135850] msgmni has been set to 469
-[ 3.139064] io scheduler noop registered
-[ 3.139133] io scheduler cfq registered (default)
-[ 3.139792] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.139806] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.139818] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.139830] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.139841] pci_bus 0000:00: scanning bus
-[ 3.139853] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.139868] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.139883] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.139931] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.139944] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.139955] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.139966] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.139978] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.139989] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.140001] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.140044] pci_bus 0000:00: fixups for bus
-[ 3.140052] pci_bus 0000:00: bus scan returning with max=00
-[ 3.140066] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.140089] pci 0000:00:00.0: fixup irq: got 33
-[ 3.140098] pci 0000:00:00.0: assigning IRQ 33
-[ 3.140110] pci 0000:00:01.0: fixup irq: got 34
-[ 3.140119] pci 0000:00:01.0: assigning IRQ 34
-[ 3.140132] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.140146] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.140159] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.140173] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.140185] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.140197] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.140209] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.140221] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.140886] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.141268] ata_piix 0000:00:01.0: version 2.13
-[ 3.141280] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.141313] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.141940] scsi0 : ata_piix
-[ 3.142073] scsi1 : ata_piix
-[ 3.142110] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.142123] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.142257] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.142269] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.142286] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.142298] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301286] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301296] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301328] ata1.00: configured for UDMA/33
-[ 3.301395] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301536] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.301567] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.301615] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.301625] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.301650] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.301813] sda: sda1
-[ 3.301968] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421575] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.421589] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.421613] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.421623] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.421648] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.421660] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.421747] usbcore: registered new interface driver usb-storage
-[ 3.421815] mousedev: PS/2 mouse device common for all mice
-[ 3.422009] usbcore: registered new interface driver usbhid
-[ 3.422020] usbhid: USB HID core driver
-[ 3.422060] TCP: cubic registered
-[ 3.422068] NET: Registered protocol family 17
- -[ 3.422570] devtmpfs: mounted
-[ 3.422641] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 3.130956] usbcore: registered new interface driver usbfs
+[ 3.130977] usbcore: registered new interface driver hub
+[ 3.131019] usbcore: registered new device driver usb
+[ 3.131051] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131061] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131081] PTP clock support registered
+[ 3.131243] Switched to clocksource arch_sys_counter
+[ 3.132709] NET: Registered protocol family 2
+[ 3.132818] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.132843] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.132874] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.132892] TCP: reno registered
+[ 3.132900] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132916] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132971] NET: Registered protocol family 1
+[ 3.133024] RPC: Registered named UNIX socket transport module.
+[ 3.133035] RPC: Registered udp transport module.
+[ 3.133043] RPC: Registered tcp transport module.
+[ 3.133051] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.133064] PCI: CLS 0 bytes, default 64
+[ 3.133270] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.133439] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.135679] fuse init (API version 7.23)
+[ 3.135790] msgmni has been set to 469
+[ 3.138999] io scheduler noop registered
+[ 3.139069] io scheduler cfq registered (default)
+[ 3.139634] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.139648] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.139659] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.139672] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.139682] pci_bus 0000:00: scanning bus
+[ 3.139694] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.139709] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.139724] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139771] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.139784] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.139795] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.139806] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.139818] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.139829] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.139841] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139883] pci_bus 0000:00: fixups for bus
+[ 3.139892] pci_bus 0000:00: bus scan returning with max=00
+[ 3.139905] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.139929] pci 0000:00:00.0: fixup irq: got 33
+[ 3.139938] pci 0000:00:00.0: assigning IRQ 33
+[ 3.139949] pci 0000:00:01.0: fixup irq: got 34
+[ 3.139958] pci 0000:00:01.0: assigning IRQ 34
+[ 3.139971] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.139985] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.139998] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.140011] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.140023] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.140035] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.140047] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.140059] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.140718] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.141064] ata_piix 0000:00:01.0: version 2.13
+[ 3.141076] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.141104] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.141758] scsi0 : ata_piix
+[ 3.141889] scsi1 : ata_piix
+[ 3.141926] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.141938] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.142070] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.142082] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.142099] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.142111] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301279] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301289] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301320] ata1.00: configured for UDMA/33
+[ 3.301387] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.301528] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.301559] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.301607] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.301617] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.301642] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.301803] sda: sda1
+[ 3.301959] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.421568] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.421582] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.421605] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.421616] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.421640] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.421652] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.421739] usbcore: registered new interface driver usb-storage
+[ 3.421808] mousedev: PS/2 mouse device common for all mice
+[ 3.422005] usbcore: registered new interface driver usbhid
+[ 3.422015] usbhid: USB HID core driver
+[ 3.422054] TCP: cubic registered
+[ 3.422062] NET: Registered protocol family 17
+ +[ 3.422556] devtmpfs: mounted
+[ 3.422604] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.464661] udevd[607]: starting version 182
+[ 3.464675] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.594831] random: dd urandom read with 20 bits of entropy available
+[ 3.594846] random: dd urandom read with 20 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.761486] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.761479] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini index c5d0f1c68..094c3d2fb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -121,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -159,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -198,8 +216,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu.checker] type=O3Checker @@ -207,6 +232,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -225,6 +251,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -255,9 +285,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker [system.cpu.checker.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.dtb] @@ -271,9 +306,14 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[5] @@ -327,9 +367,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker [system.cpu.checker.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.itb] @@ -343,9 +388,14 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[4] @@ -360,13 +410,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -385,8 +439,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -409,9 +468,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -425,9 +489,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -703,13 +772,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -728,8 +801,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -787,9 +865,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -803,9 +886,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -816,13 +904,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -841,8 +933,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -850,9 +947,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -897,9 +1000,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -913,13 +1021,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -938,8 +1050,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -947,9 +1064,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -963,11 +1086,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1012,6 +1140,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1023,7 +1152,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1066,10 +1199,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1150,14 +1288,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1166,13 +1309,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1182,6 +1330,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1252,10 +1401,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1335,17 +1489,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1371,12 +1530,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1384,14 +1549,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1477,14 +1647,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1493,13 +1668,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1508,13 +1688,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1522,11 +1707,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1540,11 +1730,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1558,19 +1753,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1616,14 +1817,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1632,11 +1848,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1646,21 +1867,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1670,12 +1901,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1684,10 +1920,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1697,12 +1938,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1712,26 +1958,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1740,10 +1996,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1751,10 +2012,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1762,21 +2028,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1790,11 +2066,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1805,11 +2086,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1817,10 +2103,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr index 96daf2d1b..c04cf2403 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr @@ -3,101 +3,90 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 12469689449500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0 -warn: 12469692907500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0 +warn: 12465253480500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0 +warn: 12465256875500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 13859656146500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13859950489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13860549714500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13861141715500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13861425606000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13887655302500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13887984972000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13888175197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13888527468000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13926855654000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13927074222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13927622636000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13927831908000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13928069949000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13928309196000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13944831907000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13960769373500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 14182895786500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14182896036500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14182896282500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14191041595500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14198847599000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14198848114500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14198848578500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14206625430000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14206625664000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14206625894000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14211939480000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14211939710000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14218406091500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14218406321500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14228222612500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14228222857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14228223366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14228223600500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14228223830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14228224037000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14239432062500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14239432572000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14239432806000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14239433036000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14239433242500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14249200202500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14249200432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14264670876000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14264671403500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14264671637500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14264671867500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14264672074000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14269733190000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14276719950000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14276720459500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14276720693500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14276720923500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14276721130000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14286856693000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14349944433000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14349944681500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14349944897000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14407864195500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14407864763000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14407865015500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14407865264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14407865479500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14533528504500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14533619061000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14533620387500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14533622455000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14533622773500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534367031000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534367292000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 -warn: 14534367496500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534438304500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14534438514500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534438785500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14534439356000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534439611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14534439835000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534440124000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534440633000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534441696000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534442194000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14534442496000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14583340343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 14583519554000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 -warn: 14583519838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14583520090000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14583520334500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14583520596500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14583520826000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 13848743916500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13856080320500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13856660917500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13856932644000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13891365050500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13914492463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13915494038500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13915724569500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13929415957500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13975739128500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14218303751000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14218304352000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14218304616500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14218304863000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14218305076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14234303193500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14242116775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14242117552500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14242117792000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14242117998500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14247408751000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14247409260500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14247409494500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14247409734000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14247409931000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14253842696500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14253843672000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14253843878500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14263637803000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14263638037500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14263638268000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14263638474500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14274868668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14274868899000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14274869105500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14284684734000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14284685479000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14284685709500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14300304682500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14300304916500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14300305146500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14305416988000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14305417218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14305417424500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14312475874500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14312476114000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14322624432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14322624672000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14337182893000: Instruction results do not match! (Values may not actually be integers) Inst: 0x48, checker: 0x49 +warn: 14386098021000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14444180838500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14444181087000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14568925614000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569017181500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569017437000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14569020030500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569020349000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569750354000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569750626000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 +warn: 14569750836000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569821557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14569821767500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569822044000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 +warn: 14569822614500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569822870000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14569823093500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569823382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569823891500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569824954500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569825452500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14569825754500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14618889380500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 14618889688000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14618889945500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14618890194000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14618890463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14618890702500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout index f9ab0d84b..0a3ce6a26 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 14:35:47 -gem5 executing on e104799-lin, pid 16996 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:39:11 +gem5 executing on e108600-lin, pid 23099 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-checker Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51291805611000 because m5_exit instruction encountered +Exiting @ tick 51327142820000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index fb27e7fcb..eb2eff4bd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.327140 # Number of seconds simulated -sim_ticks 51327139864000 # Number of ticks simulated -final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.327143 # Number of seconds simulated +sim_ticks 51327142820000 # Number of ticks simulated +final_tick 51327142820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87448 # Simulator instruction rate (inst/s) -host_op_rate 102753 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5291966495 # Simulator tick rate (ticks/s) -host_mem_usage 687348 # Number of bytes of host memory used -host_seconds 9699.07 # Real time elapsed on the host -sim_insts 848164321 # Number of instructions simulated -sim_ops 996610207 # Number of ops (including micro ops) simulated +host_inst_rate 112988 # Simulator instruction rate (inst/s) +host_op_rate 132763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6836989613 # Simulator tick rate (ticks/s) +host_mem_usage 681568 # Number of bytes of host memory used +host_seconds 7507.27 # Real time elapsed on the host +sim_insts 848230502 # Number of instructions simulated +sim_ops 996685945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory -system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68386496 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 212864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5673056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 41642312 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory +system.physmem.bytes_read::total 48200872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5673056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5673056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68445056 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68407076 # Number of bytes written to this memory +system.physmem.bytes_written::total 68465636 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3383 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 649748 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6922 # Number of read requests responded to by this memory -system.physmem.num_reads::total 768028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1068539 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 650674 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory +system.physmem.num_reads::total 769104 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1069454 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1071112 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1072027 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 810157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 937750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1332365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 110527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 939091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1333506 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1332766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1332365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 1333907 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1333506 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 810558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2270516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 768028 # Number of read requests accepted -system.physmem.writeReqs 1071112 # Number of write requests accepted -system.physmem.readBursts 768028 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1071112 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49106944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 46848 # Total number of bytes read from write queue -system.physmem.bytesWritten 68406272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48132008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68407076 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 732 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.itb.walker 4147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2272998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 769104 # Number of read requests accepted +system.physmem.writeReqs 1072027 # Number of write requests accepted +system.physmem.readBursts 769104 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1072027 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49176064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 46592 # Total number of bytes read from write queue +system.physmem.bytesWritten 68464384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48200872 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68465636 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 728 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 45073 # Per bank write bursts -system.physmem.perBankRdBursts::1 51507 # Per bank write bursts -system.physmem.perBankRdBursts::2 47331 # Per bank write bursts -system.physmem.perBankRdBursts::3 43047 # Per bank write bursts -system.physmem.perBankRdBursts::4 45469 # Per bank write bursts -system.physmem.perBankRdBursts::5 51901 # Per bank write bursts -system.physmem.perBankRdBursts::6 46387 # Per bank write bursts -system.physmem.perBankRdBursts::7 47163 # Per bank write bursts -system.physmem.perBankRdBursts::8 43832 # Per bank write bursts -system.physmem.perBankRdBursts::9 71407 # Per bank write bursts -system.physmem.perBankRdBursts::10 44269 # Per bank write bursts -system.physmem.perBankRdBursts::11 52269 # Per bank write bursts -system.physmem.perBankRdBursts::12 42900 # Per bank write bursts -system.physmem.perBankRdBursts::13 46591 # Per bank write bursts -system.physmem.perBankRdBursts::14 43222 # Per bank write bursts -system.physmem.perBankRdBursts::15 44928 # Per bank write bursts -system.physmem.perBankWrBursts::0 64149 # Per bank write bursts -system.physmem.perBankWrBursts::1 68917 # Per bank write bursts -system.physmem.perBankWrBursts::2 66979 # Per bank write bursts -system.physmem.perBankWrBursts::3 64863 # Per bank write bursts -system.physmem.perBankWrBursts::4 67442 # Per bank write bursts -system.physmem.perBankWrBursts::5 70404 # Per bank write bursts -system.physmem.perBankWrBursts::6 66306 # Per bank write bursts -system.physmem.perBankWrBursts::7 67867 # Per bank write bursts -system.physmem.perBankWrBursts::8 65614 # Per bank write bursts -system.physmem.perBankWrBursts::9 70732 # Per bank write bursts -system.physmem.perBankWrBursts::10 65165 # Per bank write bursts -system.physmem.perBankWrBursts::11 71475 # Per bank write bursts -system.physmem.perBankWrBursts::12 63578 # Per bank write bursts -system.physmem.perBankWrBursts::13 66114 # Per bank write bursts -system.physmem.perBankWrBursts::14 64356 # Per bank write bursts -system.physmem.perBankWrBursts::15 64887 # Per bank write bursts +system.physmem.perBankRdBursts::0 44564 # Per bank write bursts +system.physmem.perBankRdBursts::1 52315 # Per bank write bursts +system.physmem.perBankRdBursts::2 47721 # Per bank write bursts +system.physmem.perBankRdBursts::3 44538 # Per bank write bursts +system.physmem.perBankRdBursts::4 44659 # Per bank write bursts +system.physmem.perBankRdBursts::5 50872 # Per bank write bursts +system.physmem.perBankRdBursts::6 46439 # Per bank write bursts +system.physmem.perBankRdBursts::7 47959 # Per bank write bursts +system.physmem.perBankRdBursts::8 44018 # Per bank write bursts +system.physmem.perBankRdBursts::9 71274 # Per bank write bursts +system.physmem.perBankRdBursts::10 43972 # Per bank write bursts +system.physmem.perBankRdBursts::11 51692 # Per bank write bursts +system.physmem.perBankRdBursts::12 45026 # Per bank write bursts +system.physmem.perBankRdBursts::13 46672 # Per bank write bursts +system.physmem.perBankRdBursts::14 42515 # Per bank write bursts +system.physmem.perBankRdBursts::15 44140 # Per bank write bursts +system.physmem.perBankWrBursts::0 64758 # Per bank write bursts +system.physmem.perBankWrBursts::1 69412 # Per bank write bursts +system.physmem.perBankWrBursts::2 67623 # Per bank write bursts +system.physmem.perBankWrBursts::3 66442 # Per bank write bursts +system.physmem.perBankWrBursts::4 66817 # Per bank write bursts +system.physmem.perBankWrBursts::5 69740 # Per bank write bursts +system.physmem.perBankWrBursts::6 65132 # Per bank write bursts +system.physmem.perBankWrBursts::7 69008 # Per bank write bursts +system.physmem.perBankWrBursts::8 65482 # Per bank write bursts +system.physmem.perBankWrBursts::9 70623 # Per bank write bursts +system.physmem.perBankWrBursts::10 64235 # Per bank write bursts +system.physmem.perBankWrBursts::11 70444 # Per bank write bursts +system.physmem.perBankWrBursts::12 64965 # Per bank write bursts +system.physmem.perBankWrBursts::13 66804 # Per bank write bursts +system.physmem.perBankWrBursts::14 64273 # Per bank write bursts +system.physmem.perBankWrBursts::15 63998 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51327138450500 # Total gap between requests +system.physmem.numWrRetry 34 # Number of times write queue was full causing retry +system.physmem.totGap 51327141408500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 746743 # Read request sizes (log2) +system.physmem.readPktSize::6 747819 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1068539 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 514973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 144 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1069454 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 515353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 203905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,126 +160,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 58973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 471440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.263737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.464196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.749786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207824 44.08% 44.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 122155 25.91% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42779 9.07% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22709 4.82% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14933 3.17% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9495 2.01% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7568 1.61% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6030 1.28% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37947 8.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 471440 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54191 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.158790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 76.596487 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 54185 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 26806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 65026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 74 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 471870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.306089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.569568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.567780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207742 44.03% 44.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122462 25.95% 69.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 42886 9.09% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22733 4.82% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14982 3.18% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9606 2.04% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7566 1.60% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6003 1.27% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37890 8.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 471870 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 54238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.166341 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 76.651597 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 54233 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54191 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54191 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.723718 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.774638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.948432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40576 74.88% 74.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4593 8.48% 83.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5177 9.55% 92.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1373 2.53% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 420 0.78% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 248 0.46% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 301 0.56% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 130 0.24% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 393 0.73% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 142 0.26% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 38 0.07% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 61 0.11% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 323 0.60% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 40 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.20% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 181 0.33% 99.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 54238 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 54238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.723367 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.775784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.950161 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 40620 74.89% 74.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4585 8.45% 83.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5200 9.59% 92.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1381 2.55% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 413 0.76% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 235 0.43% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 311 0.57% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 127 0.23% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 390 0.72% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 50 0.09% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 65 0.12% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 327 0.60% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 29 0.05% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.20% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 166 0.31% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54191 # Writes before turning the bus around for reads -system.physmem.totQLat 15195806089 # Total ticks spent queuing -system.physmem.totMemAccLat 29582606089 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3836480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19804.36 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 54238 # Writes before turning the bus around for reads +system.physmem.totQLat 15209667379 # Total ticks spent queuing +system.physmem.totMemAccLat 29616717379 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3841880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19794.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38554.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38544.56 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s @@ -288,43 +288,43 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 579763 # Number of row buffer hits during reads -system.physmem.writeRowHits 784939 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing +system.physmem.readRowHits 580662 # Number of row buffer hits during reads +system.physmem.writeRowHits 785598 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes -system.physmem.avgGap 27908228.00 # Average gap between requests -system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1800088920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 982191375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2947417200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3479286960 # Energy for write commands per rank (pJ) +system.physmem.avgGap 27878049.64 # Average gap between requests +system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1803657240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 984138375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2956722600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3492279360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235810088180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29712239669250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309697958765 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.451396 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49428932348966 # Time in different power states +system.physmem_0.actBackEnergy 1235640856320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29712388110000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34309704980775 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.451533 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49429181288166 # Time in different power states system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184281028534 # Time in different power states +system.physmem_0.memoryStateTime::ACT 184032075584 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1763997480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 962498625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3037452600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3446848080 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 1763679960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 962325375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3036563400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3439739520 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235330422065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.450284 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states +system.physmem_1.actBackEnergy 1235034526230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712919978500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34309596029865 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.449411 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49430060847495 # Time in different power states system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states +system.physmem_1.memoryStateTime::ACT 183155359005 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -341,30 +341,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225024609 # Number of BP lookups -system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12305268 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158924221 # Number of BTB lookups -system.cpu.branchPred.BTBHits 98148969 # Number of BTB hits +system.cpu.branchPred.lookups 225047911 # Number of BP lookups +system.cpu.branchPred.condPredicted 149825196 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12305756 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158986930 # Number of BTB lookups +system.cpu.branchPred.BTBHits 98148773 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 61.733863 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30878370 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 343644 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6734089 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4745857 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1988232 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 765703 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,47 +394,47 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 197728 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 197728 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 197728 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 197728 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 197728 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.walks 197474 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 197474 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 197474 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 197474 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 197474 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 154026 91.54% 91.54% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 14228 8.46% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 168254 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197728 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 153977 91.65% 91.65% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 14023 8.35% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 168000 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197474 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197728 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168254 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197474 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168000 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168254 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 365982 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168000 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 365474 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 159555012 # DTB read hits -system.cpu.checker.dtb.read_misses 147105 # DTB read misses -system.cpu.checker.dtb.write_hits 144753445 # DTB write hits -system.cpu.checker.dtb.write_misses 50623 # DTB write misses +system.cpu.checker.dtb.read_hits 159568162 # DTB read hits +system.cpu.checker.dtb.read_misses 146947 # DTB read misses +system.cpu.checker.dtb.write_hits 144766301 # DTB write hits +system.cpu.checker.dtb.write_misses 50527 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 71724 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 71659 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 6683 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 6990 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 19053 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 159702117 # DTB read accesses -system.cpu.checker.dtb.write_accesses 144804068 # DTB write accesses +system.cpu.checker.dtb.read_accesses 159715109 # DTB read accesses +system.cpu.checker.dtb.write_accesses 144816828 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 304308457 # DTB hits -system.cpu.checker.dtb.misses 197728 # DTB misses -system.cpu.checker.dtb.accesses 304506185 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.hits 304334463 # DTB hits +system.cpu.checker.dtb.misses 197474 # DTB misses +system.cpu.checker.dtb.accesses 304531937 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,27 +464,27 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 119805 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 119805 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 119805 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 119805 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 119805 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.walks 119817 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 119817 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 119817 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 119817 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 119817 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 107946 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::4K 107958 98.83% 98.83% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109226 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109238 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119805 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119805 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119817 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119817 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109226 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109226 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 229031 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 848570685 # ITB inst hits -system.cpu.checker.itb.inst_misses 119805 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109238 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109238 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 229055 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 848636866 # ITB inst hits +system.cpu.checker.itb.inst_misses 119817 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits @@ -493,22 +493,22 @@ system.cpu.checker.itb.flush_tlb 20 # Nu system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 51649 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 51647 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 848690490 # ITB inst accesses -system.cpu.checker.itb.hits 848570685 # DTB hits -system.cpu.checker.itb.misses 119805 # DTB misses -system.cpu.checker.itb.accesses 848690490 # DTB accesses -system.cpu.checker.pwrStateResidencyTicks::ON 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 997179501 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 848756683 # ITB inst accesses +system.cpu.checker.itb.hits 848636866 # DTB hits +system.cpu.checker.itb.misses 119817 # DTB misses +system.cpu.checker.itb.accesses 848756683 # DTB accesses +system.cpu.checker.pwrStateResidencyTicks::ON 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.checker.numCycles 997255251 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -538,89 +538,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 947007 # Table walker walks requested -system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 508020 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 2030 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1046 0.20% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 222 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 147 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 54 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 511600 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 486864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 475438 97.65% 97.65% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7837 1.61% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2530 0.52% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 265 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 545 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 113 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 104 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 16 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 486864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 779668807876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725507 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.522451 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 777433889876 99.71% 99.71% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1160253500 0.15% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 513477500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 201866500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 152233500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 119773500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 32296000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52448000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2569500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 779668807876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155483 90.77% 90.77% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15816 9.23% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171299 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 947007 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 948773 # Table walker walks requested +system.cpu.dtb.walker.walksLong 948773 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15596 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155468 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 437937 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 510836 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2285.186439 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 507265 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 2025 0.40% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1066 0.21% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 145 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 43 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 510836 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 488329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 476828 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7891 1.62% 99.26% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2533 0.52% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 229 0.05% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 568 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 114 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 488329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 779668986876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.725199 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.523523 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 777411937376 99.71% 99.71% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1169683000 0.15% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 513347500 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 208116000 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 157188000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121226500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 32342000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 52541000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2605500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 779668986876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155469 90.88% 90.88% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15596 9.12% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 171065 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 948773 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 947007 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171299 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 948773 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171065 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171299 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1118306 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171065 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1119838 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169398877 # DTB read hits -system.cpu.dtb.read_misses 674798 # DTB read misses -system.cpu.dtb.write_hits 147332912 # DTB write hits -system.cpu.dtb.write_misses 272209 # DTB write misses +system.cpu.dtb.read_hits 169411407 # DTB read hits +system.cpu.dtb.read_misses 675369 # DTB read misses +system.cpu.dtb.write_hits 147344334 # DTB write hits +system.cpu.dtb.write_misses 273404 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 71963 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10047 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170073675 # DTB read accesses -system.cpu.dtb.write_accesses 147605121 # DTB write accesses +system.cpu.dtb.perms_faults 69388 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170086776 # DTB read accesses +system.cpu.dtb.write_accesses 147617738 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316731789 # DTB hits -system.cpu.dtb.misses 947007 # DTB misses -system.cpu.dtb.accesses 317678796 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 316755741 # DTB hits +system.cpu.dtb.misses 948773 # DTB misses +system.cpu.dtb.accesses 317704514 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -650,66 +648,66 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 162102 # Table walker walks requested -system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143046 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 588 0.41% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 94 0.07% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 159 0.11% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 224 0.16% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 44 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144186 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139421 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28788.855337 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136254 97.73% 97.73% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 690 0.49% 98.22% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2101 1.51% 99.73% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 136 0.10% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 47 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 162181 # Table walker walks requested +system.cpu.itb.walker.walksLong 162181 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1496 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 120027 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17971 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144210 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1137.740101 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9342.723838 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143038 99.19% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 619 0.43% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 86 0.06% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 189 0.13% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 221 0.15% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 35 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144210 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 139494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29066.088864 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 136396 97.78% 97.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 707 0.51% 98.29% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1985 1.42% 99.71% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 151 0.11% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 171 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 34 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139421 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 680881393568 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.947864 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.222600 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 35543211356 5.22% 5.22% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 645294358712 94.77% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 43207500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 580000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 36000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 680881393568 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120022 98.78% 98.78% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1483 1.22% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 121505 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 139494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 676589720772 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.947980 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.222341 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 35236838356 5.21% 5.21% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 641313182416 94.79% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 39010000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 686000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 676589720772 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 120027 98.77% 98.77% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1496 1.23% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 121523 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162102 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162102 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162181 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 162181 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121505 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 121505 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283607 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357007788 # ITB inst hits -system.cpu.itb.inst_misses 162102 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121523 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 121523 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 283704 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 357038073 # ITB inst hits +system.cpu.itb.inst_misses 162181 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -718,21 +716,21 @@ system.cpu.itb.flush_tlb 20 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52848 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 357344 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357169890 # ITB inst accesses -system.cpu.itb.hits 357007788 # DTB hits -system.cpu.itb.misses 162102 # DTB misses -system.cpu.itb.accesses 357169890 # DTB accesses +system.cpu.itb.inst_accesses 357200254 # ITB inst accesses +system.cpu.itb.hits 357038073 # DTB hits +system.cpu.itb.misses 162181 # DTB misses +system.cpu.itb.accesses 357200254 # DTB accesses system.cpu.numPwrStateTransitions 32228 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3134631677.512784 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60494120707.852806 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state @@ -744,139 +742,139 @@ system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1631144067 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 815687968559 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1631385344 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646877625 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1002761410 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225047911 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133773000 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 898188451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26266186 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3841497 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30548 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8722394 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1026877 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1034 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 356664988 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6247416 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47904 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1571821519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.149310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1014113227 64.52% 64.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 214297646 13.63% 78.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70312417 4.47% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 273098229 17.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1571821519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137949 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.614669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526332322 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 552246914 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434136742 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49729183 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9376358 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33563941 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3814299 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1086052117 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29449193 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9376358 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571289803 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66024800 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 371545208 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 438989582 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 114595768 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1065754363 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6907795 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5097238 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 334375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 639506 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 63573833 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20465 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1013430764 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1640279788 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259572075 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1474026 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 947250209 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 66180552 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26901106 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23243208 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101784051 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173837388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150829276 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9883117 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9014861 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1030729252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27201158 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1045808358 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3377405 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 61244461 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 34071399 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 308913 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1571821519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.665348 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.919634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 924230442 58.80% 58.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 334342298 21.27% 80.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234750151 14.93% 95.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72048277 4.58% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6430828 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19523 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1571821519 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 667 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44277065 26.88% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62625013 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57691324 35.03% 35.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100152 0.06% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26730 0.02% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 622 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44285841 26.89% 62.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62576075 38.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 720295550 68.88% 68.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2531326 0.24% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122856 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 720343690 68.88% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2530628 0.24% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122776 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued @@ -899,100 +897,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 119220 0.01% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 119191 0.01% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173490543 16.59% 85.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149201098 14.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued -system.cpu.iq.rate 0.641106 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1045808358 # Type of FU issued +system.cpu.iq.rate 0.641055 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164680744 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157467 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3829023509 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118377930 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1027460456 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2472874 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 938610 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909796 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1208933693 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1555398 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4274316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14173969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14495 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 142953 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6059351 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2526453 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1440750 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9376358 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7004216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6913167 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1058165202 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22818732 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57696 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6782714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3464744 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5492402 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8957146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1034225316 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169386893 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10574140 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173837388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150829276 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22819114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57849 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6781828 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 142953 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3462734 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5495013 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8957747 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1034296660 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169399584 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10573772 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 235018 # number of nop insts executed -system.cpu.iew.exec_refs 316715121 # number of memory reference insts executed -system.cpu.iew.exec_branches 196182084 # Number of branches executed -system.cpu.iew.exec_stores 147328228 # Number of stores executed -system.cpu.iew.exec_rate 0.634049 # Inst execution rate -system.cpu.iew.wb_sent 1029119140 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back -system.cpu.iew.wb_producers 437817967 # num instructions producing a value -system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value -system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle +system.cpu.iew.exec_nop 234792 # number of nop insts executed +system.cpu.iew.exec_refs 316739180 # number of memory reference insts executed +system.cpu.iew.exec_branches 196198672 # Number of branches executed +system.cpu.iew.exec_stores 147339596 # Number of stores executed +system.cpu.iew.exec_rate 0.633999 # Inst execution rate +system.cpu.iew.wb_sent 1029187818 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1028370252 # cumulative count of insts written-back +system.cpu.iew.wb_producers 437853372 # num instructions producing a value +system.cpu.iew.wb_consumers 708400240 # num instructions consuming a value +system.cpu.iew.wb_rate 0.630366 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618088 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51884426 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26892245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8549021 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1559762540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.638999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273827 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1047991029 67.19% 67.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288035307 18.47% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120100080 7.70% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36659789 2.35% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28506606 1.83% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13942789 0.89% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8651847 0.55% 98.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4181084 0.27% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11694009 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle -system.cpu.commit.committedInsts 848164321 # Number of instructions committed -system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1559762540 # Number of insts commited each cycle +system.cpu.commit.committedInsts 848230502 # Number of instructions committed +system.cpu.commit.committedOps 996685945 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304407284 # Number of memory references committed -system.cpu.commit.loads 159650119 # Number of loads committed -system.cpu.commit.membars 6926917 # Number of memory barriers committed -system.cpu.commit.branches 189306416 # Number of branches committed -system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions. -system.cpu.commit.int_insts 915651510 # Number of committed integer instructions. -system.cpu.commit.function_calls 25281717 # Number of function calls committed. +system.cpu.commit.refs 304433343 # Number of memory references committed +system.cpu.commit.loads 159663418 # Number of loads committed +system.cpu.commit.membars 6927415 # Number of memory barriers committed +system.cpu.commit.branches 189324067 # Number of branches committed +system.cpu.commit.fp_insts 898712 # Number of committed floating point instructions. +system.cpu.commit.int_insts 915721971 # Number of committed integer instructions. +system.cpu.commit.function_calls 25285288 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 689843263 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2149527 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98159 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 689893101 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2149376 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98151 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -1019,541 +1017,540 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159663418 16.02% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144769925 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction -system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2588836134 # The number of ROB reads -system.cpu.rob.rob_writes 2108972650 # The number of ROB writes -system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 848164321 # Number of Instructions Simulated -system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.923146 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519981 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads -system.cpu.int_regfile_writes 731349876 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads -system.cpu.fp_regfile_writes 780384 # number of floating regfile writes -system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads -system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes -system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads -system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9706309 # number of replacements +system.cpu.commit.op_class_0::total 996685945 # Class of committed instruction +system.cpu.commit.bw_lim_events 11694009 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2589097882 # The number of ROB reads +system.cpu.rob.rob_writes 2109106528 # The number of ROB writes +system.cpu.timesIdled 8171713 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59563825 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101022900419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 848230502 # Number of Instructions Simulated +system.cpu.committedOps 996685945 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.923281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.923281 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519945 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519945 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1223820104 # number of integer regfile reads +system.cpu.int_regfile_writes 731394908 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462803 # number of floating regfile reads +system.cpu.fp_regfile_writes 780644 # number of floating regfile writes +system.cpu.cc_regfile_reads 225050166 # number of cc regfile reads +system.cpu.cc_regfile_writes 225684828 # number of cc regfile writes +system.cpu.misc_regfile_reads 2558325337 # number of misc regfile reads +system.cpu.misc_regfile_writes 26931155 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9701158 # number of replacements system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 283187639 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9701670 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.189577 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128244124 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits -system.cpu.dcache.overall_hits::total 276127624 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11252664 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1170750 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1170750 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1233990 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1233990 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses -system.cpu.dcache.overall_misses::total 23239410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 444283559827 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52343559973 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 52343559973 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 139496788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548503 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1548503 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080666 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756053 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.756053 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792311 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.792311 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1237018765 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1237018765 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 147199934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147199934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128255410 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128255410 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377663 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377663 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 323814 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 323814 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295431 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3295431 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3691256 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3691256 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 275779158 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 275779158 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 276156821 # number of overall hits +system.cpu.dcache.overall_hits::total 276156821 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9580915 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9580915 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11254027 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11254027 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1170464 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1170464 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1233639 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1233639 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 446709 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 446709 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 22068581 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 22068581 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 23239045 # number of overall misses +system.cpu.dcache.overall_misses::total 23239045 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 168767240000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 444298934810 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52375248289 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 52375248289 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6883962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6883962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 380500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 380500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 665441423099 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 665441423099 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 665441423099 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 665441423099 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156780849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156780849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 139509437 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 139509437 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548127 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1548127 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557453 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1557453 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3742140 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3742140 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691264 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3691264 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 297847739 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 297847739 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 299395866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 299395866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061110 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061110 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080669 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080669 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756052 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.756052 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792087 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.792087 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119373 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119373 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.074093 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074093 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.077620 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.077620 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30153.339859 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28634.628622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32224409 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1601607 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.120048 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks -system.cpu.dcache.writebacks::total 7511281 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4454269 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9249122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9249122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2003542 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163937 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1163937 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226860 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1226860 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7504086 # number of writebacks +system.cpu.dcache.writebacks::total 7504086 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4456599 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4456599 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9250788 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9250788 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7056 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7056 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219268 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 219268 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13714443 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13714443 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13714443 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13714443 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5124316 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5124316 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8354138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9517786 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9517786 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84965736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84965736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77538140437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77538140437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23685156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23685156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50670413473 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014363 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751653 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751653 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787733 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787733 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84959954500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84959954500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77558080846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77558080846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23723735000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23723735000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50708992789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50708992789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3202218000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3202218000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 372500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 372500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 213227028135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 236950763135 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192056000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192056000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192056000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192056000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032685 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032685 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751649 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751649 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787557 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787557 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060778 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060778 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 15141033 # number of replacements -system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028048 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028048 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 15134592 # number of replacements +system.cpu.icache.tags.tagsinuse 511.928988 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 340756209 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15135104 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.514296 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.928988 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340718799 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340718799 # number of overall hits -system.cpu.icache.overall_hits::total 340718799 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15894345 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15894345 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15894345 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15894345 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15894345 # number of overall misses -system.cpu.icache.overall_misses::total 15894345 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214960438379 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214960438379 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214960438379 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214960438379 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214960438379 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214960438379 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356613144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356613144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356613144 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356613144 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356613144 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356613144 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044570 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044570 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044570 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044570 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044570 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044570 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13524.334496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13524.334496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13524.334496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13524.334496 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 23721 # 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15887482 # number of overall misses +system.cpu.icache.overall_misses::total 15887482 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214918228873 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214918228873 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214918228873 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214918228873 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214918228873 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 356643691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 356643691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 356643691 # 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average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785050 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785050 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039465 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039465 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407265 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407265 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030044 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030044 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 50407203 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25570213 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1618708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23266675 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1963403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1963403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15141775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6525421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226860 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45466959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29342845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 722067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1919121 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77450992 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1938426848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023681310 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2369528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6237568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2970715254 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1868325 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27924144 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156198 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8573574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15134592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2391693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43548 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1963232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1963232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15135331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1333247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226583 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45447628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29327152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 726647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1928826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77430253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1937602080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1022907422 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2405600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6328296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2969243398 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1852603 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 72285944 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 27912596 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.024958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.155996 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27225372 97.50% 97.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 698772 2.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27215961 97.50% 97.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 696635 2.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27924144 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48365955497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27912596 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48339894491 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1497386 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1459384 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22733591738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13401353655 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 426266814 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1138134788 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40299 # Transaction distribution -system.iobus.trans_dist::ReadResp 40299 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40293 # Transaction distribution +system.iobus.trans_dist::ReadResp 40293 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1764,11 +1762,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1783,16 +1781,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41885000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41884500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 345000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1810,75 +1808,75 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25104500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25117000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36501000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567323274 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115453 # number of replacements +system.iocache.tags.tagsinuse 10.423128 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13098782503000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878927 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039605 # Number of tag accesses +system.iocache.tags.data_accesses 1039605 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses -system.iocache.demand_misses::total 115518 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115472 # number of demand (read+write) misses +system.iocache.demand_misses::total 115512 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115478 # number of overall misses -system.iocache.overall_misses::total 115518 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115472 # number of overall misses +system.iocache.overall_misses::total 115512 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5076000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1670063987 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1675139987 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13414774287 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13414774287 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5427000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15084838274 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15090265274 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5427000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15084838274 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15090265274 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115472 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115512 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115472 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115512 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1892,53 +1890,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189388.353533 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135675 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130638.074607 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135675 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130638.074607 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33964 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3510 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.676353 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115472 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115512 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115472 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115512 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3226000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229663987 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1232889987 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076516803 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8076516803 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3427000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9306180790 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9309607790 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3427000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9306180790 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9309607790 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1952,88 +1950,89 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 410008 # Transaction distribution +system.membus.trans_dist::ReadResp 411033 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution -system.membus.trans_dist::CleanEvict 192763 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1069454 # Transaction distribution +system.membus.trans_dist::CleanEvict 193565 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34895 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 394295 # Transaction distribution -system.membus.trans_dist::ReadExResp 394295 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 355036 # Transaction distribution -system.membus.trans_dist::InvalidateReq 605480 # Transaction distribution +system.membus.trans_dist::ReadExReq 394310 # Transaction distribution +system.membus.trans_dist::ReadExResp 394310 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 356061 # Transaction distribution +system.membus.trans_dist::InvalidateReq 606112 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3207653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3337273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3575172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3212019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3341639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237917 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237917 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3579556 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109271756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109441726 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7267328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7267328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 116709054 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2596 # Total snoops (count) -system.membus.snoop_fanout::samples 2739791 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109397260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109567230 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7269248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7269248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116836478 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2560 # Total snoops (count) +system.membus.snoopTraffic 163328 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2743103 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2739791 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2743103 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2739791 # Request fanout histogram -system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2743103 # Request fanout histogram +system.membus.reqLayer0.occupancy 103939500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5573000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7172212711 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4075256665 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44789891 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2076,29 +2075,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal index 1b50f034a..3c0eb417b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal @@ -31,136 +31,136 @@ [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000022] Console: colour dummy device 80x25
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000021] Console: colour dummy device 80x25
[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000025] pid_max: default: 32768 minimum: 301
[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000160] hw perfevents: no hardware support available
-[ 1.060067] CPU1: failed to come online
-[ 2.080129] CPU2: failed to come online
-[ 3.100191] CPU3: failed to come online
-[ 3.100194] Brought up 1 CPUs
-[ 3.100195] SMP: Total of 1 processors activated.
-[ 3.100251] devtmpfs: initialized
-[ 3.100700] atomic64_test: passed
-[ 3.100743] regulator-dummy: no parameters
-[ 3.101166] NET: Registered protocol family 16
-[ 3.101292] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101301] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.102003] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.102008] Serial: AMBA PL011 UART driver
-[ 3.102194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.102227] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102794] console [ttyAMA0] enabled
-[ 3.102873] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102904] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.102936] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.102965] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130500] 3V3: 3300 mV
-[ 3.130542] vgaarb: loaded
-[ 3.130589] SCSI subsystem initialized
-[ 3.130626] libata version 3.00 loaded.
-[ 3.130670] usbcore: registered new interface driver usbfs
-[ 3.130688] usbcore: registered new interface driver hub
-[ 3.130719] usbcore: registered new device driver usb
-[ 3.130744] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130753] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130772] PTP clock support registered
-[ 3.130888] Switched to clocksource arch_sys_counter
-[ 3.131885] NET: Registered protocol family 2
-[ 3.131959] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131977] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131999] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.132014] TCP: reno registered
-[ 3.132021] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132036] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132076] NET: Registered protocol family 1
-[ 3.132127] RPC: Registered named UNIX socket transport module.
-[ 3.132137] RPC: Registered udp transport module.
-[ 3.132145] RPC: Registered tcp transport module.
-[ 3.132153] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132165] PCI: CLS 0 bytes, default 64
-[ 3.132312] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.132411] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.133969] fuse init (API version 7.23)
-[ 3.134047] msgmni has been set to 469
-[ 3.136178] io scheduler noop registered
-[ 3.136228] io scheduler cfq registered (default)
-[ 3.136665] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.136678] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.136689] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.136702] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.136712] pci_bus 0000:00: scanning bus
-[ 3.136722] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.136735] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.136749] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136786] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.136798] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.136809] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.136819] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.136830] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.136841] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136885] pci_bus 0000:00: fixups for bus
-[ 3.136893] pci_bus 0000:00: bus scan returning with max=00
-[ 3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.136925] pci 0000:00:00.0: fixup irq: got 33
-[ 3.136933] pci 0000:00:00.0: assigning IRQ 33
-[ 3.136944] pci 0000:00:01.0: fixup irq: got 34
-[ 3.136952] pci 0000:00:01.0: assigning IRQ 34
-[ 3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.137002] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.137014] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.137025] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.137036] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.137048] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.137735] ata_piix 0000:00:01.0: version 2.13
-[ 3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.137770] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.138035] scsi0 : ata_piix
-[ 3.138128] scsi1 : ata_piix
-[ 3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.138306] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290924] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290951] ata1.00: configured for UDMA/33
-[ 3.291001] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.291104] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.291128] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.291165] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.291174] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.291193] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291307] sda: sda1
-[ 3.291413] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.411182] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.411195] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.411215] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.411225] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411245] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411257] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411320] usbcore: registered new interface driver usb-storage
-[ 3.411372] mousedev: PS/2 mouse device common for all mice
-[ 3.411510] usbcore: registered new interface driver usbhid
-[ 3.411519] usbhid: USB HID core driver
-[ 3.411550] TCP: cubic registered
-[ 3.411558] NET: Registered protocol family 17
- -[ 3.411924] devtmpfs: mounted
-[ 3.411972] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000147] hw perfevents: no hardware support available
+[ 1.060066] CPU1: failed to come online
+[ 2.080127] CPU2: failed to come online
+[ 3.100188] CPU3: failed to come online
+[ 3.100191] Brought up 1 CPUs
+[ 3.100192] SMP: Total of 1 processors activated.
+[ 3.100247] devtmpfs: initialized
+[ 3.100685] atomic64_test: passed
+[ 3.100727] regulator-dummy: no parameters
+[ 3.101141] NET: Registered protocol family 16
+[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.101638] Serial: AMBA PL011 UART driver
+[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102416] console [ttyAMA0] enabled
+[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130494] 3V3: 3300 mV
+[ 3.130534] vgaarb: loaded
+[ 3.130580] SCSI subsystem initialized
+[ 3.130617] libata version 3.00 loaded.
+[ 3.130659] usbcore: registered new interface driver usbfs
+[ 3.130676] usbcore: registered new interface driver hub
+[ 3.130707] usbcore: registered new device driver usb
+[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130759] PTP clock support registered
+[ 3.130873] Switched to clocksource arch_sys_counter
+[ 3.131846] NET: Registered protocol family 2
+[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131975] TCP: reno registered
+[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132036] NET: Registered protocol family 1
+[ 3.132085] RPC: Registered named UNIX socket transport module.
+[ 3.132095] RPC: Registered udp transport module.
+[ 3.132103] RPC: Registered tcp transport module.
+[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132123] PCI: CLS 0 bytes, default 64
+[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.133901] fuse init (API version 7.23)
+[ 3.133978] msgmni has been set to 469
+[ 3.136097] io scheduler noop registered
+[ 3.136147] io scheduler cfq registered (default)
+[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.136562] pci_bus 0000:00: scanning bus
+[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136734] pci_bus 0000:00: fixups for bus
+[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
+[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
+[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
+[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
+[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
+[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.137572] ata_piix 0000:00:01.0: version 2.13
+[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.137866] scsi0 : ata_piix
+[ 3.137956] scsi1 : ata_piix
+[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290935] ata1.00: configured for UDMA/33
+[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.291287] sda: sda1
+[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.411304] usbcore: registered new interface driver usb-storage
+[ 3.411354] mousedev: PS/2 mouse device common for all mice
+[ 3.411491] usbcore: registered new interface driver usbhid
+[ 3.411501] usbhid: USB HID core driver
+[ 3.411531] TCP: cubic registered
+[ 3.411538] NET: Registered protocol family 17
+ +[ 3.411900] devtmpfs: mounted
+[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.450398] udevd[607]: starting version 182
+[ 3.450359] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.533417] random: dd urandom read with 19 bits of entropy available
+[ 3.543431] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
-Configuring network interfaces... [ 3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
udhcpc (v1.21.1) started
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini index 11768aa62..5e79cd0cc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -121,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -159,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -198,8 +216,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu0.dcache] type=Cache @@ -208,13 +233,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -233,8 +262,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -257,9 +291,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -273,9 +312,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -551,13 +595,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -576,8 +624,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -635,9 +688,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -651,9 +709,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -664,13 +727,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -688,6 +755,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -698,6 +766,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -714,8 +786,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -723,9 +800,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -770,6 +853,7 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -808,6 +892,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -847,8 +935,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu1.dcache] type=Cache @@ -857,13 +952,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -882,8 +981,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -906,9 +1010,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -922,9 +1031,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -1200,13 +1314,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -1225,8 +1343,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1284,9 +1407,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1300,9 +1428,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -1313,13 +1446,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -1337,6 +1474,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -1347,6 +1485,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -1363,8 +1505,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -1372,9 +1519,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1419,9 +1572,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1435,13 +1593,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1460,8 +1622,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1472,13 +1639,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1497,20 +1668,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1522,11 +1704,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1537,6 +1724,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -1571,6 +1765,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1582,7 +1777,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1625,10 +1824,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1709,14 +1913,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1725,13 +1934,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1741,6 +1955,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1811,10 +2026,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1894,17 +2114,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1930,12 +2155,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1943,14 +2174,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2036,14 +2272,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2052,13 +2293,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2067,13 +2313,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2081,11 +2332,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2099,11 +2355,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2117,19 +2378,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -2175,14 +2442,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2191,11 +2473,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2205,21 +2492,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2229,12 +2526,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2243,10 +2545,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2256,12 +2563,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2271,26 +2583,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2299,10 +2621,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2310,10 +2637,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2321,21 +2653,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2349,11 +2691,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2364,11 +2711,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2376,10 +2728,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2395,9 +2752,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr index 4c70e8d66..ab526e302 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr @@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist @@ -11,3 +13,4 @@ warn: allocating bonus target for snoop warn: allocating bonus target for snoop warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: allocating bonus target for snoop diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout index cc1e1c387..83022ad25 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 13:59:02 -gem5 executing on e104799-lin, pid 13304 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:49:48 +gem5 executing on e108600-lin, pid 23303 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47393980707000 because m5_exit instruction encountered +Exiting @ tick 47384351300000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index bdfed319a..374e48ec0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384315 # Number of seconds simulated -sim_ticks 47384315163000 # Number of ticks simulated -final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.384351 # Number of seconds simulated +sim_ticks 47384351300000 # Number of ticks simulated +final_tick 47384351300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151085 # Simulator instruction rate (inst/s) -host_op_rate 177673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7925620115 # Simulator tick rate (ticks/s) -host_mem_usage 773240 # Number of bytes of host memory used -host_seconds 5978.63 # Real time elapsed on the host -sim_insts 903281747 # Number of instructions simulated -sim_ops 1062243320 # Number of ops (including micro ops) simulated +host_inst_rate 172914 # Simulator instruction rate (inst/s) +host_op_rate 195786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6718052359 # Simulator tick rate (ticks/s) +host_mem_usage 777068 # Number of bytes of host memory used +host_seconds 7053.29 # Real time elapsed on the host +sim_insts 1219610005 # Number of instructions simulated +sim_ops 1380933056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11439440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 16431296 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory -system.physmem.bytes_read::total 62456088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4233376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2647264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6880640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79489088 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 205248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 202880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4270112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16788488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21729728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 123968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 83584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3109600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10061712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12393536 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory +system.physmem.bytes_read::total 69407256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4270112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3109600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7379712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 85545984 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 79509672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1380 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82099 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 200409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 217140 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3149 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41407 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 178754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 256739 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 991898 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1242017 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 85566568 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 262333 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 339527 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1306 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 157227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 193649 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1100510 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1336656 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1244591 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 89341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 270667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 293282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 241418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 346767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1318075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 89341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55868 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 145209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1677540 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1339230 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 90117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 354304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 458584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 212343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 261553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1464772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 90117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1805364 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1677974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1677540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 89341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 271101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 293282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 241418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 346767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2996050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 991898 # Number of read requests accepted -system.physmem.writeReqs 1244591 # Number of write requests accepted -system.physmem.readBursts 991898 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1244591 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 63457600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue -system.physmem.bytesWritten 79508544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62456088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 79509672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1805798 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1805364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 90117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 354739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 458584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 212343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 261553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3270570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1100510 # Number of read requests accepted +system.physmem.writeReqs 1339230 # Number of write requests accepted +system.physmem.readBursts 1100510 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1339230 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 70408640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue +system.physmem.bytesWritten 85564992 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69407256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 85566568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57534 # Per bank write bursts -system.physmem.perBankRdBursts::1 67322 # Per bank write bursts -system.physmem.perBankRdBursts::2 57239 # Per bank write bursts -system.physmem.perBankRdBursts::3 59640 # Per bank write bursts -system.physmem.perBankRdBursts::4 58543 # Per bank write bursts -system.physmem.perBankRdBursts::5 68655 # Per bank write bursts -system.physmem.perBankRdBursts::6 57471 # Per bank write bursts -system.physmem.perBankRdBursts::7 60839 # Per bank write bursts -system.physmem.perBankRdBursts::8 60208 # Per bank write bursts -system.physmem.perBankRdBursts::9 81942 # Per bank write bursts -system.physmem.perBankRdBursts::10 59318 # Per bank write bursts -system.physmem.perBankRdBursts::11 61436 # Per bank write bursts -system.physmem.perBankRdBursts::12 60309 # Per bank write bursts -system.physmem.perBankRdBursts::13 62906 # Per bank write bursts -system.physmem.perBankRdBursts::14 58748 # Per bank write bursts -system.physmem.perBankRdBursts::15 59415 # Per bank write bursts -system.physmem.perBankWrBursts::0 74024 # Per bank write bursts -system.physmem.perBankWrBursts::1 81724 # Per bank write bursts -system.physmem.perBankWrBursts::2 74878 # Per bank write bursts -system.physmem.perBankWrBursts::3 76858 # Per bank write bursts -system.physmem.perBankWrBursts::4 76593 # Per bank write bursts -system.physmem.perBankWrBursts::5 82864 # Per bank write bursts -system.physmem.perBankWrBursts::6 74278 # Per bank write bursts -system.physmem.perBankWrBursts::7 78173 # Per bank write bursts -system.physmem.perBankWrBursts::8 76626 # Per bank write bursts -system.physmem.perBankWrBursts::9 80136 # Per bank write bursts -system.physmem.perBankWrBursts::10 77163 # Per bank write bursts -system.physmem.perBankWrBursts::11 80655 # Per bank write bursts -system.physmem.perBankWrBursts::12 76245 # Per bank write bursts -system.physmem.perBankWrBursts::13 79687 # Per bank write bursts -system.physmem.perBankWrBursts::14 75064 # Per bank write bursts -system.physmem.perBankWrBursts::15 77353 # Per bank write bursts +system.physmem.perBankRdBursts::0 70416 # Per bank write bursts +system.physmem.perBankRdBursts::1 75191 # Per bank write bursts +system.physmem.perBankRdBursts::2 64063 # Per bank write bursts +system.physmem.perBankRdBursts::3 69912 # Per bank write bursts +system.physmem.perBankRdBursts::4 59812 # Per bank write bursts +system.physmem.perBankRdBursts::5 69643 # Per bank write bursts +system.physmem.perBankRdBursts::6 65430 # Per bank write bursts +system.physmem.perBankRdBursts::7 68144 # Per bank write bursts +system.physmem.perBankRdBursts::8 61950 # Per bank write bursts +system.physmem.perBankRdBursts::9 89644 # Per bank write bursts +system.physmem.perBankRdBursts::10 68037 # Per bank write bursts +system.physmem.perBankRdBursts::11 70586 # Per bank write bursts +system.physmem.perBankRdBursts::12 61163 # Per bank write bursts +system.physmem.perBankRdBursts::13 71056 # Per bank write bursts +system.physmem.perBankRdBursts::14 65094 # Per bank write bursts +system.physmem.perBankRdBursts::15 69994 # Per bank write bursts +system.physmem.perBankWrBursts::0 85481 # Per bank write bursts +system.physmem.perBankWrBursts::1 90029 # Per bank write bursts +system.physmem.perBankWrBursts::2 81966 # Per bank write bursts +system.physmem.perBankWrBursts::3 85433 # Per bank write bursts +system.physmem.perBankWrBursts::4 77921 # Per bank write bursts +system.physmem.perBankWrBursts::5 84076 # Per bank write bursts +system.physmem.perBankWrBursts::6 83054 # Per bank write bursts +system.physmem.perBankWrBursts::7 85039 # Per bank write bursts +system.physmem.perBankWrBursts::8 78873 # Per bank write bursts +system.physmem.perBankWrBursts::9 84297 # Per bank write bursts +system.physmem.perBankWrBursts::10 83224 # Per bank write bursts +system.physmem.perBankWrBursts::11 86586 # Per bank write bursts +system.physmem.perBankWrBursts::12 79852 # Per bank write bursts +system.physmem.perBankWrBursts::13 85124 # Per bank write bursts +system.physmem.perBankWrBursts::14 80745 # Per bank write bursts +system.physmem.perBankWrBursts::15 85253 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51477 # Number of times write queue was full causing retry -system.physmem.totGap 47384313590500 # Total gap between requests +system.physmem.numWrRetry 51215 # Number of times write queue was full causing retry +system.physmem.totGap 47384349786500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 970540 # Read request sizes (log2) +system.physmem.readPktSize::6 1079152 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1242017 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 445378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 243433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 56880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 37150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 31949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 29173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 27068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 6848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3836 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1336656 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 480448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 272774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 88894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 67384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 42690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 36411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -189,137 +189,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 41131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 48159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 53054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 68707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 72599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 69938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 72538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120872 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 982131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 145.566960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.657532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 193.069606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 654413 66.63% 66.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194527 19.81% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50477 5.14% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21176 2.16% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16419 1.67% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9395 0.96% 96.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6596 0.67% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5289 0.54% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23839 2.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 982131 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 56922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.418608 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 74.895923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 56917 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 24574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 38198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 48248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 57744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 79272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 77429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 90816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 73646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 69003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 120342 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1069816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 145.794462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.799028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 192.755385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 712470 66.60% 66.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 211048 19.73% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55044 5.15% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23596 2.21% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18557 1.73% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10547 0.99% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7452 0.70% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5550 0.52% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25552 2.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1069816 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.613853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 71.325725 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 62454 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 56922 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 56922 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.824971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.750218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 638.100533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 56920 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 62458 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.405633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.660061 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 609.107080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 62456 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 56922 # Writes before turning the bus around for reads -system.physmem.totQLat 43578574020 # Total ticks spent queuing -system.physmem.totMemAccLat 62169667770 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4957625000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43951.06 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 62458 # Writes before turning the bus around for reads +system.physmem.totQLat 48895390505 # Total ticks spent queuing +system.physmem.totMemAccLat 69522921755 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5500675000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44444.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62701.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 63194.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.75 # Average write queue length when enqueuing -system.physmem.readRowHits 750886 # Number of row buffer hits during reads -system.physmem.writeRowHits 500828 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.31 # Row buffer hit rate for writes -system.physmem.avgGap 21186920.03 # Average gap between requests -system.physmem.pageHitRate 56.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3717395640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2028340875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3800456400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4013660160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1158326321940 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27414513105000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31681312358415 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.603367 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45606511009457 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582266400000 # Time in different power states +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.21 # Average write queue length when enqueuing +system.physmem.readRowHits 830166 # Number of row buffer hits during reads +system.physmem.writeRowHits 537104 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.17 # Row buffer hit rate for writes +system.physmem.avgGap 19421885.03 # Average gap between requests +system.physmem.pageHitRate 56.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4087639080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2230358625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4232326800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4361033520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1166279241240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27407555547000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31683661258905 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.652499 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45594888254330 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582267440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 195537314293 # Time in different power states +system.physmem_0.memoryStateTime::ACT 207195159170 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3707514720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2022949500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3933399600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4036579920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1156667621085 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.602035 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states +system.physmem_1.actEnergy 4000169880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2182632375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4348679400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4302421920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1168435080135 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27405664460250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31683848556600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.656452 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45591701065782 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582267440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states +system.physmem_1.memoryStateTime::ACT 210382633218 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -346,30 +345,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 138091637 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6789940 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97223509 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 59866310 # Number of BTB hits +system.cpu0.branchPred.lookups 199183431 # Number of BP lookups +system.cpu0.branchPred.condPredicted 140489040 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7036065 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 156342542 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 99990575 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 63.956089 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20013017 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 198399 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4618183 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2919648 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1698535 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 412858 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,90 +398,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 530338 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 286535 99.37% 99.37% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1269 0.44% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 337 0.12% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 607513 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 607513 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13877 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97395 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 289192 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 318321 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2219.643065 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12711.673990 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 315923 99.25% 99.25% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1786 0.56% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 409 0.13% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 127 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 31 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 288343 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 261783 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19021.382214 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 16878.246550 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 10891.763559 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 246122 94.02% 94.02% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 14409 5.50% 99.52% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 656 0.25% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 427 0.16% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 44 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 47 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 261783 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 513336492752 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.609866 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.537961 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 512309669252 99.80% 99.80% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 522001000 0.10% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 221126000 0.04% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 109873500 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 86703000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 51185000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 14405500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 21121500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 397500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 10500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 513336492752 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 79785 88.44% 88.44% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10426 11.56% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 90211 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 530338 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 318321 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 324666 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20482.457356 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17703.017560 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16938.599592 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 320665 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2783 0.86% 99.62% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 369 0.11% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 625 0.19% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 139 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 57 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 324666 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 513372677252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.571567 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.552695 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 512028975252 99.74% 99.74% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 726675000 0.14% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 290458500 0.06% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 129299000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 102361000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 55725500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 16517000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 21785000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 858500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 513372677252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 97395 87.53% 87.53% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13877 12.47% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 111272 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 607513 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 530338 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90211 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 607513 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111272 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90211 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 620549 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111272 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 718785 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 99690232 # DTB read hits -system.cpu0.dtb.read_misses 367422 # DTB read misses -system.cpu0.dtb.write_hits 83046551 # DTB write hits -system.cpu0.dtb.write_misses 162916 # DTB write misses +system.cpu0.dtb.read_hits 141538315 # DTB read hits +system.cpu0.dtb.read_misses 437252 # DTB read misses +system.cpu0.dtb.write_hits 86796370 # DTB write hits +system.cpu0.dtb.write_misses 170261 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35477 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 43183 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 271 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6902 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 100057654 # DTB read accesses -system.cpu0.dtb.write_accesses 83209467 # DTB write accesses +system.cpu0.dtb.perms_faults 42288 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 141975567 # DTB read accesses +system.cpu0.dtb.write_accesses 86966631 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 182736783 # DTB hits -system.cpu0.dtb.misses 530338 # DTB misses -system.cpu0.dtb.accesses 183267121 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 228334685 # DTB hits +system.cpu0.dtb.misses 607513 # DTB misses +system.cpu0.dtb.accesses 228942198 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -512,1195 +507,1194 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 81834 # Table walker walks requested -system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 71606 99.41% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 296 0.41% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 49 0.07% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 70 0.10% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 72029 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 69659 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 23684.893553 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21955.996989 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 12765.700584 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 63811 91.60% 91.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 5242 7.53% 99.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 100 0.14% 99.27% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 402 0.58% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 69659 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 375894589280 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.860066 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.347066 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 52618427692 14.00% 14.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 323259257588 86.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 15893500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 943500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 54500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 375894589280 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58824 98.28% 98.28% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1030 1.72% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59854 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 87943 # Table walker walks requested +system.cpu0.itb.walker.walksLong 87943 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1130 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62851 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10253 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 77690 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1458.353713 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 10159.922633 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 76707 98.73% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 405 0.52% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 337 0.43% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 198 0.25% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77690 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 74234 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26234.178409 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23080.051735 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 21732.027543 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 71871 96.82% 96.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1986 2.68% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 153 0.21% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 128 0.17% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 62 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 74234 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 410290287148 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.846605 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.360675 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 62979367364 15.35% 15.35% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 347270506784 84.64% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 38246000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1931000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 236000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 410290287148 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62851 98.23% 98.23% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1130 1.77% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 63981 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81834 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81834 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 87943 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 87943 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59854 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59854 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 141688 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 216521473 # ITB inst hits -system.cpu0.itb.inst_misses 81834 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63981 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63981 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 151924 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 282848559 # ITB inst hits +system.cpu0.itb.inst_misses 87943 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25278 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 30949 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 212727 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses -system.cpu0.itb.hits 216521473 # DTB hits -system.cpu0.itb.misses 81834 # DTB misses -system.cpu0.itb.accesses 216603307 # DTB accesses -system.cpu0.numPwrStateTransitions 26480 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13240 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3550703383.143278 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 88629328460.442917 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3078 23.25% 23.25% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10135 76.55% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7390881192332 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13240 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 373002370183 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 47011312792817 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 746014900 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 282936502 # ITB inst accesses +system.cpu0.itb.hits 282848559 # DTB hits +system.cpu0.itb.misses 87943 # DTB misses +system.cpu0.itb.accesses 282936502 # DTB accesses +system.cpu0.numPwrStateTransitions 28168 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 14084 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3333377849.836978 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 92382687873.308472 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 4020 28.54% 28.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10033 71.24% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 13 0.09% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6914082605000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 14084 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 437057662896 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46947293637104 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 874125395 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14620490 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1715297 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 295776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5589619 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 711520 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 813110 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 216323861 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1696724 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 26704 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 722267733 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.989116 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.222569 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 92275983 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 768900237 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 199183431 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 122923240 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 738928784 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15190816 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2037144 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 294842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6072240 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 792344 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 839757 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 282635522 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1737700 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28623 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 848836502 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.034930 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.208968 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 380266002 52.65% 52.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 133082578 18.43% 71.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45433566 6.29% 77.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 163485587 22.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 416377385 49.05% 49.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 176079063 20.74% 69.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 66732959 7.86% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 189647095 22.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 722267733 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.185106 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.817910 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 106050198 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 344087060 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 231125881 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 35774912 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5229682 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19752919 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2120005 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 632519077 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23747295 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5229682 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 140879480 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 46445701 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 235545365 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 231642525 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 62524980 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 614970268 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6274841 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9683853 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 239254 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 254272 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 29219197 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11058 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 585821211 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 944611426 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 725501320 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 860588 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 527918401 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 57902804 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14873386 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12932012 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 72326353 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100125445 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86327833 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8833111 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7713299 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 593239093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14925406 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 596650262 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2740149 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54305512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35087941 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 259840 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 722267733 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.826079 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.071801 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 848836502 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.227866 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.879622 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 110330106 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 381856903 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 311429263 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39757521 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5462709 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 29836532 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2173523 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 791623702 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 24444549 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5462709 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 147675961 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53914284 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 258297798 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 313275075 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 70210675 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 773227105 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6509157 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10689754 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 377832 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 811571 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 32991272 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11799 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 742885425 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1169549966 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 880889153 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 700737 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 682115784 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 60769635 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16576266 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14423738 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79729853 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 141637487 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90242008 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9692958 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8374311 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 749539213 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16620515 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 754385019 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2849937 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 57154900 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 36998097 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 294454 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 848836502 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888728 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088535 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 398653423 55.19% 55.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 132668388 18.37% 73.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 116695962 16.16% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 66414173 9.20% 98.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7831504 1.08% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4283 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 442949824 52.18% 52.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 161566736 19.03% 71.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 148384909 17.48% 88.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 87697049 10.33% 99.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8232602 0.97% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5382 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 722267733 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 848836502 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62572261 45.86% 45.86% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 47637 0.03% 45.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 27538 0.02% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 12 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 35025206 25.67% 71.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 38780691 28.42% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 74538342 48.88% 48.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 62447 0.04% 48.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15099 0.01% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 9 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 37581602 24.64% 73.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40298347 26.43% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 408003074 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1391206 0.23% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 75246 0.01% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 75513 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 102801955 17.23% 85.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84303178 14.13% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 519755806 68.90% 68.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1543884 0.20% 69.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 77211 0.01% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 64 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 42719 0.01% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 144854124 19.20% 88.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88111156 11.68% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 596650262 # Type of FU issued -system.cpu0.iq.rate 0.799783 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 136453345 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228699 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2053360508 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 662051351 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 579495604 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1401241 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 556367 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 521179 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 732235238 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 868332 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2674563 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 754385019 # Type of FU issued +system.cpu0.iq.rate 0.863017 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 152495846 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.202146 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2511823586 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 823027375 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 736101219 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1128735 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 443604 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 415332 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 906176667 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 704147 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2868207 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12322480 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 16225 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 138716 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5498195 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13104832 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17724 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 157642 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5794849 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2627025 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4349073 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2875718 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4918474 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5229682 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6015766 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1577054 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 608291813 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5462709 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7926079 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1884320 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 766295642 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100125445 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86327833 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12661031 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 57348 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1462300 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 138716 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1920652 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3139987 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5060639 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 588583301 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 99681195 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7546532 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 141637487 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90242008 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 14144816 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 61216 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1749510 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 157642 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2035907 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3235941 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5271848 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 745963336 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 141529970 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7821454 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 127314 # number of nop insts executed -system.cpu0.iew.exec_refs 182727665 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110905985 # Number of branches executed -system.cpu0.iew.exec_stores 83046470 # Number of stores executed -system.cpu0.iew.exec_rate 0.788970 # Inst execution rate -system.cpu0.iew.wb_sent 580785082 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 580016783 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 281571835 # num instructions producing a value -system.cpu0.iew.wb_consumers 462036259 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.777487 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609415 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 47239068 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14665566 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4709377 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 713265593 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.776512 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.575400 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 135914 # number of nop insts executed +system.cpu0.iew.exec_refs 228324326 # number of memory reference insts executed +system.cpu0.iew.exec_branches 170531782 # Number of branches executed +system.cpu0.iew.exec_stores 86794356 # Number of stores executed +system.cpu0.iew.exec_rate 0.853383 # Inst execution rate +system.cpu0.iew.wb_sent 737330155 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 736516551 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 351214969 # num instructions producing a value +system.cpu0.iew.wb_consumers 595098705 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.842575 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.590179 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 49835507 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16326061 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4903366 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 839368834 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.844688 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.533259 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 472345396 66.22% 66.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 122854697 17.22% 83.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 54352038 7.62% 91.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18530727 2.60% 93.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13156863 1.84% 95.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8843989 1.24% 96.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5973723 0.84% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3646989 0.51% 98.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13561171 1.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 512658006 61.08% 61.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 158759517 18.91% 79.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 92536082 11.02% 91.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 27862473 3.32% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13576189 1.62% 95.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9358920 1.11% 97.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6289735 0.75% 97.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3875341 0.46% 98.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14452571 1.72% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 713265593 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 471410910 # Number of instructions committed -system.cpu0.commit.committedOps 553858980 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 839368834 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 622433451 # Number of instructions committed +system.cpu0.commit.committedOps 709004821 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 168632602 # Number of memory references committed -system.cpu0.commit.loads 87802964 # Number of loads committed -system.cpu0.commit.membars 3653468 # Number of memory barriers committed -system.cpu0.commit.branches 105429162 # Number of branches committed -system.cpu0.commit.fp_insts 512997 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 508174699 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13889214 # Number of function calls committed. +system.cpu0.commit.refs 212979813 # Number of memory references committed +system.cpu0.commit.loads 128532654 # Number of loads committed +system.cpu0.commit.membars 3921678 # Number of memory barriers committed +system.cpu0.commit.branches 164749224 # Number of branches committed +system.cpu0.commit.fp_insts 407380 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 634275437 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14942203 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 383941234 69.32% 69.32% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1156077 0.21% 69.53% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 59954 0.01% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 69071 0.01% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 87802964 15.85% 85.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 80829638 14.59% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 494636379 69.76% 69.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1291078 0.18% 69.95% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 60530 0.01% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 37021 0.01% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.96% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 128532654 18.13% 88.09% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84447159 11.91% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 553858980 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13561171 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1296549352 # The number of ROB reads -system.cpu0.rob.rob_writes 1211163120 # The number of ROB writes -system.cpu0.timesIdled 982435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23747167 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 94022615466 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 471410910 # Number of Instructions Simulated -system.cpu0.committedOps 553858980 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.582515 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.582515 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.631905 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.631905 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads -system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes -system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads -system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5793916 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 709004821 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14452571 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1579278211 # The number of ROB reads +system.cpu0.rob.rob_writes 1527109253 # The number of ROB writes +system.cpu0.timesIdled 1033857 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25288893 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93894577230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 622433451 # Number of Instructions Simulated +system.cpu0.committedOps 709004821 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.404368 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.404368 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.712064 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.712064 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 848778973 # number of integer regfile reads +system.cpu0.int_regfile_writes 506977822 # number of integer regfile writes +system.cpu0.fp_regfile_reads 685984 # number of floating regfile reads +system.cpu0.fp_regfile_writes 317032 # number of floating regfile writes +system.cpu0.cc_regfile_reads 188384037 # number of cc regfile reads +system.cpu0.cc_regfile_writes 189031095 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1590236345 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16401028 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6409966 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.619482 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 199938758 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6410478 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.189368 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810689 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1810689 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1836259 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1836259 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 152398464 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 152398464 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 152611509 # number of overall hits -system.cpu0.dcache.overall_hits::total 152611509 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6448823 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6448823 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7191873 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7191873 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 676181 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 676181 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 810826 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 810826 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 247493 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 247493 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187335 # 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number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88064855 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88064855 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77714642 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77714642 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 889226 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 889226 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1070489 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1070489 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2058182 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2058182 # 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number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 128770220 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 128770220 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81278747 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81278747 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1002323 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1002323 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033701 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1033701 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2154950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2154950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2115422 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2115422 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 211082668 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 211082668 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 212084991 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 212084991 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.055451 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.055451 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.098731 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.098731 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774570 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774570 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.811251 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.811251 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.134325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.134325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.075817 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.075817 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.079120 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.079120 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15199.082129 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15199.082129 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.245799 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.245799 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37877.388252 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37877.388252 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14914.790786 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14914.790786 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25143.319317 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25143.319317 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17777.853389 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17777.853389 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16983.215453 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16983.215453 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9060649 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19650869 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 747322 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 698056 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.124157 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28.150849 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5793928 # number of writebacks -system.cpu0.dcache.writebacks::total 5793928 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3323367 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3323367 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5758852 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5758852 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4670 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4670 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 128237 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 128237 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9086889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9086889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9086889 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9086889 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125456 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3125456 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1433021 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1433021 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 669278 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 669278 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 806156 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 806156 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119256 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 119256 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187331 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 187331 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5364633 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5364633 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6033911 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6033911 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32527 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64878 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43142423000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43142423000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30169010620 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30169010620 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14964455000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14964455000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28947099689 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28947099689 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564593500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564593500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4499876000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4499876000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3717500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3717500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102258533309 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 102258533309 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117222988309 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 117222988309 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6208668000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6208668000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6208668000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6208668000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018440 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018440 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752652 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752652 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753073 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753073 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057942 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057942 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092573 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092573 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032152 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032152 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035972 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.035972 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13803.561144 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13803.561144 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21052.734482 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21052.734482 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22359.101898 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22359.101898 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35907.565892 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35907.565892 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13119.620816 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13119.620816 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24020.989585 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24020.989585 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18375.158370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18375.158370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17524.990566 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17524.990566 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9668545 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 23532840 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 779892 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 794197 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.397287 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.630986 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6410042 # number of writebacks +system.cpu0.dcache.writebacks::total 6410042 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3690786 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3690786 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6446005 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6446005 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4347 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4347 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 149571 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 149571 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10141138 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10141138 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10141138 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10141138 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3449649 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3449649 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1578703 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1578703 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 769355 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 769355 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 834244 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 834244 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139893 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139893 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195965 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195965 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5862596 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5862596 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6631951 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6631951 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31285 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31285 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30958 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30958 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62243 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62243 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50416416500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50416416500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33875543231 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33875543231 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17245260500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17245260500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 30759768392 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 30759768392 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1918237000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1918237000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4731380000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4731380000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3064500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3064500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 115051728123 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 115051728123 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132296988623 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 132296988623 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6062914000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6062914000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6062914000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6062914000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.026789 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026789 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019423 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019423 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767572 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767572 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.807046 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.807046 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064917 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064917 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092636 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092636 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031270 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031270 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14614.940969 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14614.940969 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21457.831670 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21457.831670 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22415.218592 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22415.218592 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36871.428973 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36871.428973 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13712.172875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13712.172875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24144.005307 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24144.005307 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 6136519 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19624.706891 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19624.706891 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19948.426733 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19948.426733 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193796.196260 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193796.196260 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97407.162251 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97407.162251 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 6234341 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.962382 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 276007197 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6234853 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 44.268437 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12884658000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962382 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits -system.cpu0.icache.overall_hits::total 209807209 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6488653 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6488653 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6488653 # number of overall misses -system.cpu0.icache.overall_misses::total 6488653 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69596700450 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 69596700450 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 69596700450 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 69596700450 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 69596700450 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 69596700450 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 216295862 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 216295862 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 216295862 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 216295862 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 216295862 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 216295862 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029999 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029999 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029999 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029999 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029999 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029999 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10725.908821 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10725.908821 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10725.908821 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10725.908821 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10132412 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 737599 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.737020 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 48.444444 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 6136519 # number of writebacks -system.cpu0.icache.writebacks::total 6136519 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351573 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 351573 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 351573 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 351573 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 351573 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 351573 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6137080 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6137080 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6137080 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6137080 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6137080 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6137080 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 571449747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 571449747 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 276007197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 276007197 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 276007197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 276007197 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 276007197 # number of overall hits +system.cpu0.icache.overall_hits::total 276007197 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6600102 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6600102 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6600102 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6600102 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6600102 # number of overall misses +system.cpu0.icache.overall_misses::total 6600102 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71550800576 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 71550800576 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 71550800576 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 71550800576 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 71550800576 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 71550800576 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 282607299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 282607299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 282607299 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 282607299 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 282607299 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 282607299 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.023354 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023354 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.023354 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023354 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.023354 # 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number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6235149 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6235149 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6235149 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6235149 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62984871633 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 62984871633 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62984871633 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 62984871633 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62984871633 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 62984871633 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64720811973 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 64720811973 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64720811973 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 64720811973 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64720811973 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 64720811973 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028374 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028374 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028374 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10263.003193 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.022063 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.022063 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.022063 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10379.994443 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8818791 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8829534 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 9675 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2565485 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1134314 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2939155 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16147.226336 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 18219506 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2955258 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.165115 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 23.448036 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000032 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1047.520376 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.906351 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002205 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001431 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 15244.220202 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.043386 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.165258 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000002 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 782.797489 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.930433 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003543 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003794 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063936 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.973922 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14569 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047778 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985548 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1151 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14871 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 211 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 564 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1288 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # 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mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251498 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771791 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771791 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021110 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048079 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098271 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242815 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157972 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021110 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048079 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098271 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242815 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.217839 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27568.864230 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46845.335420 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20843.655320 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20843.655320 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16505.909731 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16505.909731 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 454785.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 454785.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40291.912662 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40291.912662 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28979.940194 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28953.724719 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28953.724719 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36518.816670 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36518.816670 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30644.561078 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35447.837007 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230754 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38987.144877 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56590.929630 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20556.048168 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20556.048168 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16627.774157 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16627.774157 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 655374.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 655374.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 44819.023202 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 44819.023202 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28775.786737 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31374.295958 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31374.295958 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36606.229223 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36606.229223 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32554.736432 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40136.035953 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182858.994066 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142583.305463 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185781.620585 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143370.934611 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 475065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 341372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 522361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 76 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1216718 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1192935 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6137080 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4901216 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 866556 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 803970 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18453192 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18807742 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 402695 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170958 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 38834587 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 785846352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 704525389 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1531416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4405792 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1496308949 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6903738 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20024554 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.116908 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.321383 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93378.821715 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90238.424152 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 26220064 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13479100 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2657 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2182451 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2181920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 531 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 979416 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11666319 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 30958 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 30958 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6060800 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8438347 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2860883 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1184490 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 488552 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348527 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 533031 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1347603 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1325056 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6235149 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5307790 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 891051 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 832317 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18746760 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20650560 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436622 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1328978 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 41162920 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 798358288 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 780155262 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1670248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5039864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1585223662 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7567060 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 126041936 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 21529267 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.118569 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.323357 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 17683990 88.31% 88.31% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2340100 11.69% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 464 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 18977100 88.15% 88.15% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2551636 11.85% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 531 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20024554 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 24612511939 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 21529267 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 26091722433 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 212521499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 187623310 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9233457820 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9380939070 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8324768239 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9216328089 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 211573883 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 228203766 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 620908635 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 699632706 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 127244460 # Number of BP lookups -system.cpu1.branchPred.condPredicted 83927531 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6411720 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89791062 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 55539581 # Number of BTB hits +system.cpu1.branchPred.lookups 194671556 # Number of BP lookups +system.cpu1.branchPred.condPredicted 153305610 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6254288 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 157865267 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 88709282 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 56.193033 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16475486 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 172497 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3896881 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2381021 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1515860 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 389837 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1730,85 +1724,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 579824 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 298702 99.17% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1877 0.62% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.14% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 301214 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 311038 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20491.173104 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17661.433181 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 17134.136599 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 306887 98.67% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3006 0.97% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 404 0.13% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 531 0.17% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 60 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 29 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 311038 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 427436234332 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.596252 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.559035 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 426093627832 99.69% 99.69% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 733360500 0.17% 99.86% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 289523500 0.07% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 124054000 0.03% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 101131500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 55199000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 17877500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 20812500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 638500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 427436234332 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 93540 88.44% 88.44% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 12232 11.56% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 105772 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 579824 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 533309 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 533309 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10503 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 81680 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 248509 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 284800 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2470.932233 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13518.648671 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 279405 98.11% 98.11% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 3083 1.08% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 908 0.32% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 713 0.25% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 284 0.10% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 163 0.06% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 13 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 284800 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 268382 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19517.668845 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17136.373439 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13227.910444 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 250971 93.51% 93.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 15361 5.72% 99.24% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 757 0.28% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 835 0.31% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 87 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 116 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 116 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 51 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 29 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 31 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 268382 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 466126532996 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.617043 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.546089 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 464998520496 99.76% 99.76% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 569195000 0.12% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 249472000 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 122508000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 91886000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 55274500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 15901500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 23390500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 385000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 466126532996 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 81681 88.61% 88.61% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10503 11.39% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 92184 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 533309 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 579824 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105772 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 533309 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92184 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105772 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 685596 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92184 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 625493 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 94100008 # DTB read hits -system.cpu1.dtb.read_misses 416726 # DTB read misses -system.cpu1.dtb.write_hits 75732153 # DTB write hits -system.cpu1.dtb.write_misses 163098 # DTB write misses +system.cpu1.dtb.read_hits 161844710 # DTB read hits +system.cpu1.dtb.read_misses 366883 # DTB read misses +system.cpu1.dtb.write_hits 74184112 # DTB write hits +system.cpu1.dtb.write_misses 166426 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40885 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34599 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 386 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6272 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 94516734 # DTB read accesses -system.cpu1.dtb.write_accesses 75895251 # DTB write accesses +system.cpu1.dtb.perms_faults 37354 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 162211593 # DTB read accesses +system.cpu1.dtb.write_accesses 74350538 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 169832161 # DTB hits -system.cpu1.dtb.misses 579824 # DTB misses -system.cpu1.dtb.accesses 170411985 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 236028822 # DTB hits +system.cpu1.dtb.misses 533309 # DTB misses +system.cpu1.dtb.accesses 236562131 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1838,1179 +1840,1178 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 86146 # Table walker walks requested -system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 74992 98.83% 98.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 442 0.58% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 265 0.35% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 132 0.17% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 11 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75879 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 72359 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25927.458920 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22905.536509 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 21012.178040 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70191 97.00% 97.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1833 2.53% 99.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 132 0.18% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 128 0.18% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 41 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 72359 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 388687033168 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.860499 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.346749 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 54258161808 13.96% 13.96% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 334394621860 86.03% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 32560000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1626500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 63000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 388687033168 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61109 98.42% 98.42% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 983 1.58% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 62092 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 80718 # Table walker walks requested +system.cpu1.itb.walker.walksLong 80718 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 768 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57037 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 10137 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 70581 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 996.309205 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6981.449622 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 70036 99.23% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 380 0.54% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 60 0.09% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 83 0.12% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 70581 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 67942 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24162.219246 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22142.693859 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15015.121608 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 66991 98.60% 98.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 778 1.15% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 100 0.15% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 45 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 67942 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 397380257260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.877039 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.328570 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 48883602860 12.30% 12.30% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 348476867900 87.69% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 18158500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1572000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 56000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 397380257260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57037 98.67% 98.67% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 768 1.33% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 57805 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86146 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86146 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 80718 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 80718 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62092 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62092 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 148238 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 200179962 # ITB inst hits -system.cpu1.itb.inst_misses 86146 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57805 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57805 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 138523 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 264777096 # ITB inst hits +system.cpu1.itb.inst_misses 80718 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29927 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24684 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 195163 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses -system.cpu1.itb.hits 200179962 # DTB hits -system.cpu1.itb.misses 86146 # DTB misses -system.cpu1.itb.accesses 200266108 # DTB accesses -system.cpu1.numPwrStateTransitions 11252 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5626 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 8361647359.894774 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 196584250353.907135 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4008 71.24% 71.24% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1597 28.39% 99.63% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.18% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813562713000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5626 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 341687116232 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47042628046768 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 683375860 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 264857814 # ITB inst accesses +system.cpu1.itb.hits 264777096 # DTB hits +system.cpu1.itb.misses 80718 # DTB misses +system.cpu1.itb.accesses 264857814 # DTB accesses +system.cpu1.numPwrStateTransitions 9670 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 4835 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9724953244.725336 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 147881742434.863098 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3183 65.83% 65.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1626 33.63% 99.46% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.50% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.61% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.65% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.29% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7390881470984 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 4835 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 364202361753 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47020148938247 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 728406370 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13807906 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2007349 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 258832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5872913 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 777107 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 768148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 199953853 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1622392 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27919 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 664820080 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.994147 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.223667 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 83192103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 724269312 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 194671556 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 107565789 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 610871186 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13439122 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1719504 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 273339 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5608482 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 704978 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 774415 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 264561727 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1602178 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 26700 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 709863568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.153991 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.257090 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 348468390 52.42% 52.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 123001690 18.50% 70.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 42123132 6.34% 77.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 151226868 22.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 331851103 46.75% 46.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 119648081 16.86% 63.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 75565351 10.65% 74.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 182799033 25.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 664820080 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.186200 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.824539 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 100313259 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 315334519 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 208757120 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 35486026 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4929156 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17976704 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2012194 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 582722672 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22029645 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4929156 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 133756265 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 43242401 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 214462360 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 210347945 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 58081953 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 566482483 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5736321 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9739688 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 342221 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 843279 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 24527700 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11906 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 538415916 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 871757488 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 668460678 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 644937 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 483561743 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 54854172 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15093428 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13190698 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 71341154 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 94469141 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 78816060 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 9208116 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7878049 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 544809829 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15364466 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 549398452 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2550658 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 51789954 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 33366441 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 282362 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 664820080 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.826387 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.065764 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 709863568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.267257 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.994320 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 98062054 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 297890044 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 275618841 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 33512378 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4780251 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17247911 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1977266 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 743961992 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21656856 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4780251 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 130238128 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 40363481 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 204147620 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 276602035 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 53732053 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 728176206 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5626727 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9082967 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240191 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 268836 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 22296515 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11543 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 630286495 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 1024905330 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 827525539 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 801877 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 577128327 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 53158158 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14384532 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12638476 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 67737488 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 162372694 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 77181222 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8520193 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7294637 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 707349171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14663402 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 711466322 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2509310 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 50084332 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32217686 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252969 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 709863568 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.002258 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.141899 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 363096071 54.62% 54.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 129026402 19.41% 74.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 104942160 15.79% 89.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 60539163 9.11% 98.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7211179 1.08% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 5105 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 346424684 48.80% 48.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 123916139 17.46% 66.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 138092978 19.45% 85.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 94358537 13.29% 99.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7067534 1.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3696 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 664820080 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 709863568 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 54936992 44.00% 44.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 69872 0.06% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 6570 0.01% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.06% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 34367116 27.52% 71.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35481157 28.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53419887 27.72% 27.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 53191 0.03% 27.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 19037 0.01% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.76% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 103986379 53.96% 81.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35231745 18.28% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 373883416 68.05% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1335155 0.24% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 74884 0.01% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 48854 0.01% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97153433 17.68% 86.00% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 76902643 14.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 469996066 66.06% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1210560 0.17% 66.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 70927 0.01% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 81598 0.01% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 164776620 23.16% 89.41% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 75330478 10.59% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 549398452 # Type of FU issued -system.cpu1.iq.rate 0.803948 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 124861724 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227270 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1889962970 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 611689245 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 533047508 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1066396 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 424008 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 393622 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 673596915 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 663205 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2524444 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 711466322 # Type of FU issued +system.cpu1.iq.rate 0.976744 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 192710254 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.270863 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 2326678945 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 771690256 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 695698465 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1336829 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 536159 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 497637 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 903350253 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 826298 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2394067 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12144847 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16403 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 149896 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5262071 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11654320 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15948 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 130447 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5130974 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2572719 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4009144 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2399995 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3738162 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4929156 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7182655 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1646879 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 560304926 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4780251 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5901245 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1355404 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 722138785 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 94469141 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 78816060 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12974148 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 56258 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1524659 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 149896 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1843431 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2924818 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4768249 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 541845400 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94094962 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6980663 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 162372694 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 77181222 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12419825 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 58724 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1239916 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 130447 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1767111 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2862185 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4629296 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 704121990 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 161840669 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6820718 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 130631 # number of nop insts executed -system.cpu1.iew.exec_refs 169824676 # number of memory reference insts executed -system.cpu1.iew.exec_branches 101510793 # Number of branches executed -system.cpu1.iew.exec_stores 75729714 # Number of stores executed -system.cpu1.iew.exec_rate 0.792895 # Inst execution rate -system.cpu1.iew.wb_sent 534152020 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 533441130 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 258912640 # num instructions producing a value -system.cpu1.iew.wb_consumers 423656459 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.780597 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.611138 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 45293147 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15082103 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4436923 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 656213363 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.774724 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.573400 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 126212 # number of nop insts executed +system.cpu1.iew.exec_refs 236024480 # number of memory reference insts executed +system.cpu1.iew.exec_branches 169760384 # Number of branches executed +system.cpu1.iew.exec_stores 74183811 # Number of stores executed +system.cpu1.iew.exec_rate 0.966661 # Inst execution rate +system.cpu1.iew.wb_sent 696881354 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 696196102 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 357262878 # num instructions producing a value +system.cpu1.iew.wb_consumers 517340824 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.955780 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.690575 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 43732145 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14410433 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4314978 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 701540457 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.957790 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.589997 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 432598016 65.92% 65.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 117091486 17.84% 83.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 49126445 7.49% 91.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16229930 2.47% 93.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11628277 1.77% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8033144 1.22% 96.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5546832 0.85% 97.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3283510 0.50% 98.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12675723 1.93% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 413092247 58.88% 58.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 113176092 16.13% 75.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 83530992 11.91% 86.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 51841229 7.39% 94.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11508500 1.64% 95.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7726725 1.10% 97.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5343630 0.76% 97.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3131269 0.45% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12189773 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 656213363 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 431870837 # Number of instructions committed -system.cpu1.commit.committedOps 508384340 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 701540457 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 597176554 # Number of instructions committed +system.cpu1.commit.committedOps 671928235 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 155878283 # Number of memory references committed -system.cpu1.commit.loads 82324294 # Number of loads committed -system.cpu1.commit.membars 3722309 # Number of memory barriers committed -system.cpu1.commit.branches 96290107 # Number of branches committed -system.cpu1.commit.fp_insts 384716 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 467163355 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12903273 # Number of function calls committed. +system.cpu1.commit.refs 222768619 # Number of memory references committed +system.cpu1.commit.loads 150718371 # Number of loads committed +system.cpu1.commit.membars 39196572 # Number of memory barriers committed +system.cpu1.commit.branches 164739467 # Number of branches committed +system.cpu1.commit.fp_insts 488627 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 631392614 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12167965 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 351312000 69.10% 69.10% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1092238 0.21% 69.32% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 59391 0.01% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 42428 0.01% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82324294 16.19% 85.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 73553989 14.47% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 448043617 66.68% 66.68% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 985154 0.15% 66.83% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 56630 0.01% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 74173 0.01% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 150718371 22.43% 89.28% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 72050248 10.72% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 508384340 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12675723 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1193390155 # The number of ROB reads -system.cpu1.rob.rob_writes 1115923607 # The number of ROB writes -system.cpu1.timesIdled 934929 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18555780 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94085254498 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 431870837 # Number of Instructions Simulated -system.cpu1.committedOps 508384340 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.582362 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.582362 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.631967 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.631967 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads -system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes -system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads -system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes -system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads -system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5420466 # number of replacements -system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 671928235 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12189773 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1401264531 # The number of ROB reads +system.cpu1.rob.rob_writes 1439606443 # The number of ROB writes +system.cpu1.timesIdled 902579 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18542802 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94040296263 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 597176554 # Number of Instructions Simulated +system.cpu1.committedOps 671928235 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.219750 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.219750 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.819840 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.819840 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 799341399 # number of integer regfile reads +system.cpu1.int_regfile_writes 475575163 # number of integer regfile writes +system.cpu1.fp_regfile_reads 787030 # number of floating regfile reads +system.cpu1.fp_regfile_writes 454812 # number of floating regfile writes +system.cpu1.cc_regfile_reads 112918659 # number of cc regfile reads +system.cpu1.cc_regfile_writes 113685571 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1427881847 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14489141 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5047432 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.905792 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 212666270 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5047943 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 42.129293 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8477400492000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.905792 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.894347 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1700918 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1700918 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1741756 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1741756 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 140628202 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 140628202 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 140798630 # number of overall hits -system.cpu1.dcache.overall_hits::total 140798630 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6372316 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6372316 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7014697 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7014697 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658076 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 658076 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445973 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 445973 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 278553 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 278553 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193453 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193453 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13832986 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13832986 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14491062 # number of overall misses -system.cpu1.dcache.overall_misses::total 14491062 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 93736923500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 93736923500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 131113304741 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 131113304741 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11858807099 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11858807099 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4107251000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4107251000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4806521000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4806521000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3714500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3714500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 236709035340 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 236709035340 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 236709035340 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 236709035340 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82838741 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82838741 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71125310 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71125310 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828504 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 828504 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 497137 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 497137 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1979471 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1979471 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935209 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1935209 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154461188 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154461188 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155289692 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155289692 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076924 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.076924 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098624 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.098624 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794294 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794294 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.897083 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.897083 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140721 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140721 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099965 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099965 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089556 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.089556 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093316 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.093316 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.024346 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14710.024346 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18691.228536 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18691.228536 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26590.863346 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 26590.863346 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14744.953384 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14744.953384 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24845.936739 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24845.936739 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 457080025 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 457080025 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 145190780 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 145190780 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 62993534 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 62993534 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167629 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 167629 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 116242 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 116242 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1721505 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1721505 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1728884 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1728884 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 208300556 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 208300556 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 208468185 # number of overall hits +system.cpu1.dcache.overall_hits::total 208468185 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5993321 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5993321 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6604202 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6604202 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607895 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 607895 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421696 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 421696 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 237246 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 237246 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187668 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 187668 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13019219 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13019219 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13627114 # number of overall misses +system.cpu1.dcache.overall_misses::total 13627114 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 89379669000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 89379669000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119695443135 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 119695443135 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10488678921 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10488678921 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3322992000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3322992000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4669078500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4669078500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3521000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3521000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 219563791056 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 219563791056 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 219563791056 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 219563791056 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 151184101 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 151184101 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69597736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69597736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 775524 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 775524 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 537938 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 537938 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958751 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1958751 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1916552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1916552 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 221319775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 221319775 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 222095299 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 222095299 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039643 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.039643 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094891 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.094891 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783851 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783851 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.783912 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.783912 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121121 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121121 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.058825 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.058825 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.061357 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.061357 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14913.212391 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14913.212391 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18124.134170 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18124.134170 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24872.607094 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24872.607094 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14006.524873 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14006.524873 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24879.460004 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24879.460004 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17111.926184 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17111.926184 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16334.830072 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16334.830072 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3137293 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 21285332 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 376632 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 706469 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.329863 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 30.129180 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5420571 # number of writebacks -system.cpu1.dcache.writebacks::total 5420571 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3225514 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3225514 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5658563 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5658563 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3397 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3397 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 142581 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 142581 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8887474 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8887474 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8887474 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8887474 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3146802 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3146802 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1356134 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1356134 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 657988 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 657988 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 442576 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 442576 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193443 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193443 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4945512 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4945512 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5603500 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5603500 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12301 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43613350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43613350000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26794309953 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26794309953 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14059014500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14059014500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11316204599 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11316204599 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1866790500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1866790500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4613147000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4613147000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3645500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3645500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81723864552 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 81723864552 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 95782879052 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 95782879052 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 749898500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 749898500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749898500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749898500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037987 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019067 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019067 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794188 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794188 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.890250 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.890250 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068691 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068691 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099960 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099960 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036084 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036084 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.578709 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.578709 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19757.863126 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19757.863126 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21366.673100 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21366.673100 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25568.952223 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 25568.952223 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13729.227341 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13729.227341 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23847.577839 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23847.577839 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16864.590038 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16864.590038 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16112.273740 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16112.273740 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2706631 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18960106 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 351175 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 660083 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.707357 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.723821 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5047462 # number of writebacks +system.cpu1.dcache.writebacks::total 5047462 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3052290 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3052290 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5325465 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5325465 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3276 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3276 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122610 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122610 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8381031 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8381031 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8381031 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8381031 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2941031 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2941031 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1278737 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1278737 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607807 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 607807 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 418420 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 418420 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 114636 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114636 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187667 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 187667 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4638188 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4638188 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5245995 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5245995 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7218 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7480 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7480 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14698 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14698 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39704145500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39704145500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24666220214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24666220214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14600377000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14600377000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9957787421 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9957787421 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521960000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521960000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4481476500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4481476500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3456000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3456000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74328153135 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 74328153135 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88928530135 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 88928530135 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 880126000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 880126000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 880126000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 880126000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.019453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.019453 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783737 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783737 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.777822 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.777822 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058525 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058525 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097919 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097919 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.020957 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.020957 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023620 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.023620 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.077184 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13500.077184 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19289.517871 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19289.517871 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24021.403176 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24021.403176 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23798.545531 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23798.545531 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.457657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.457657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23879.938934 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23879.938934 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5742782 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16025.256659 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16025.256659 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16951.699370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16951.699370 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 121934.885010 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 121934.885010 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59880.664036 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59880.664036 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5706197 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.707809 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 258521982 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5706709 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 45.301413 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8517122288000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.707809 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979898 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979898 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits -system.cpu1.icache.overall_hits::total 193871102 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6076268 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6076268 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6076268 # number of overall misses -system.cpu1.icache.overall_misses::total 6076268 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64119298557 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 64119298557 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 64119298557 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 64119298557 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 64119298557 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 64119298557 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 199947370 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 199947370 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 199947370 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 199947370 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 199947370 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 199947370 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030389 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030389 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030389 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030389 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030389 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030389 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10552.414501 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10552.414501 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10552.414501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10552.414501 # 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average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9429094 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 708482 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.308869 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 5706197 # number of writebacks +system.cpu1.icache.writebacks::total 5706197 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 326394 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 326394 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 326394 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 326394 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 326394 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 326394 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5706805 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5706805 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5706805 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5706805 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5706805 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5706805 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58166889552 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 58166889552 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58166889552 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 58166889552 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58166889552 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 58166889552 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6789498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6789498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6789498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6789498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028724 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10127.714850 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58058775330 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 58058775330 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58058775330 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 58058775330 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58058775330 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 58058775330 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6679498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6679498 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6679498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6679498 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021571 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021571 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021571 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10173.604202 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99694 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99694 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6901811 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6907587 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 5314 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2216875 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.205555 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 757.041527 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.766629 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003838 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003858 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046206 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.820531 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14527 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 681 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 779 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 872441 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 872441 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5195235 # 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mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093506 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093506 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.249462 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249462 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.557861 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.557861 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021158 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.042934 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093506 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243611 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152463 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021158 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.042934 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093506 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243611 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220233 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38409.213974 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52588.772093 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20699.721837 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20699.721837 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16333.391896 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16333.391896 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 782000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36110.304736 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36110.304736 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26962.650321 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28763.842481 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28763.842481 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 28069.480634 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 28069.480634 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29359.627093 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36378.343549 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 114548.545276 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114324.009701 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 981692 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 441382 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342905 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 485827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1162425 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1140502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5743338 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4866994 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 495411 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 441012 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17229566 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17476902 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 425595 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1276864 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36408927 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 735111088 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 677743701 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1625328 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4839024 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1419319141 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6390553 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 18731260 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.122712 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.328150 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.216738 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30698.366424 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44779.098624 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21123.913810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21123.913810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16366.066612 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16366.066612 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247208.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247208.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33772.345856 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33772.345856 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28015.333267 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28790.171126 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28790.171126 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26887.644192 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26887.644192 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29263.608095 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33864.848983 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 113906.275977 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113706.451613 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55937.916723 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56102.370471 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 22350657 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11505244 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1543 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1883368 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1883027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 341 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 842183 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10302833 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7480 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7480 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4215889 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7583095 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2514473 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 909607 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 430035 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341692 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 476439 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1090279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1068076 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5706805 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4656106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 474602 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 416607 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17119850 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16343111 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 395526 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186164 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 35044651 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 730427376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 631688689 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1504072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4470264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1368090401 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6163170 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 73999248 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 18018661 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.123449 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.329009 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16432977 87.73% 87.73% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2298014 12.27% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15794619 87.66% 87.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2223701 12.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 341 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18731260 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23041315974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18018661 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 22188055468 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175324271 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 182014003 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8566090793 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7517136176 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 207825380 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 628033176 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40341 # Transaction distribution -system.iobus.trans_dist::ReadResp 40341 # Transaction distribution -system.iobus.trans_dist::WriteReq 136646 # Transaction distribution -system.iobus.trans_dist::WriteResp 136646 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40328 # Transaction distribution +system.iobus.trans_dist::ReadResp 40328 # Transaction distribution +system.iobus.trans_dist::WriteReq 136631 # Transaction distribution +system.iobus.trans_dist::WriteResp 136631 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47646 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3021,15 +3022,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353974 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47810 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47666 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3040,21 +3041,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155687 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339048 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37061004 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496821 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36938002 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 332000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -3066,79 +3067,79 @@ system.iobus.reqLayer14.occupancy 10500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24283001 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24205503 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36403501 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36443500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569408550 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147954000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115592 # number of replacements -system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115626 # number of replacements +system.iocache.tags.tagsinuse 11.305309 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115642 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9115830406000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.413187 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.892123 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463324 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.243258 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706582 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040856 # Number of tag accesses -system.iocache.tags.data_accesses 1040856 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041018 # Number of tag accesses +system.iocache.tags.data_accesses 1041018 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8901 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8938 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses -system.iocache.demand_misses::total 115651 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115629 # number of demand (read+write) misses +system.iocache.demand_misses::total 115669 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115611 # number of overall misses -system.iocache.overall_misses::total 115651 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5246000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1667860010 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1673106010 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115629 # number of overall misses +system.iocache.overall_misses::total 115669 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1667264523 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1672463023 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12956345994 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12956345994 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5615000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14624206004 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14629821004 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5615000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14624206004 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14629821004 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12925157527 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12925157527 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14592422050 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14597989550 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14592422050 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14597989550 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8901 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8938 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115669 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115669 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3152,53 +3153,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141783.783784 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187758.641225 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187567.938341 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187312.046175 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187118.261692 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121395.941028 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 121395.941028 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 140375 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126499.736310 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 140375 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126499.736310 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33436 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121103.717178 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121103.717178 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126204.856530 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126204.856530 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33241 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3541 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3524 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.442530 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.432747 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8901 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8938 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115629 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115669 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # 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number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7611309187 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7611309187 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3615000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8835019197 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8838634197 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3615000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8835019197 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8838634197 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7580015931 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3854.622142 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3569.542843 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 2315.690288 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 335.622211 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 552.279614 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2996.807733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11095.009846 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17872.212619 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.317794 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000194 # 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Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 21119.731437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 317.083055 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 501.157048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4189.705266 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12756.928607 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18825.078792 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.382680 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 33.853586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2676.679680 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1884.367858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1239.923843 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.322262 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004838 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007647 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063930 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.194655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.287248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000448 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040843 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028753 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.018920 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.970061 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11464 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 47937 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 482 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8826 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 76659871 # Number of tag accesses -system.l2c.tags.data_accesses 76659871 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2799563 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 321191 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6205 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4222 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 506602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 616661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 285940 # number of demand (read+write) hits -system.l2c.demand_hits::total 2922513 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6441 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4632 # number of overall hits -system.l2c.overall_hits::cpu0.inst 512914 # number of overall hits -system.l2c.overall_hits::cpu0.data 657705 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 321191 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6205 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.267108 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510866 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.232310 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.234808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091027 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.214345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.404246 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.265494 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21552.155177 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21730.655027 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21643.133400 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24653.874406 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24518.317079 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.136660 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83276.625632 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 78040.298609 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81476.190773 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 85858.003201 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90422.003810 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109363.844709 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24730.353519 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 21241.236877 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24165.559172 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84962.739511 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86688.086112 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 105739.396778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81260.835984 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79545.899685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78527.795024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84962.739511 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127321.987159 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84841.766649 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 85305.516080 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77758.231343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86688.086112 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128844.489781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 105739.396778 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164853.967627 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 96561.069817 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121669.858307 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167775.627329 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 95912.972007 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121759.442826 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82650.590416 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84328.526919 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 47094.992243 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74147.671970 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 4190264 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2528993 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3019 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 60003 # Transaction distribution -system.membus.trans_dist::ReadResp 904829 # Transaction distribution -system.membus.trans_dist::WriteReq 38534 # Transaction distribution -system.membus.trans_dist::WriteResp 38534 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution -system.membus.trans_dist::CleanEvict 238236 # Transaction distribution -system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution -system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 144708 # Transaction distribution -system.membus.trans_dist::ReadExResp 128413 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 844826 # Transaction distribution -system.membus.trans_dist::InvalidateReq 684897 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122672 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 59861 # Transaction distribution +system.membus.trans_dist::ReadResp 1006452 # Transaction distribution +system.membus.trans_dist::WriteReq 38438 # Transaction distribution +system.membus.trans_dist::WriteResp 38438 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1336656 # Transaction distribution +system.membus.trans_dist::CleanEvict 266935 # Transaction distribution +system.membus.trans_dist::UpgradeReq 438975 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 302731 # Transaction distribution +system.membus.trans_dist::UpgradeResp 22 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 150471 # Transaction distribution +system.membus.trans_dist::ReadExResp 135365 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 946591 # Transaction distribution +system.membus.trans_dist::InvalidateReq 696687 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4681290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4830500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5068695 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155802 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26078 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5027920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5176654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238145 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238145 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5414799 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155687 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134692416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 134901698 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7273344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7273344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 142175042 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 606585 # Total snoops (count) -system.membus.snoop_fanout::samples 2519367 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015113 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.122002 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52156 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147706944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 147915343 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7266880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 155182223 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 597489 # Total snoops (count) +system.membus.snoopTraffic 179456 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2633759 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013061 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113535 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2481292 98.49% 98.49% # Request fanout histogram -system.membus.snoop_fanout::1 38075 1.51% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2599360 98.69% 98.69% # Request fanout histogram +system.membus.snoop_fanout::1 34399 1.31% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2519367 # Request fanout histogram -system.membus.reqLayer0.occupancy 98170994 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2633759 # Request fanout histogram +system.membus.reqLayer0.occupancy 98019495 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21931994 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9377704107 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5794716587 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45616715 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3908,82 +3913,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12205642 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6628070 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1941255 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 157740 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 142803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 59863 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4654836 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38438 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38438 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4118892 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 380628 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1121842 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 140 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295903 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295903 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4433512 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 874748 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 839647 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9358904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7932274 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17291178 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230390413 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198586357 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 428976770 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2884507 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8248846 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.358423 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482538 # Request fanout histogram +system.toL2Bus.trans_dist::CleanEvict 2762121 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 740907 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 383504 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1124411 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298356 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298356 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4595571 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 881263 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 849910 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10458732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7383011 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17841743 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 265418110 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179948433 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 445366543 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3005080 # Total snoops (count) +system.toL2Bus.snoopTraffic 132103248 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8556754 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.351410 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.481053 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5304178 64.30% 64.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2932760 35.55% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11908 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5564766 65.03% 65.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2977051 34.79% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14937 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8248846 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9216694138 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8556754 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9506782087 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2593163 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2628899 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4234968582 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4728944566 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3934186551 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3692981173 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13240 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 14084 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5626 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 4835 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal index 8e5190276..cbe8d6472 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000018] Console: colour dummy device 80x25
-[ 0.000020] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000021] pid_max: default: 32768 minimum: 301
-[ 0.000029] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000030] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000132] hw perfevents: no hardware support available
-[ 0.060034] CPU1: Booted secondary processor
-[ 1.080058] CPU2: failed to come online
-[ 2.100109] CPU3: failed to come online
-[ 2.100111] Brought up 2 CPUs
-[ 2.100112] SMP: Total of 2 processors activated.
-[ 2.100158] devtmpfs: initialized
-[ 2.100486] atomic64_test: passed
-[ 2.100520] regulator-dummy: no parameters
-[ 2.100764] NET: Registered protocol family 16
-[ 2.100855] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.100862] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.101406] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.101409] Serial: AMBA PL011 UART driver
-[ 2.101542] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.101569] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.102150] console [ttyAMA0] enabled
-[ 2.102255] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.102304] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.102356] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.102402] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140243] 3V3: 3300 mV
-[ 2.140289] vgaarb: loaded
-[ 2.140336] SCSI subsystem initialized
-[ 2.140372] libata version 3.00 loaded.
-[ 2.140432] usbcore: registered new interface driver usbfs
-[ 2.140452] usbcore: registered new interface driver hub
-[ 2.140475] usbcore: registered new device driver usb
-[ 2.140509] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140519] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140540] PTP clock support registered
-[ 2.140668] Switched to clocksource arch_sys_counter
-[ 2.141701] NET: Registered protocol family 2
-[ 2.141770] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.141785] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.141801] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.141824] TCP: reno registered
-[ 2.141831] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141842] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141872] NET: Registered protocol family 1
-[ 2.141906] RPC: Registered named UNIX socket transport module.
-[ 2.141917] RPC: Registered udp transport module.
-[ 2.141925] RPC: Registered tcp transport module.
-[ 2.141933] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.141946] PCI: CLS 0 bytes, default 64
-[ 2.142111] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.142194] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.143636] fuse init (API version 7.23)
-[ 2.143718] msgmni has been set to 469
-[ 2.143799] io scheduler noop registered
-[ 2.143835] io scheduler cfq registered (default)
-[ 2.144137] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.144150] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.144161] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.144173] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.144183] pci_bus 0000:00: scanning bus
-[ 2.144193] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.144206] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.144220] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.144247] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.144259] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.144269] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.144280] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.144290] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.144301] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.144312] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.144339] pci_bus 0000:00: fixups for bus
-[ 2.144347] pci_bus 0000:00: bus scan returning with max=00
-[ 2.144358] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.144376] pci 0000:00:00.0: fixup irq: got 33
-[ 2.144384] pci 0000:00:00.0: assigning IRQ 33
-[ 2.144394] pci 0000:00:01.0: fixup irq: got 34
-[ 2.144402] pci 0000:00:01.0: assigning IRQ 34
-[ 2.144413] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.144426] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.144438] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.144451] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.144462] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.144473] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.144485] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.144496] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.144948] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.145137] ata_piix 0000:00:01.0: version 2.13
-[ 2.145148] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.145169] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.145354] scsi0 : ata_piix
-[ 2.145413] scsi1 : ata_piix
-[ 2.145434] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.145446] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.145522] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.145534] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.145547] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.145559] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290714] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290739] ata1.00: configured for UDMA/33
-[ 2.290784] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.290883] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.290917] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.290926] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.290943] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.290996] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.291064] sda: sda1
-[ 2.291152] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.410949] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.410962] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.410980] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.410990] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.411008] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.411020] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411070] usbcore: registered new interface driver usb-storage
-[ 2.411118] mousedev: PS/2 mouse device common for all mice
-[ 2.411225] usbcore: registered new interface driver usbhid
-[ 2.411235] usbhid: USB HID core driver
-[ 2.411260] TCP: cubic registered
-[ 2.411267] NET: Registered protocol family 17
- -[ 2.411619] devtmpfs: mounted
-[ 2.411656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000015] Console: colour dummy device 80x25
+[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000017] pid_max: default: 32768 minimum: 301
+[ 0.000024] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000098] hw perfevents: no hardware support available
+[ 0.060026] CPU1: Booted secondary processor
+[ 1.080051] CPU2: failed to come online
+[ 2.100096] CPU3: failed to come online
+[ 2.100099] Brought up 2 CPUs
+[ 2.100099] SMP: Total of 2 processors activated.
+[ 2.100138] devtmpfs: initialized
+[ 2.100443] atomic64_test: passed
+[ 2.100470] regulator-dummy: no parameters
+[ 2.100693] NET: Registered protocol family 16
+[ 2.100775] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.100781] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.100925] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.100928] Serial: AMBA PL011 UART driver
+[ 2.101044] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.101067] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.101650] console [ttyAMA0] enabled
+[ 2.101714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.101771] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.101798] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140207] 3V3: 3300 mV
+[ 2.140239] vgaarb: loaded
+[ 2.140270] SCSI subsystem initialized
+[ 2.140299] libata version 3.00 loaded.
+[ 2.140331] usbcore: registered new interface driver usbfs
+[ 2.140346] usbcore: registered new interface driver hub
+[ 2.140370] usbcore: registered new device driver usb
+[ 2.140390] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140399] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140417] PTP clock support registered
+[ 2.140503] Switched to clocksource arch_sys_counter
+[ 2.141444] NET: Registered protocol family 2
+[ 2.141497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.141512] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.141527] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.141543] TCP: reno registered
+[ 2.141550] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141561] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.141588] NET: Registered protocol family 1
+[ 2.141628] RPC: Registered named UNIX socket transport module.
+[ 2.141638] RPC: Registered udp transport module.
+[ 2.141647] RPC: Registered tcp transport module.
+[ 2.141655] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.141667] PCI: CLS 0 bytes, default 64
+[ 2.141771] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.141835] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.142859] fuse init (API version 7.23)
+[ 2.142916] msgmni has been set to 469
+[ 2.143149] io scheduler noop registered
+[ 2.143186] io scheduler cfq registered (default)
+[ 2.143405] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.143418] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.143429] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.143442] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.143451] pci_bus 0000:00: scanning bus
+[ 2.143461] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.143473] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.143487] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143514] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.143526] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.143536] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.143547] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.143557] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.143567] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.143578] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.143604] pci_bus 0000:00: fixups for bus
+[ 2.143612] pci_bus 0000:00: bus scan returning with max=00
+[ 2.143623] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.143640] pci 0000:00:00.0: fixup irq: got 33
+[ 2.143648] pci 0000:00:00.0: assigning IRQ 33
+[ 2.143658] pci 0000:00:01.0: fixup irq: got 34
+[ 2.143666] pci 0000:00:01.0: assigning IRQ 34
+[ 2.143676] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.143689] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.143702] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.143715] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.143726] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.143737] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.143748] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.143759] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.144053] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.144214] ata_piix 0000:00:01.0: version 2.13
+[ 2.144224] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.144241] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.144410] scsi0 : ata_piix
+[ 2.144458] scsi1 : ata_piix
+[ 2.144479] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.144492] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.144562] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.144575] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.144587] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.144599] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290528] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290538] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290562] ata1.00: configured for UDMA/33
+[ 2.290599] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.290672] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.290676] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.290693] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.290693] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.290701] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.290789] sda: sda1
+[ 2.290864] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.410776] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.410789] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.410807] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.410817] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.410834] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.410846] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.410894] usbcore: registered new interface driver usb-storage
+[ 2.410940] mousedev: PS/2 mouse device common for all mice
+[ 2.411046] usbcore: registered new interface driver usbhid
+[ 2.411056] usbhid: USB HID core driver
+[ 2.411079] TCP: cubic registered
+[ 2.411086] NET: Registered protocol family 17
+ +[ 2.411396] devtmpfs: mounted
+[ 2.411414] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.447817] udevd[609]: starting version 182
+[ 2.447448] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.532679] random: dd urandom read with 18 bits of entropy available
+[ 2.532422] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.640899] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.640730] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini index 2ab6e4e82..945f8e486 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -121,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -159,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -198,8 +216,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -208,13 +233,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -233,8 +262,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -257,9 +291,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -273,9 +312,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -551,13 +595,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -576,8 +624,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -635,9 +688,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -651,9 +709,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -664,13 +727,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -689,8 +756,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -698,9 +770,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -745,9 +823,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -761,13 +844,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -786,8 +873,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -795,9 +887,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -811,11 +909,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -860,6 +963,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -871,7 +975,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -914,10 +1022,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -998,14 +1111,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1014,13 +1132,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1030,6 +1153,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1100,10 +1224,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1183,17 +1312,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1219,12 +1353,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1232,14 +1372,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1325,14 +1470,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1341,13 +1491,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1356,13 +1511,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1370,11 +1530,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1388,11 +1553,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1406,19 +1576,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1464,14 +1640,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1480,11 +1671,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1494,21 +1690,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1518,12 +1724,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1532,10 +1743,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1545,12 +1761,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1560,26 +1781,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1588,10 +1819,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1599,10 +1835,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1610,21 +1851,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1638,11 +1889,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1653,11 +1909,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1665,10 +1926,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr index 3c2cf37c0..082803b1b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simerr @@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout index 596287bde..25ac82c4f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 11:54:11 -gem5 executing on e104799-lin, pid 641 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:40:47 +gem5 executing on e108600-lin, pid 23116 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3 Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51291805611000 because m5_exit instruction encountered +Exiting @ tick 51327142820000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 3c37d97cb..7cac85e04 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.327140 # Number of seconds simulated -sim_ticks 51327139864000 # Number of ticks simulated -final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.327143 # Number of seconds simulated +sim_ticks 51327142820000 # Number of ticks simulated +final_tick 51327142820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138298 # Simulator instruction rate (inst/s) -host_op_rate 162502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8369157499 # Simulator tick rate (ticks/s) -host_mem_usage 688884 # Number of bytes of host memory used -host_seconds 6132.89 # Real time elapsed on the host -sim_insts 848164321 # Number of instructions simulated -sim_ops 996610207 # Number of ops (including micro ops) simulated +host_inst_rate 147527 # Simulator instruction rate (inst/s) +host_op_rate 173346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8926963197 # Simulator tick rate (ticks/s) +host_mem_usage 681308 # Number of bytes of host memory used +host_seconds 5749.68 # Real time elapsed on the host +sim_insts 848230502 # Number of instructions simulated +sim_ops 996685945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory -system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68386496 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.itb.walker 212864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5673056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 41642312 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory +system.physmem.bytes_read::total 48200872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5673056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5673056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68445056 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68407076 # Number of bytes written to this memory +system.physmem.bytes_written::total 68465636 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3383 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 649748 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6922 # Number of read requests responded to by this memory -system.physmem.num_reads::total 768028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1068539 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 650674 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory +system.physmem.num_reads::total 769104 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1069454 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1071112 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1072027 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 810157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 937750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1332365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 110527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 939091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1333506 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1332766 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1332365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 1333907 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1333506 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 810558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2270516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 768028 # Number of read requests accepted -system.physmem.writeReqs 1071112 # Number of write requests accepted -system.physmem.readBursts 768028 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1071112 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49106944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 46848 # Total number of bytes read from write queue -system.physmem.bytesWritten 68406272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48132008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68407076 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 732 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.itb.walker 4147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2272998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 769104 # Number of read requests accepted +system.physmem.writeReqs 1072027 # Number of write requests accepted +system.physmem.readBursts 769104 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1072027 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 49176064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 46592 # Total number of bytes read from write queue +system.physmem.bytesWritten 68464384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48200872 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68465636 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 728 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 45073 # Per bank write bursts -system.physmem.perBankRdBursts::1 51507 # Per bank write bursts -system.physmem.perBankRdBursts::2 47331 # Per bank write bursts -system.physmem.perBankRdBursts::3 43047 # Per bank write bursts -system.physmem.perBankRdBursts::4 45469 # Per bank write bursts -system.physmem.perBankRdBursts::5 51901 # Per bank write bursts -system.physmem.perBankRdBursts::6 46387 # Per bank write bursts -system.physmem.perBankRdBursts::7 47163 # Per bank write bursts -system.physmem.perBankRdBursts::8 43832 # Per bank write bursts -system.physmem.perBankRdBursts::9 71407 # Per bank write bursts -system.physmem.perBankRdBursts::10 44269 # Per bank write bursts -system.physmem.perBankRdBursts::11 52269 # Per bank write bursts -system.physmem.perBankRdBursts::12 42900 # Per bank write bursts -system.physmem.perBankRdBursts::13 46591 # Per bank write bursts -system.physmem.perBankRdBursts::14 43222 # Per bank write bursts -system.physmem.perBankRdBursts::15 44928 # Per bank write bursts -system.physmem.perBankWrBursts::0 64149 # Per bank write bursts -system.physmem.perBankWrBursts::1 68917 # Per bank write bursts -system.physmem.perBankWrBursts::2 66979 # Per bank write bursts -system.physmem.perBankWrBursts::3 64863 # Per bank write bursts -system.physmem.perBankWrBursts::4 67442 # Per bank write bursts -system.physmem.perBankWrBursts::5 70404 # Per bank write bursts -system.physmem.perBankWrBursts::6 66306 # Per bank write bursts -system.physmem.perBankWrBursts::7 67867 # Per bank write bursts -system.physmem.perBankWrBursts::8 65614 # Per bank write bursts -system.physmem.perBankWrBursts::9 70732 # Per bank write bursts -system.physmem.perBankWrBursts::10 65165 # Per bank write bursts -system.physmem.perBankWrBursts::11 71475 # Per bank write bursts -system.physmem.perBankWrBursts::12 63578 # Per bank write bursts -system.physmem.perBankWrBursts::13 66114 # Per bank write bursts -system.physmem.perBankWrBursts::14 64356 # Per bank write bursts -system.physmem.perBankWrBursts::15 64887 # Per bank write bursts +system.physmem.perBankRdBursts::0 44564 # Per bank write bursts +system.physmem.perBankRdBursts::1 52315 # Per bank write bursts +system.physmem.perBankRdBursts::2 47721 # Per bank write bursts +system.physmem.perBankRdBursts::3 44538 # Per bank write bursts +system.physmem.perBankRdBursts::4 44659 # Per bank write bursts +system.physmem.perBankRdBursts::5 50872 # Per bank write bursts +system.physmem.perBankRdBursts::6 46439 # Per bank write bursts +system.physmem.perBankRdBursts::7 47959 # Per bank write bursts +system.physmem.perBankRdBursts::8 44018 # Per bank write bursts +system.physmem.perBankRdBursts::9 71274 # Per bank write bursts +system.physmem.perBankRdBursts::10 43972 # Per bank write bursts +system.physmem.perBankRdBursts::11 51692 # Per bank write bursts +system.physmem.perBankRdBursts::12 45026 # Per bank write bursts +system.physmem.perBankRdBursts::13 46672 # Per bank write bursts +system.physmem.perBankRdBursts::14 42515 # Per bank write bursts +system.physmem.perBankRdBursts::15 44140 # Per bank write bursts +system.physmem.perBankWrBursts::0 64758 # Per bank write bursts +system.physmem.perBankWrBursts::1 69412 # Per bank write bursts +system.physmem.perBankWrBursts::2 67623 # Per bank write bursts +system.physmem.perBankWrBursts::3 66442 # Per bank write bursts +system.physmem.perBankWrBursts::4 66817 # Per bank write bursts +system.physmem.perBankWrBursts::5 69740 # Per bank write bursts +system.physmem.perBankWrBursts::6 65132 # Per bank write bursts +system.physmem.perBankWrBursts::7 69008 # Per bank write bursts +system.physmem.perBankWrBursts::8 65482 # Per bank write bursts +system.physmem.perBankWrBursts::9 70623 # Per bank write bursts +system.physmem.perBankWrBursts::10 64235 # Per bank write bursts +system.physmem.perBankWrBursts::11 70444 # Per bank write bursts +system.physmem.perBankWrBursts::12 64965 # Per bank write bursts +system.physmem.perBankWrBursts::13 66804 # Per bank write bursts +system.physmem.perBankWrBursts::14 64273 # Per bank write bursts +system.physmem.perBankWrBursts::15 63998 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51327138450500 # Total gap between requests +system.physmem.numWrRetry 34 # Number of times write queue was full causing retry +system.physmem.totGap 51327141408500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 746743 # Read request sizes (log2) +system.physmem.readPktSize::6 747819 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1068539 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 514973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 144 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1069454 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 515353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 203905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,126 +160,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 58973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 471440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.263737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.464196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.749786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207824 44.08% 44.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 122155 25.91% 69.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42779 9.07% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22709 4.82% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14933 3.17% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9495 2.01% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7568 1.61% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6030 1.28% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37947 8.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 471440 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54191 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.158790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 76.596487 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 54185 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 26806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 69842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 65026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 74 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 471870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.306089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.569568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.567780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207742 44.03% 44.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122462 25.95% 69.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 42886 9.09% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22733 4.82% 83.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14982 3.18% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9606 2.04% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7566 1.60% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6003 1.27% 91.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37890 8.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 471870 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 54238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.166341 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 76.651597 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 54233 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54191 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54191 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.723718 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.774638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.948432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40576 74.88% 74.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4593 8.48% 83.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5177 9.55% 92.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1373 2.53% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 420 0.78% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 248 0.46% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 301 0.56% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 130 0.24% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 393 0.73% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 142 0.26% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 38 0.07% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 61 0.11% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 323 0.60% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 40 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.20% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 181 0.33% 99.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 54238 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 54238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.723367 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.775784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.950161 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 40620 74.89% 74.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4585 8.45% 83.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5200 9.59% 92.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1381 2.55% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 413 0.76% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 235 0.43% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 311 0.57% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 127 0.23% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 390 0.72% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 50 0.09% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 65 0.12% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 327 0.60% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 36 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 29 0.05% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.20% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 166 0.31% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54191 # Writes before turning the bus around for reads -system.physmem.totQLat 15195806089 # Total ticks spent queuing -system.physmem.totMemAccLat 29582606089 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3836480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19804.36 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 54238 # Writes before turning the bus around for reads +system.physmem.totQLat 15209667379 # Total ticks spent queuing +system.physmem.totMemAccLat 29616717379 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3841880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19794.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38554.36 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38544.56 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s @@ -288,43 +288,43 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing -system.physmem.readRowHits 579763 # Number of row buffer hits during reads -system.physmem.writeRowHits 784939 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing +system.physmem.readRowHits 580662 # Number of row buffer hits during reads +system.physmem.writeRowHits 785598 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes -system.physmem.avgGap 27908228.00 # Average gap between requests -system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1800088920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 982191375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2947417200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3479286960 # Energy for write commands per rank (pJ) +system.physmem.avgGap 27878049.64 # Average gap between requests +system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1803657240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 984138375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2956722600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3492279360 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235810088180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29712239669250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309697958765 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.451396 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49428932348966 # Time in different power states +system.physmem_0.actBackEnergy 1235640856320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29712388110000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34309704980775 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.451533 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49429181288166 # Time in different power states system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184281028534 # Time in different power states +system.physmem_0.memoryStateTime::ACT 184032075584 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1763997480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 962498625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3037452600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3446848080 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 1763679960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 962325375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3036563400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3439739520 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235330422065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.450284 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states +system.physmem_1.actBackEnergy 1235034526230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712919978500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34309596029865 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.449411 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49430060847495 # Time in different power states system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states +system.physmem_1.memoryStateTime::ACT 183155359005 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -341,30 +341,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225024609 # Number of BP lookups -system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12305268 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158924221 # Number of BTB lookups -system.cpu.branchPred.BTBHits 98148969 # Number of BTB hits +system.cpu.branchPred.lookups 225047911 # Number of BP lookups +system.cpu.branchPred.condPredicted 149825196 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12305756 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158986930 # Number of BTB lookups +system.cpu.branchPred.BTBHits 98148773 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 61.733863 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30878370 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 343644 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6734089 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4745857 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1988232 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 765703 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,89 +394,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 947007 # Table walker walks requested -system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 508020 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 2030 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1046 0.20% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 222 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 147 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 54 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 511600 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 486864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 475438 97.65% 97.65% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7837 1.61% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2530 0.52% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 265 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 545 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 113 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 104 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 16 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 486864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 779668807876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725507 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.522451 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 777433889876 99.71% 99.71% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1160253500 0.15% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 513477500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 201866500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 152233500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 119773500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 32296000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52448000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2569500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 779668807876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155483 90.77% 90.77% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15816 9.23% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171299 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 947007 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 948773 # Table walker walks requested +system.cpu.dtb.walker.walksLong 948773 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15596 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155468 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 437937 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 510836 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2285.186439 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 507265 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 2025 0.40% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1066 0.21% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 145 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 43 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 510836 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 488329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 476828 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7891 1.62% 99.26% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2533 0.52% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 229 0.05% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 568 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 114 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 488329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 779668986876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.725199 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.523523 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 777411937376 99.71% 99.71% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1169683000 0.15% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 513347500 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 208116000 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 157188000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121226500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 32342000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 52541000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2605500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 779668986876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155469 90.88% 90.88% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15596 9.12% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 171065 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 948773 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 947007 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171299 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 948773 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171065 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171299 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1118306 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171065 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1119838 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169398877 # DTB read hits -system.cpu.dtb.read_misses 674798 # DTB read misses -system.cpu.dtb.write_hits 147332912 # DTB write hits -system.cpu.dtb.write_misses 272209 # DTB write misses +system.cpu.dtb.read_hits 169411407 # DTB read hits +system.cpu.dtb.read_misses 675369 # DTB read misses +system.cpu.dtb.write_hits 147344334 # DTB write hits +system.cpu.dtb.write_misses 273404 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 71963 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10047 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170073675 # DTB read accesses -system.cpu.dtb.write_accesses 147605121 # DTB write accesses +system.cpu.dtb.perms_faults 69388 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170086776 # DTB read accesses +system.cpu.dtb.write_accesses 147617738 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316731789 # DTB hits -system.cpu.dtb.misses 947007 # DTB misses -system.cpu.dtb.accesses 317678796 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 316755741 # DTB hits +system.cpu.dtb.misses 948773 # DTB misses +system.cpu.dtb.accesses 317704514 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,66 +504,66 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 162102 # Table walker walks requested -system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143046 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 588 0.41% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 94 0.07% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 159 0.11% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 224 0.16% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 44 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144186 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139421 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28788.855337 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136254 97.73% 97.73% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 690 0.49% 98.22% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2101 1.51% 99.73% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 136 0.10% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 47 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 162181 # Table walker walks requested +system.cpu.itb.walker.walksLong 162181 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1496 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 120027 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17971 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144210 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1137.740101 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9342.723838 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143038 99.19% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 619 0.43% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 86 0.06% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 189 0.13% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 221 0.15% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 35 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144210 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 139494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29066.088864 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 136396 97.78% 97.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 707 0.51% 98.29% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1985 1.42% 99.71% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 151 0.11% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 171 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 34 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139421 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 680881393568 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.947864 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.222600 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 35543211356 5.22% 5.22% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 645294358712 94.77% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 43207500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 580000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 36000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 680881393568 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120022 98.78% 98.78% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1483 1.22% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 121505 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 139494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 676589720772 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.947980 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.222341 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 35236838356 5.21% 5.21% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 641313182416 94.79% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 39010000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 686000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 676589720772 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 120027 98.77% 98.77% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1496 1.23% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 121523 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162102 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162102 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162181 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 162181 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121505 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 121505 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283607 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357007788 # ITB inst hits -system.cpu.itb.inst_misses 162102 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121523 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 121523 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 283704 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 357038073 # ITB inst hits +system.cpu.itb.inst_misses 162181 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -574,21 +572,21 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52848 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 357344 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357169890 # ITB inst accesses -system.cpu.itb.hits 357007788 # DTB hits -system.cpu.itb.misses 162102 # DTB misses -system.cpu.itb.accesses 357169890 # DTB accesses +system.cpu.itb.inst_accesses 357200254 # ITB inst accesses +system.cpu.itb.hits 357038073 # DTB hits +system.cpu.itb.misses 162181 # DTB misses +system.cpu.itb.accesses 357200254 # DTB accesses system.cpu.numPwrStateTransitions 32228 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3134631677.512784 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60494120707.852806 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state @@ -600,139 +598,139 @@ system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1631144067 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 815687968559 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1631385344 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646877625 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1002761410 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225047911 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133773000 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 898188451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26266186 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3841497 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30548 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8722394 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1026877 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1034 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 356664988 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6247416 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 47904 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1571821519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.149310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1014113227 64.52% 64.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 214297646 13.63% 78.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70312417 4.47% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 273098229 17.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1571821519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137949 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.614669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526332322 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 552246914 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434136742 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49729183 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9376358 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33563941 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3814299 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1086052117 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29449193 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9376358 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571289803 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66024800 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 371545208 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 438989582 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 114595768 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1065754363 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6907795 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5097238 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 334375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 639506 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 63573833 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20465 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1013430764 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1640279788 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259572075 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1474026 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 947250209 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 66180552 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26901106 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23243208 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101784051 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173837388 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150829276 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9883117 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9014861 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1030729252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27201158 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1045808358 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3377405 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 61244461 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 34071399 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 308913 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1571821519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.665348 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.919634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 924230442 58.80% 58.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 334342298 21.27% 80.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234750151 14.93% 95.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72048277 4.58% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6430828 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19523 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1571821519 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 667 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44277065 26.88% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62625013 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57691324 35.03% 35.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100152 0.06% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26730 0.02% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 622 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44285841 26.89% 62.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62576075 38.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 720295550 68.88% 68.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2531326 0.24% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122856 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 720343690 68.88% 68.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2530628 0.24% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122776 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued @@ -755,100 +753,100 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 119220 0.01% 69.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 119191 0.01% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173490543 16.59% 85.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149201098 14.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued -system.cpu.iq.rate 0.641106 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1045808358 # Type of FU issued +system.cpu.iq.rate 0.641055 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164680744 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157467 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3829023509 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118377930 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1027460456 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2472874 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 938610 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909796 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1208933693 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1555398 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4274316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14173969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14495 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 142953 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6059351 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2526453 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1440750 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9376358 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7004216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6913167 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1058165202 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22818732 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57696 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6782714 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3464744 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5492402 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8957146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1034225316 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169386893 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10574140 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173837388 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150829276 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22819114 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57849 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6781828 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 142953 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3462734 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5495013 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8957747 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1034296660 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169399584 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10573772 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 235018 # number of nop insts executed -system.cpu.iew.exec_refs 316715121 # number of memory reference insts executed -system.cpu.iew.exec_branches 196182084 # Number of branches executed -system.cpu.iew.exec_stores 147328228 # Number of stores executed -system.cpu.iew.exec_rate 0.634049 # Inst execution rate -system.cpu.iew.wb_sent 1029119140 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back -system.cpu.iew.wb_producers 437817967 # num instructions producing a value -system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value -system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle +system.cpu.iew.exec_nop 234792 # number of nop insts executed +system.cpu.iew.exec_refs 316739180 # number of memory reference insts executed +system.cpu.iew.exec_branches 196198672 # Number of branches executed +system.cpu.iew.exec_stores 147339596 # Number of stores executed +system.cpu.iew.exec_rate 0.633999 # Inst execution rate +system.cpu.iew.wb_sent 1029187818 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1028370252 # cumulative count of insts written-back +system.cpu.iew.wb_producers 437853372 # num instructions producing a value +system.cpu.iew.wb_consumers 708400240 # num instructions consuming a value +system.cpu.iew.wb_rate 0.630366 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618088 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51884426 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26892245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8549021 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1559762540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.638999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273827 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1047991029 67.19% 67.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288035307 18.47% 85.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120100080 7.70% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36659789 2.35% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28506606 1.83% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13942789 0.89% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8651847 0.55% 98.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4181084 0.27% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11694009 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle -system.cpu.commit.committedInsts 848164321 # Number of instructions committed -system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1559762540 # Number of insts commited each cycle +system.cpu.commit.committedInsts 848230502 # Number of instructions committed +system.cpu.commit.committedOps 996685945 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304407284 # Number of memory references committed -system.cpu.commit.loads 159650119 # Number of loads committed -system.cpu.commit.membars 6926917 # Number of memory barriers committed -system.cpu.commit.branches 189306416 # Number of branches committed -system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions. -system.cpu.commit.int_insts 915651510 # Number of committed integer instructions. -system.cpu.commit.function_calls 25281717 # Number of function calls committed. +system.cpu.commit.refs 304433343 # Number of memory references committed +system.cpu.commit.loads 159663418 # Number of loads committed +system.cpu.commit.membars 6927415 # Number of memory barriers committed +system.cpu.commit.branches 189324067 # Number of branches committed +system.cpu.commit.fp_insts 898712 # Number of committed floating point instructions. +system.cpu.commit.int_insts 915721971 # Number of committed integer instructions. +system.cpu.commit.function_calls 25285288 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 689843263 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2149527 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98159 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 689893101 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2149376 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98151 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -875,541 +873,540 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159663418 16.02% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144769925 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction -system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2588836134 # The number of ROB reads -system.cpu.rob.rob_writes 2108972650 # The number of ROB writes -system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 848164321 # Number of Instructions Simulated -system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.923146 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519981 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads -system.cpu.int_regfile_writes 731349757 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads -system.cpu.fp_regfile_writes 780384 # number of floating regfile writes -system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads -system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes -system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads -system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9706309 # number of replacements +system.cpu.commit.op_class_0::total 996685945 # Class of committed instruction +system.cpu.commit.bw_lim_events 11694009 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2589097882 # The number of ROB reads +system.cpu.rob.rob_writes 2109106528 # The number of ROB writes +system.cpu.timesIdled 8171713 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59563825 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101022900419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 848230502 # Number of Instructions Simulated +system.cpu.committedOps 996685945 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.923281 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.923281 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519945 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519945 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1223820104 # number of integer regfile reads +system.cpu.int_regfile_writes 731394790 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462803 # number of floating regfile reads +system.cpu.fp_regfile_writes 780644 # number of floating regfile writes +system.cpu.cc_regfile_reads 225050166 # number of cc regfile reads +system.cpu.cc_regfile_writes 225684828 # number of cc regfile writes +system.cpu.misc_regfile_reads 2558325337 # number of misc regfile reads +system.cpu.misc_regfile_writes 26931155 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9701158 # number of replacements system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 283187639 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9701670 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.189577 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128244124 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits -system.cpu.dcache.overall_hits::total 276127624 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11252664 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1170750 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1170750 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1233990 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1233990 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses -system.cpu.dcache.overall_misses::total 23239410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 444283559827 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52343559973 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 52343559973 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 139496788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548503 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1548503 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080666 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756053 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.756053 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792311 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.792311 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1237018765 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1237018765 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 147199934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147199934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128255410 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128255410 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377663 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377663 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 323814 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 323814 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295431 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3295431 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3691256 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3691256 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 275779158 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 275779158 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 276156821 # number of overall hits +system.cpu.dcache.overall_hits::total 276156821 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9580915 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9580915 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11254027 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11254027 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1170464 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1170464 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1233639 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1233639 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 446709 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 446709 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 22068581 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 22068581 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 23239045 # number of overall misses +system.cpu.dcache.overall_misses::total 23239045 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 168767240000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 444298934810 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52375248289 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 52375248289 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6883962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6883962000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 380500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 380500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 665441423099 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 665441423099 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 665441423099 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 665441423099 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156780849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156780849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 139509437 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 139509437 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548127 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1548127 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557453 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1557453 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3742140 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3742140 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691264 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3691264 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 297847739 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 297847739 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 299395866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 299395866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061110 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061110 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080669 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080669 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756052 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.756052 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792087 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.792087 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119373 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119373 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.074093 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074093 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.077620 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.077620 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30153.339859 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28634.628622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32224409 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1601607 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.120048 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks -system.cpu.dcache.writebacks::total 7511281 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4454269 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9249122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9249122 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2003542 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163937 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1163937 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226860 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1226860 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7504086 # number of writebacks +system.cpu.dcache.writebacks::total 7504086 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4456599 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4456599 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9250788 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9250788 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7056 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 7056 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219268 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 219268 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13714443 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13714443 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13714443 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13714443 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5124316 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5124316 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8354138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9517786 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9517786 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84965736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84965736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77538140437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77538140437 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23685156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23685156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50670413473 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014363 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751653 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751653 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787733 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787733 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84959954500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84959954500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77558080846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77558080846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23723735000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23723735000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50708992789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50708992789 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3202218000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3202218000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 372500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 372500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 213227028135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 236950763135 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192056000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192056000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192056000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192056000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032685 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032685 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751649 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751649 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787557 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787557 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060778 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060778 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 15141033 # number of replacements -system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028048 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028048 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 15134592 # number of replacements +system.cpu.icache.tags.tagsinuse 511.928988 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 340756209 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15135104 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.514296 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.928988 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340718799 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340718799 # number of overall hits -system.cpu.icache.overall_hits::total 340718799 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15894345 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15894345 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15894345 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15894345 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15894345 # number of overall misses -system.cpu.icache.overall_misses::total 15894345 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214960438379 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214960438379 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214960438379 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214960438379 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214960438379 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214960438379 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356613144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356613144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356613144 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356613144 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356613144 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356613144 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044570 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044570 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044570 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044570 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044570 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044570 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13524.334496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13524.334496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13524.334496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13524.334496 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 23721 # 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15887482 # number of overall misses +system.cpu.icache.overall_misses::total 15887482 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214918228873 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214918228873 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214918228873 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214918228873 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214918228873 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 356643691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 356643691 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 356643691 # 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average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785050 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785050 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039465 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039465 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407265 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407265 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030044 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030044 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 50407203 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25570213 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1618708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23266675 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43666 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1963403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1963403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15141775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6525421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226860 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45466959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29342845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 722067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1919121 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77450992 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1938426848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023681310 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2369528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6237568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2970715254 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1868325 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27924144 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156198 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8573574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15134592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2391693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43548 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1963232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1963232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15135331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1333247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226583 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45447628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29327152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 726647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1928826 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77430253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1937602080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1022907422 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2405600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6328296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2969243398 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1852603 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 72285944 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 27912596 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.024958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.155996 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27225372 97.50% 97.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 698772 2.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27215961 97.50% 97.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 696635 2.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27924144 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48365955497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27912596 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48339894491 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1497386 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1459384 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22733591738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13401353655 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 426266814 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1138134788 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40299 # Transaction distribution -system.iobus.trans_dist::ReadResp 40299 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40293 # Transaction distribution +system.iobus.trans_dist::ReadResp 40293 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1620,11 +1618,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1639,16 +1637,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41885000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41884500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 345000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1666,75 +1664,75 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25104500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25117000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36501000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567323274 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115453 # number of replacements +system.iocache.tags.tagsinuse 10.423128 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13098782503000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878927 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039605 # Number of tag accesses +system.iocache.tags.data_accesses 1039605 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses -system.iocache.demand_misses::total 115518 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115472 # number of demand (read+write) misses +system.iocache.demand_misses::total 115512 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115478 # number of overall misses -system.iocache.overall_misses::total 115518 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115472 # number of overall misses +system.iocache.overall_misses::total 115512 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5076000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1670063987 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1675139987 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13414774287 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13414774287 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5427000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15084838274 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15090265274 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5427000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15084838274 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15090265274 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115472 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115512 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115472 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115512 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1748,53 +1746,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189388.353533 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135675 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130638.074607 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135675 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130638.074607 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33964 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3510 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.676353 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115472 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115512 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115472 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115512 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3226000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229663987 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1232889987 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076516803 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8076516803 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3427000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9306180790 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9309607790 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3427000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9306180790 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9309607790 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1808,88 +1806,89 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 410008 # Transaction distribution +system.membus.trans_dist::ReadResp 411033 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution -system.membus.trans_dist::CleanEvict 192763 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1069454 # Transaction distribution +system.membus.trans_dist::CleanEvict 193565 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34895 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 394295 # Transaction distribution -system.membus.trans_dist::ReadExResp 394295 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 355036 # Transaction distribution -system.membus.trans_dist::InvalidateReq 605480 # Transaction distribution +system.membus.trans_dist::ReadExReq 394310 # Transaction distribution +system.membus.trans_dist::ReadExResp 394310 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 356061 # Transaction distribution +system.membus.trans_dist::InvalidateReq 606112 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3207653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3337273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3575172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3212019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3341639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237917 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237917 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3579556 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109271756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109441726 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7267328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7267328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 116709054 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2596 # Total snoops (count) -system.membus.snoop_fanout::samples 2739791 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109397260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109567230 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7269248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7269248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 116836478 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2560 # Total snoops (count) +system.membus.snoopTraffic 163328 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2743103 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2739791 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2743103 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2739791 # Request fanout histogram -system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2743103 # Request fanout histogram +system.membus.reqLayer0.occupancy 103939500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5573000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7172212711 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4075256665 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44789891 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1932,29 +1931,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal index 1b50f034a..3c0eb417b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal @@ -31,136 +31,136 @@ [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000022] Console: colour dummy device 80x25
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000021] Console: colour dummy device 80x25
[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000025] pid_max: default: 32768 minimum: 301
[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000160] hw perfevents: no hardware support available
-[ 1.060067] CPU1: failed to come online
-[ 2.080129] CPU2: failed to come online
-[ 3.100191] CPU3: failed to come online
-[ 3.100194] Brought up 1 CPUs
-[ 3.100195] SMP: Total of 1 processors activated.
-[ 3.100251] devtmpfs: initialized
-[ 3.100700] atomic64_test: passed
-[ 3.100743] regulator-dummy: no parameters
-[ 3.101166] NET: Registered protocol family 16
-[ 3.101292] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101301] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.102003] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.102008] Serial: AMBA PL011 UART driver
-[ 3.102194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.102227] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102794] console [ttyAMA0] enabled
-[ 3.102873] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102904] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.102936] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.102965] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130500] 3V3: 3300 mV
-[ 3.130542] vgaarb: loaded
-[ 3.130589] SCSI subsystem initialized
-[ 3.130626] libata version 3.00 loaded.
-[ 3.130670] usbcore: registered new interface driver usbfs
-[ 3.130688] usbcore: registered new interface driver hub
-[ 3.130719] usbcore: registered new device driver usb
-[ 3.130744] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130753] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130772] PTP clock support registered
-[ 3.130888] Switched to clocksource arch_sys_counter
-[ 3.131885] NET: Registered protocol family 2
-[ 3.131959] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131977] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131999] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.132014] TCP: reno registered
-[ 3.132021] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132036] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132076] NET: Registered protocol family 1
-[ 3.132127] RPC: Registered named UNIX socket transport module.
-[ 3.132137] RPC: Registered udp transport module.
-[ 3.132145] RPC: Registered tcp transport module.
-[ 3.132153] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132165] PCI: CLS 0 bytes, default 64
-[ 3.132312] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.132411] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.133969] fuse init (API version 7.23)
-[ 3.134047] msgmni has been set to 469
-[ 3.136178] io scheduler noop registered
-[ 3.136228] io scheduler cfq registered (default)
-[ 3.136665] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.136678] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.136689] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.136702] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.136712] pci_bus 0000:00: scanning bus
-[ 3.136722] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.136735] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.136749] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136786] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.136798] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.136809] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.136819] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.136830] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.136841] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136885] pci_bus 0000:00: fixups for bus
-[ 3.136893] pci_bus 0000:00: bus scan returning with max=00
-[ 3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.136925] pci 0000:00:00.0: fixup irq: got 33
-[ 3.136933] pci 0000:00:00.0: assigning IRQ 33
-[ 3.136944] pci 0000:00:01.0: fixup irq: got 34
-[ 3.136952] pci 0000:00:01.0: assigning IRQ 34
-[ 3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.137002] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.137014] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.137025] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.137036] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.137048] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.137735] ata_piix 0000:00:01.0: version 2.13
-[ 3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.137770] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.138035] scsi0 : ata_piix
-[ 3.138128] scsi1 : ata_piix
-[ 3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.138306] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290924] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290951] ata1.00: configured for UDMA/33
-[ 3.291001] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.291104] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.291128] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.291165] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.291174] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.291193] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291307] sda: sda1
-[ 3.291413] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.411182] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.411195] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.411215] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.411225] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411245] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411257] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411320] usbcore: registered new interface driver usb-storage
-[ 3.411372] mousedev: PS/2 mouse device common for all mice
-[ 3.411510] usbcore: registered new interface driver usbhid
-[ 3.411519] usbhid: USB HID core driver
-[ 3.411550] TCP: cubic registered
-[ 3.411558] NET: Registered protocol family 17
- -[ 3.411924] devtmpfs: mounted
-[ 3.411972] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000147] hw perfevents: no hardware support available
+[ 1.060066] CPU1: failed to come online
+[ 2.080127] CPU2: failed to come online
+[ 3.100188] CPU3: failed to come online
+[ 3.100191] Brought up 1 CPUs
+[ 3.100192] SMP: Total of 1 processors activated.
+[ 3.100247] devtmpfs: initialized
+[ 3.100685] atomic64_test: passed
+[ 3.100727] regulator-dummy: no parameters
+[ 3.101141] NET: Registered protocol family 16
+[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.101638] Serial: AMBA PL011 UART driver
+[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102416] console [ttyAMA0] enabled
+[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130494] 3V3: 3300 mV
+[ 3.130534] vgaarb: loaded
+[ 3.130580] SCSI subsystem initialized
+[ 3.130617] libata version 3.00 loaded.
+[ 3.130659] usbcore: registered new interface driver usbfs
+[ 3.130676] usbcore: registered new interface driver hub
+[ 3.130707] usbcore: registered new device driver usb
+[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130759] PTP clock support registered
+[ 3.130873] Switched to clocksource arch_sys_counter
+[ 3.131846] NET: Registered protocol family 2
+[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131975] TCP: reno registered
+[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132036] NET: Registered protocol family 1
+[ 3.132085] RPC: Registered named UNIX socket transport module.
+[ 3.132095] RPC: Registered udp transport module.
+[ 3.132103] RPC: Registered tcp transport module.
+[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132123] PCI: CLS 0 bytes, default 64
+[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.133901] fuse init (API version 7.23)
+[ 3.133978] msgmni has been set to 469
+[ 3.136097] io scheduler noop registered
+[ 3.136147] io scheduler cfq registered (default)
+[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.136562] pci_bus 0000:00: scanning bus
+[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136734] pci_bus 0000:00: fixups for bus
+[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
+[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
+[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
+[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
+[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
+[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.137572] ata_piix 0000:00:01.0: version 2.13
+[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.137866] scsi0 : ata_piix
+[ 3.137956] scsi1 : ata_piix
+[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290935] ata1.00: configured for UDMA/33
+[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.291287] sda: sda1
+[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.411304] usbcore: registered new interface driver usb-storage
+[ 3.411354] mousedev: PS/2 mouse device common for all mice
+[ 3.411491] usbcore: registered new interface driver usbhid
+[ 3.411501] usbhid: USB HID core driver
+[ 3.411531] TCP: cubic registered
+[ 3.411538] NET: Registered protocol family 17
+ +[ 3.411900] devtmpfs: mounted
+[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.450398] udevd[607]: starting version 182
+[ 3.450359] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.533417] random: dd urandom read with 19 bits of entropy available
+[ 3.543431] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
-Configuring network interfaces... [ 3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
udhcpc (v1.21.1) started
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini index 78dc4998c..d912070c6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -168,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -192,9 +219,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -208,9 +240,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -246,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -305,9 +351,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -321,9 +372,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -334,13 +390,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -359,8 +419,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -368,9 +433,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -415,9 +486,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -431,13 +507,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -456,8 +536,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -465,9 +550,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -481,11 +572,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -501,11 +597,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -520,10 +621,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -604,14 +710,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -620,13 +731,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -636,6 +752,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -706,10 +823,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -789,17 +911,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -825,12 +952,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -838,14 +971,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -931,14 +1069,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -947,13 +1090,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -962,13 +1110,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -976,11 +1129,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -994,11 +1152,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1012,19 +1175,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1070,14 +1239,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1086,11 +1270,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1100,21 +1289,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1124,12 +1323,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1138,10 +1342,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1151,12 +1360,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1166,26 +1380,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1194,10 +1418,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1205,10 +1434,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1216,21 +1450,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1244,11 +1488,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1259,11 +1508,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1271,10 +1525,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json index 28d4955ee..bad452cca 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json @@ -6,8 +6,9 @@ "mmap_using_noreserve": false, "kernel_addr_check": true, "highest_el_is_64": false, - "kernel": "/work/gem5/dist/binaries/vmlinux.aarch64.20140821", + "kernel": "/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821", "iobus": { + "forward_latency": 1, "slave": { "peer": [ "system.bridge.master", @@ -19,8 +20,11 @@ "role": "SLAVE" }, "name": "iobus", - "forward_latency": 1, + "p_state_clk_gate_min": 1000, + "p_state_clk_gate_bins": 20, + "cxx_class": "NoncoherentXBar", "clk_domain": "system.clk_domain", + "power_model": null, "width": 16, "eventq_index": 0, "master": { @@ -55,18 +59,22 @@ "role": "MASTER" }, "response_latency": 2, - "cxx_class": "NoncoherentXBar", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.iobus", "type": "NoncoherentXBar", "use_default_range": false, "frontend_latency": 2 }, "symbolfile": "", - "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh", + "readfile": "/work/curdun01/gem5-external.hg/tests/testing/../halt.sh", "have_large_asid_64": false, + "thermal_model": null, "phys_addr_range_64": 40, - "have_lpae": false, + "work_begin_exit_count": 0, + "have_lpae": true, "cxx_class": "LinuxArmSystem", + "work_begin_cpu_id_exit": -1, "load_offset": 2147483648, "vncserver": { "name": "vncserver", @@ -79,9 +87,41 @@ "port": 5900 }, "multi_proc": true, + "bridge": { + "ranges": [ + "788529152:805306367", + "721420288:725614591", + "805306368:1073741823", + "1073741824:1610612735", + "402653184:469762047", + "469762048:536870911" + ], + "slave": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "name": "bridge", + "p_state_clk_gate_min": 1000, + "p_state_clk_gate_bins": 20, + "cxx_class": "Bridge", + "req_size": 16, + "clk_domain": "system.clk_domain", + "power_model": null, + "delay": 50000, + "eventq_index": 0, + "master": { + "peer": "system.iobus.slave[0]", + "role": "MASTER" + }, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "path": "system.bridge", + "resp_size": 16, + "type": "Bridge" + }, "early_kernel_symbols": false, "panic_on_oops": true, - "dtb_filename": "/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb", + "dtb_filename": "/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb", "panic_on_panic": true, "enable_context_switch_stats_dump": false, "work_begin_ckpt_count": 0, @@ -103,52 +143,64 @@ ], "realview": { "hdlcd": { - "vnc": "system.vncserver", - "pxl_clk": "system.realview.dcc.osc_pxl", - "name": "hdlcd", - "workaround_dma_line_count": true, - "amba_id": 1314816, "pio": { "peer": "system.iobus.master[6]", "role": "SLAVE" }, + "system": "system", + "cxx_class": "HDLcd", + "enable_capture": true, + "pio_addr": 721420288, + "pixel_chunk": 32, "pio_latency": 10000, "clk_domain": "system.clk_domain", - "system": "system", - "gic": "system.realview.gic", "int_num": 117, + "gic": "system.realview.gic", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "eventq_index": 0, + "pxl_clk": "system.realview.dcc.osc_pxl", + "type": "HDLcd", + "vnc": "system.vncserver", + "p_state_clk_gate_min": 1000, + "power_model": null, + "workaround_dma_line_count": true, "pixel_buffer_size": 2048, - "cxx_class": "HDLcd", - "enable_capture": true, "path": "system.realview.hdlcd", - "pio_addr": 721420288, "workaround_swap_rb": true, - "type": "HDLcd", - "pixel_chunk": 32, "dma": { "peer": "system.membus.slave[0]", "role": "MASTER" - } + }, + "name": "hdlcd", + "p_state_clk_gate_bins": 20, + "amba_id": 1314816 }, "mmc_fake": { + "p_state_clk_gate_bins": 20, "name": "mmc_fake", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[21]", "role": "SLAVE" }, "amba_id": 0, "ignore_access": false, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "cxx_class": "AmbaFake", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.mmc_fake", "pio_addr": 470089728, "type": "AmbaFake" }, "rtc": { + "p_state_clk_gate_min": 1000, + "p_state_clk_gate_bins": 20, "name": "rtc", "int_delay": 100000, "pio": { @@ -156,31 +208,39 @@ "role": "SLAVE" }, "amba_id": 3412017, - "time": "Thu Jan 1 00:00:00 2009", + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "gic": "system.realview.gic", "int_num": 36, "eventq_index": 0, + "time": "Thu Jan 1 00:00:00 2009", "cxx_class": "PL031", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.rtc", "pio_addr": 471269376, "type": "PL031" }, "watchdog_fake": { + "p_state_clk_gate_bins": 20, "name": "watchdog_fake", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[17]", "role": "SLAVE" }, "amba_id": 0, "ignore_access": false, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "cxx_class": "AmbaFake", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.watchdog_fake", "pio_addr": 470745088, "type": "AmbaFake" @@ -188,36 +248,46 @@ "vgic": { "system": "system", "name": "vgic", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.membus.master[3]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, + "cxx_class": "VGic", "clk_domain": "system.clk_domain", - "ppint": 25, + "power_model": null, "hv_addr": 738213888, "gic": "system.realview.gic", "platform": "system.realview", "vcpu_addr": 738222080, "eventq_index": 0, - "cxx_class": "VGic", + "ppint": 25, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.vgic", "type": "VGic", "pio_delay": 10000 }, "cxx_class": "RealView", "uart3_fake": { + "p_state_clk_gate_bins": 20, "name": "uart3_fake", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[15]", "role": "SLAVE" }, "amba_id": 0, "ignore_access": false, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "cxx_class": "AmbaFake", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.uart3_fake", "pio_addr": 470548480, "type": "AmbaFake" @@ -225,101 +295,126 @@ "realview_io": { "proc_id1": 335544320, "name": "realview_io", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[1]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, + "cxx_class": "RealViewCtrl", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", - "eventq_index": 0, - "cxx_class": "RealViewCtrl", "proc_id0": 335544320, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.realview_io", "idreg": 35979264, "type": "RealViewCtrl", "pio_addr": 469827584 }, "l2x0_fake": { - "system": "system", - "ret_data8": 255, - "name": "l2x0_fake", - "warn_access": "", "pio": { "peer": "system.iobus.master[12]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 4095, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.realview.l2x0_fake", "pio_addr": 739246080, + "update_data": false, + "warn_access": "", + "pio_latency": 100000, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 1000, + "power_model": null, + "ret_data32": 4294967295, + "path": "system.realview.l2x0_fake", + "ret_data16": 65535, + "ret_data8": 255, + "name": "l2x0_fake", + "ret_bad_addr": false, + "pio_size": 4095, + "p_state_clk_gate_bins": 20 }, "uart1_fake": { + "p_state_clk_gate_bins": 20, "name": "uart1_fake", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[13]", "role": "SLAVE" }, "amba_id": 0, "ignore_access": false, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "cxx_class": "AmbaFake", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.uart1_fake", "pio_addr": 470417408, "type": "AmbaFake" }, "usb_fake": { - "system": "system", - "ret_data8": 255, - "name": "usb_fake", - "warn_access": "", "pio": { "peer": "system.iobus.master[20]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 131071, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.realview.usb_fake", "pio_addr": 452984832, + "update_data": false, + "warn_access": "", + "pio_latency": 100000, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 1000, + "power_model": null, + "ret_data32": 4294967295, + "path": "system.realview.usb_fake", + "ret_data16": 65535, + "ret_data8": 255, + "name": "usb_fake", + "ret_bad_addr": false, + "pio_size": 131071, + "p_state_clk_gate_bins": 20 }, "system": "system", "local_cpu_timer": { "int_num_watchdog": 30, "name": "local_cpu_timer", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.membus.master[4]", "role": "SLAVE" }, - "int_num_timer": 29, + "p_state_clk_gate_bins": 20, + "cxx_class": "CpuLocalTimer", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "gic": "system.realview.gic", + "int_num_timer": 29, "eventq_index": 0, - "cxx_class": "CpuLocalTimer", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.local_cpu_timer", "pio_addr": 738721792, "type": "CpuLocalTimer" @@ -336,40 +431,51 @@ "type": "GenericTimer" }, "gic": { + "gem5_extensions": true, "it_lines": 128, + "dist_pio_delay": 10000, "name": "gic", + "p_state_clk_gate_min": 1000, "dist_addr": 738201600, + "p_state_clk_gate_bins": 20, "cpu_pio_delay": 10000, - "dist_pio_delay": 10000, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "cpu_addr": 738205696, "platform": "system.realview", "int_latency": 10000, "eventq_index": 0, "cxx_class": "Pl390", + "p_state_clk_gate_max": 1000000000000, + "path": "system.realview.gic", "pio": { "peer": "system.membus.master[2]", "role": "SLAVE" }, - "path": "system.realview.gic", "type": "Pl390" }, "timer1": { + "p_state_clk_gate_bins": 20, "name": "timer1", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[4]", "role": "SLAVE" }, "amba_id": 1316868, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "clock0": 1000000, "clock1": 1000000, "gic": "system.realview.gic", "eventq_index": 0, "cxx_class": "Sp804", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.timer1", "int_num0": 35, "int_num1": 35, @@ -377,20 +483,25 @@ "pio_addr": 470941696 }, "timer0": { + "p_state_clk_gate_bins": 20, "name": "timer0", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[3]", "role": "SLAVE" }, "amba_id": 1316868, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "clock0": 1000000, "clock1": 1000000, "gic": "system.realview.gic", "eventq_index": 0, "cxx_class": "Sp804", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.timer0", "int_num0": 34, "int_num1": 34, @@ -398,18 +509,23 @@ "pio_addr": 470876160 }, "uart2_fake": { + "p_state_clk_gate_bins": 20, "name": "uart2_fake", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[14]", "role": "SLAVE" }, "amba_id": 0, "ignore_access": false, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "cxx_class": "AmbaFake", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.uart2_fake", "pio_addr": 470482944, "type": "AmbaFake" @@ -417,15 +533,20 @@ "eventq_index": 0, "energy_ctrl": { "name": "energy_ctrl", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[22]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, + "cxx_class": "EnergyCtrl", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, - "cxx_class": "EnergyCtrl", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.energy_ctrl", "dvfs_handler": "system.dvfs_handler", "type": "EnergyCtrl", @@ -433,6 +554,8 @@ }, "type": "RealView", "pci_host": { + "p_state_clk_gate_min": 1000, + "default_p_state": "UNDEFINED", "conf_size": 268435456, "name": "pci_host", "conf_device_bits": 12, @@ -440,55 +563,68 @@ "peer": "system.iobus.master[2]", "role": "SLAVE" }, + "p_state_clk_gate_bins": 20, "conf_base": 805306368, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "pci_dma_base": 0, "platform": "system.realview", "eventq_index": 0, "cxx_class": "GenericPciHost", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.pci_host", "pci_pio_base": 788529152, "type": "GenericPciHost", "pci_mem_base": 0 }, "lan_fake": { - "system": "system", - "ret_data8": 255, - "name": "lan_fake", - "warn_access": "", "pio": { "peer": "system.iobus.master[19]", "role": "SLAVE" }, - "ret_bad_addr": false, - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 65535, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.realview.lan_fake", "pio_addr": 436207616, + "update_data": false, + "warn_access": "", + "pio_latency": 100000, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 1000, + "power_model": null, + "ret_data32": 4294967295, + "path": "system.realview.lan_fake", + "ret_data16": 65535, + "ret_data8": 255, + "name": "lan_fake", + "ret_bad_addr": false, + "pio_size": 65535, + "p_state_clk_gate_bins": 20 }, "aaci_fake": { + "p_state_clk_gate_bins": 20, "name": "aaci_fake", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[18]", "role": "SLAVE" }, "amba_id": 0, "ignore_access": false, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "cxx_class": "AmbaFake", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.aaci_fake", "pio_addr": 470024192, "type": "AmbaFake" @@ -523,10 +659,6 @@ "freq": 20000, "type": "RealViewOsc" }, - "type": "SubSystem", - "eventq_index": 0, - "cxx_class": "SubSystem", - "path": "system.realview.mcc", "osc_clcd": { "position": 0, "name": "osc_clcd", @@ -541,6 +673,24 @@ "freq": 42105, "type": "RealViewOsc" }, + "thermal_domain": null, + "eventq_index": 0, + "cxx_class": "SubSystem", + "path": "system.realview.mcc", + "temp_crtl": { + "system": "system", + "position": 0, + "name": "temp_crtl", + "parent": "system.realview.realview_io", + "dcc": 0, + "site": 0, + "eventq_index": 0, + "cxx_class": "RealViewTemperatureSensor", + "device": 0, + "path": "system.realview.mcc.temp_crtl", + "type": "RealViewTemperatureSensor" + }, + "type": "SubSystem", "osc_system_bus": { "position": 0, "name": "osc_system_bus", @@ -572,6 +722,7 @@ "freq": 25000, "type": "RealViewOsc" }, + "thermal_domain": null, "osc_sys": { "position": 0, "name": "osc_sys", @@ -652,12 +803,17 @@ "range": "402653184:436207615", "latency": 30000, "name": "vram", + "p_state_clk_gate_min": 1000, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "73.000000", "conf_table_reported": false, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.vram", "null": false, "type": "SimpleMemory", @@ -671,12 +827,17 @@ "range": "0:67108863", "latency": 30000, "name": "nvmem", + "p_state_clk_gate_min": 1000, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "73.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.nvmem", "null": false, "type": "SimpleMemory", @@ -687,54 +848,66 @@ "in_addr_map": true }, "clcd": { - "dma": { - "peer": "system.iobus.slave[1]", - "role": "MASTER" - }, - "pixel_clock": 41667, - "vnc": "system.vncserver", - "name": "clcd", "pio": { "peer": "system.iobus.master[5]", "role": "SLAVE" }, - "amba_id": 1315089, + "system": "system", + "cxx_class": "Pl111", + "enable_capture": true, + "pio_addr": 471793664, "pio_latency": 10000, "clk_domain": "system.clk_domain", - "system": "system", - "gic": "system.realview.gic", "int_num": 46, + "gic": "system.realview.gic", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "eventq_index": 0, - "cxx_class": "Pl111", - "enable_capture": true, + "type": "Pl111", + "vnc": "system.vncserver", + "p_state_clk_gate_min": 1000, + "power_model": null, "path": "system.realview.clcd", - "pio_addr": 471793664, - "type": "Pl111" + "dma": { + "peer": "system.iobus.slave[1]", + "role": "MASTER" + }, + "name": "clcd", + "p_state_clk_gate_bins": 20, + "pixel_clock": 41667, + "amba_id": 1315089 }, "name": "realview", "uart": { + "p_state_clk_gate_min": 1000, "terminal": "system.terminal", - "name": "uart", - "int_delay": 100000, - "platform": "system.realview", "pio": { "peer": "system.iobus.master[0]", "role": "SLAVE" }, + "name": "uart", + "int_delay": 100000, + "platform": "system.realview", + "p_state_clk_gate_bins": 20, + "cxx_class": "Pl011", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "gic": "system.realview.gic", "int_num": 37, "eventq_index": 0, "end_on_eot": false, - "cxx_class": "Pl011", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.uart", "pio_addr": 470351872, "type": "Pl011" }, "intrctrl": "system.intrctrl", "kmi1": { + "p_state_clk_gate_min": 1000, + "p_state_clk_gate_bins": 20, "vnc": "system.vncserver", "name": "kmi1", "int_delay": 1000000, @@ -743,19 +916,24 @@ "role": "SLAVE" }, "amba_id": 1314896, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "gic": "system.realview.gic", "int_num": 45, "eventq_index": 0, "is_mouse": true, "cxx_class": "Pl050", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.kmi1", "pio_addr": 470220800, "type": "Pl050" }, "kmi0": { + "p_state_clk_gate_min": 1000, + "p_state_clk_gate_bins": 20, "vnc": "system.vncserver", "name": "kmi0", "int_delay": 1000000, @@ -764,14 +942,17 @@ "role": "SLAVE" }, "amba_id": 1314896, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "gic": "system.realview.gic", "int_num": 44, "eventq_index": 0, "is_mouse": false, "cxx_class": "Pl050", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.kmi0", "pio_addr": 470155264, "type": "Pl050" @@ -793,6 +974,7 @@ "PXCAPDevCapabilities": 0, "MSIXCAPCapId": 0, "BAR3Size": 4, + "power_model": null, "PXCAPCapabilities": 0, "SubsystemID": 0, "PXCAPCapId": 0, @@ -816,8 +998,10 @@ "BAR2LegacyIO": false, "LatencyTimer": 0, "BAR4LegacyIO": false, + "p_state_clk_gate_max": 1000000000000, "PXCAPLinkStatus": 0, "PXCAPDevCap2": 0, + "p_state_clk_gate_min": 1000, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, "host": "system.realview.pci_host", @@ -841,6 +1025,7 @@ "name": "cf_ctrl", "PXCAPNextCapability": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", "type": "IdeController", "ctrl_offset": 2, "PXCAPBaseOffset": 0, @@ -872,21 +1057,27 @@ "ProgIF": 133, "BAR1LegacyIO": true, "PMCAPCapabilities": 0, - "ClassCode": 1 + "ClassCode": 1, + "p_state_clk_gate_bins": 20 }, "sp810_fake": { + "p_state_clk_gate_bins": 20, "name": "sp810_fake", + "p_state_clk_gate_min": 1000, "pio": { "peer": "system.iobus.master[16]", "role": "SLAVE" }, "amba_id": 0, "ignore_access": true, + "default_p_state": "UNDEFINED", "pio_latency": 100000, "clk_domain": "system.clk_domain", + "power_model": null, "system": "system", "eventq_index": 0, "cxx_class": "AmbaFake", + "p_state_clk_gate_max": 1000000000000, "path": "system.realview.sp810_fake", "pio_addr": 469893120, "type": "AmbaFake" @@ -910,6 +1101,7 @@ "MSIXCAPCapId": 0, "BAR3Size": 0, "rx_desc_cache_size": 64, + "power_model": null, "PXCAPCapabilities": 0, "SubsystemID": 4104, "PXCAPCapId": 0, @@ -933,8 +1125,10 @@ "BAR2LegacyIO": false, "LatencyTimer": 0, "BAR4LegacyIO": false, + "p_state_clk_gate_max": 1000000000000, "PXCAPLinkStatus": 0, "PXCAPDevCap2": 0, + "p_state_clk_gate_min": 1000, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, "host": "system.realview.pci_host", @@ -960,6 +1154,7 @@ "name": "ethernet", "PXCAPNextCapability": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", "type": "IGbE", "tx_fifo_size": 393216, "PXCAPBaseOffset": 0, @@ -996,6 +1191,7 @@ "wb_comp_delay": 10000, "PMCAPCapabilities": 0, "ClassCode": 2, + "p_state_clk_gate_bins": 20, "rx_fifo_size": 393216, "phy_pid": 680 }, @@ -1016,6 +1212,7 @@ "PXCAPDevCapabilities": 0, "MSIXCAPCapId": 0, "BAR3Size": 4, + "power_model": null, "PXCAPCapabilities": 0, "SubsystemID": 0, "PXCAPCapId": 0, @@ -1041,8 +1238,10 @@ "BAR2LegacyIO": false, "LatencyTimer": 0, "BAR4LegacyIO": false, + "p_state_clk_gate_max": 1000000000000, "PXCAPLinkStatus": 0, "PXCAPDevCap2": 0, + "p_state_clk_gate_min": 1000, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, "host": "system.realview.pci_host", @@ -1066,6 +1265,7 @@ "name": "ide", "PXCAPNextCapability": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", "type": "IdeController", "ctrl_offset": 0, "PXCAPBaseOffset": 0, @@ -1097,54 +1297,50 @@ "ProgIF": 133, "BAR1LegacyIO": false, "PMCAPCapabilities": 0, - "ClassCode": 1 + "ClassCode": 1, + "p_state_clk_gate_bins": 20 } }, "membus": { - "default": { - "peer": "system.membus.badaddr_responder.pio", - "role": "MASTER" - }, - "slave": { - "peer": [ - "system.realview.hdlcd.dma", - "system.system_port", - "system.cpu.l2cache.mem_side", - "system.iocache.mem_side" - ], - "role": "SLAVE" - }, - "name": "membus", + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", "badaddr_responder": { - "system": "system", - "ret_data8": 255, - "name": "badaddr_responder", - "warn_access": "warn", "pio": { "peer": "system.membus.default", "role": "SLAVE" }, - "ret_bad_addr": true, - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "fake_mem": false, - "pio_size": 8, - "ret_data32": 4294967295, - "eventq_index": 0, - "update_data": false, "ret_data64": 18446744073709551615, + "fake_mem": false, + "clk_domain": "system.clk_domain", "cxx_class": "IsaFake", - "path": "system.membus.badaddr_responder", "pio_addr": 0, + "update_data": false, + "warn_access": "warn", + "pio_latency": 100000, + "system": "system", + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "type": "IsaFake", - "ret_data16": 65535 + "p_state_clk_gate_min": 1000, + "power_model": null, + "ret_data32": 4294967295, + "path": "system.membus.badaddr_responder", + "ret_data16": 65535, + "ret_data8": 255, + "name": "badaddr_responder", + "ret_bad_addr": true, + "pio_size": 8, + "p_state_clk_gate_bins": 20 }, - "snoop_filter": null, "forward_latency": 4, "clk_domain": "system.clk_domain", - "system": "system", "width": 16, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "master": { "peer": [ "system.bridge.slave", @@ -1156,16 +1352,34 @@ ], "role": "MASTER" }, - "response_latency": 2, - "cxx_class": "CoherentXBar", + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.realview.hdlcd.dma", + "system.system_port", + "system.cpu.l2cache.mem_side", + "system.iocache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": null, + "power_model": null, "path": "system.membus", "snoop_response_latency": 4, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 3 + "name": "membus", + "default": { + "peer": "system.membus.badaddr_responder.pio", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "use_default_range": false }, "multi_thread": false, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "iocache": { "cpu_side": { "peer": "system.iobus.master[25]", @@ -1173,45 +1387,54 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 50, "cxx_class": "Cache", "size": 1024, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 50, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "sequential_access": false, "assoc": 8, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.iocache.tags", + "hit_latency": 50, "block_size": 64, "type": "LRU", "size": 1024 }, - "system": "system", + "clk_domain": "system.clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.membus.slave[3]", "role": "MASTER" }, "type": "Cache", - "forward_snoops": false, "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 50, "tgts_per_mshr": 12, "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "2147483648:2415919103" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.iocache", - "name": "iocache", "mshrs": 20, + "name": "iocache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 8 }, @@ -1228,33 +1451,7 @@ }, "work_end_exit_count": 0, "type": "LinuxArmSystem", - "bridge": { - "ranges": [ - "788529152:805306367", - "721420288:725614591", - "805306368:1073741823", - "1073741824:1610612735", - "402653184:469762047", - "469762048:536870911" - ], - "slave": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "name": "bridge", - "req_size": 16, - "clk_domain": "system.clk_domain", - "delay": 50000, - "eventq_index": 0, - "master": { - "peer": "system.iobus.slave[0]", - "role": "MASTER" - }, - "cxx_class": "Bridge", - "path": "system.bridge", - "resp_size": 16, - "type": "Bridge" - }, + "p_state_clk_gate_min": 1000, "voltage_domain": { "name": "voltage_domain", "eventq_index": 0, @@ -1267,17 +1464,26 @@ }, "cache_line_size": 64, "boot_osflags": "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1", + "system_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, "physmem": [ { "range": "2147483648:2415919103", "latency": 30000, "name": "physmem", + "p_state_clk_gate_min": 1000, "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.clk_domain", + "power_model": null, "latency_var": 0, "bandwidth": "73.000000", "conf_table_reported": true, "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, "path": "system.physmem", "null": false, "type": "SimpleMemory", @@ -1299,6 +1505,7 @@ "type": "Terminal", "port": 3456 }, + "power_model": null, "reset_addr_64": 0, "cpu": [ { @@ -1310,12 +1517,17 @@ "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { + "p_state_clk_gate_min": 1000, "name": "walker", "is_stage2": false, + "p_state_clk_gate_bins": 20, + "cxx_class": "ArmISA::TableWalker", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sys": "system", "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.itb.walker", "type": "ArmTableWalker", "port": { @@ -1339,12 +1551,17 @@ "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { + "p_state_clk_gate_min": 1000, "name": "walker", "is_stage2": true, + "p_state_clk_gate_bins": 20, + "cxx_class": "ArmISA::TableWalker", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sys": "system", "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.istage2_mmu.stage2_tlb.walker", "type": "ArmTableWalker", "num_squash_per_cycle": 2 @@ -1358,65 +1575,6 @@ "path": "system.cpu.istage2_mmu", "type": "ArmStage2MMU" }, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "AtomicSimpleCPU", - "max_loads_all_threads": 0, - "system": "system", - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "width": 1, - "checker": null, - "eventq_index": 0, - "toL2Bus": { - "slave": { - "peer": [ - "system.cpu.icache.mem_side", - "system.cpu.dcache.mem_side", - "system.cpu.itb.walker.port", - "system.cpu.dtb.walker.port" - ], - "role": "SLAVE" - }, - "name": "toL2Bus", - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.cpu.toL2Bus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 0 - }, - "forward_latency": 0, - "clk_domain": "system.cpu_clk_domain", - "system": "system", - "width": 32, - "eventq_index": 0, - "master": { - "peer": [ - "system.cpu.l2cache.cpu_side" - ], - "role": "MASTER" - }, - "response_latency": 1, - "cxx_class": "CoherentXBar", - "path": "system.cpu.toL2Bus", - "snoop_response_latency": 1, - "type": "CoherentXBar", - "use_default_range": false, - "frontend_latency": 1 - }, - "do_quiesce": true, - "type": "AtomicSimpleCPU", - "fastmem": false, - "profile": 0, - "icache_port": { - "peer": "system.cpu.icache.cpu_side", - "role": "MASTER" - }, "icache": { "cpu_side": { "peer": "system.cpu.icache_port", @@ -1424,48 +1582,126 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 1, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.icache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.cpu.toL2Bus.slave[0]", "role": "MASTER" }, "type": "Cache", - "forward_snoops": true, "writeback_clean": true, + "p_state_clk_gate_min": 1000, "hit_latency": 2, "tgts_per_mshr": 20, "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": true, "prefetch_on_access": false, "path": "system.cpu.icache", - "name": "icache", "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 1 }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side", + "system.cpu.itb.walker.port", + "system.cpu.dtb.walker.port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, "interrupts": [ { "eventq_index": 0, @@ -1480,6 +1716,7 @@ "role": "MASTER" }, "socket_id": 0, + "power_model": null, "max_insts_all_threads": 0, "dstage2_mmu": { "name": "dstage2_mmu", @@ -1491,12 +1728,17 @@ "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { + "p_state_clk_gate_min": 1000, "name": "walker", "is_stage2": true, + "p_state_clk_gate_bins": 20, + "cxx_class": "ArmISA::TableWalker", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sys": "system", "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.dstage2_mmu.stage2_tlb.walker", "type": "ArmTableWalker", "num_squash_per_cycle": 2 @@ -1517,45 +1759,54 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 20, "cxx_class": "Cache", "size": 4194304, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 20, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 8, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.l2cache.tags", + "hit_latency": 20, "block_size": 64, "type": "LRU", "size": 4194304 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.membus.slave[2]", "role": "MASTER" }, "type": "Cache", - "forward_snoops": true, "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 20, "tgts_per_mshr": 12, "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.cpu.l2cache", - "name": "l2cache", "mshrs": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 8 }, @@ -1570,12 +1821,17 @@ "eventq_index": 0, "cxx_class": "ArmISA::TLB", "walker": { + "p_state_clk_gate_min": 1000, "name": "walker", "is_stage2": false, + "p_state_clk_gate_bins": 20, + "cxx_class": "ArmISA::TableWalker", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sys": "system", "eventq_index": 0, - "cxx_class": "ArmISA::TableWalker", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.dtb.walker", "type": "ArmTableWalker", "port": { @@ -1600,45 +1856,54 @@ }, "clusivity": "mostly_incl", "prefetcher": null, - "clk_domain": "system.cpu_clk_domain", + "system": "system", "write_buffers": 8, "response_latency": 2, "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", + "p_state_clk_gate_min": 1000, "eventq_index": 0, - "hit_latency": 2, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", "clk_domain": "system.cpu_clk_domain", + "power_model": null, "sequential_access": false, "assoc": 4, "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, "path": "system.cpu.dcache.tags", + "hit_latency": 2, "block_size": 64, "type": "LRU", "size": 32768 }, - "system": "system", + "clk_domain": "system.cpu_clk_domain", "max_miss_count": 0, "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, "mem_side": { "peer": "system.cpu.toL2Bus.slave[1]", "role": "MASTER" }, "type": "Cache", - "forward_snoops": true, "writeback_clean": false, + "p_state_clk_gate_min": 1000, "hit_latency": 2, "tgts_per_mshr": 20, "demand_mshr_reserve": 1, + "power_model": null, "addr_ranges": [ "0:18446744073709551615" ], "is_read_only": false, "prefetch_on_access": false, "path": "system.cpu.dcache", - "name": "dcache", "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, "sequential_access": false, "assoc": 4 }, @@ -1689,7 +1954,7 @@ ], "gic_cpu_addr": 738205696, "work_cpus_ckpt_count": 0, - "work_begin_exit_count": 0, + "thermal_components": [], "machine_type": "VExpress_EMM64", "flags_addr": 469827632, "path": "system", @@ -1720,7 +1985,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.cf0.image.child", - "image_file": "/work/gem5/dist/disks/linaro-minimal-aarch64.img", + "image_file": "/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img", "type": "RawDiskImage" }, "path": "system.cf0.image", @@ -1738,10 +2003,7 @@ "mem_mode": "atomic", "name": "system", "init_param": 0, - "system_port": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, + "p_state_clk_gate_bins": 20, "load_addr_mask": 268435455, "work_item_id": -1, "intrctrl": { @@ -1759,11 +2021,11 @@ "system.realview.nvmem", "system.realview.vram" ], - "work_begin_cpu_id_exit": -1, + "num_work_ids": 16, "boot_loader": [ - "/work/gem5/dist/binaries/boot_emm.arm64" + "/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64" ], - "num_work_ids": 16 + "exit_on_work_items": false }, "time_sync_period": 100000000000, "eventq_index": 0, diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index e0d2d1c95..b33124edd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167216500 # Number of ticks simulated -final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 51111167192000 # Number of ticks simulated +final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 974606 # Simulator instruction rate (inst/s) -host_op_rate 1145373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50715816566 # Simulator tick rate (ticks/s) -host_mem_usage 678940 # Number of bytes of host memory used -host_seconds 1007.80 # Real time elapsed on the host -sim_insts 982203438 # Number of instructions simulated -sim_ops 1154301153 # Number of ops (including micro ops) simulated +host_inst_rate 942442 # Simulator instruction rate (inst/s) +host_op_rate 1107573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49042304128 # Simulator tick rate (ticks/s) +host_mem_usage 674172 # Number of bytes of host memory used +host_seconds 1042.19 # Real time elapsed on the host +sim_insts 982198638 # Number of instructions simulated +sim_ops 1154296340 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory +system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory +system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,7 +109,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 266586 # Table walker walks requested system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency @@ -118,8 +118,8 @@ system.cpu.dtb.walker.walkWaitTime::total 266586 # T system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -130,10 +130,10 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183545125 # DTB read hits -system.cpu.dtb.read_misses 195347 # DTB read misses -system.cpu.dtb.write_hits 167774776 # DTB write hits -system.cpu.dtb.write_misses 71239 # DTB write misses +system.cpu.dtb.read_hits 183544097 # DTB read hits +system.cpu.dtb.read_misses 195348 # DTB read misses +system.cpu.dtb.write_hits 167774773 # DTB write hits +system.cpu.dtb.write_misses 71238 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID @@ -143,13 +143,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183740472 # DTB read accesses -system.cpu.dtb.write_accesses 167846015 # DTB write accesses +system.cpu.dtb.read_accesses 183739445 # DTB read accesses +system.cpu.dtb.write_accesses 167846011 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351319901 # DTB hits +system.cpu.dtb.hits 351318870 # DTB hits system.cpu.dtb.misses 266586 # DTB misses -system.cpu.dtb.accesses 351586487 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 351585456 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 126834 # Table walker walks requested system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency @@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 982680284 # ITB inst hits +system.cpu.itb.inst_hits 982675484 # ITB inst hits system.cpu.itb.inst_misses 126834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -215,14 +215,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982807118 # ITB inst accesses -system.cpu.itb.hits 982680284 # DTB hits +system.cpu.itb.inst_accesses 982802318 # ITB inst accesses +system.cpu.itb.hits 982675484 # DTB hits system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982807118 # DTB accesses +system.cpu.itb.accesses 982802318 # DTB accesses system.cpu.numPwrStateTransitions 33550 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state @@ -234,41 +234,41 @@ system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 102222351209 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 102222351160 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 982203438 # Number of instructions committed -system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses +system.cpu.committedInsts 982198638 # Number of instructions committed +system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56834581 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057882257 # number of integer instructions +system.cpu.num_func_calls 56833909 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls +system.cpu.num_int_insts 1057877800 # number of integer instructions system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read -system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written +system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read +system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written -system.cpu.num_mem_refs 351539335 # number of memory refs -system.cpu.num_load_insts 183712430 # Number of load instructions -system.cpu.num_store_insts 167826905 # Number of store instructions -system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles -system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles +system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written +system.cpu.num_mem_refs 351538306 # number of memory refs +system.cpu.num_load_insts 183711405 # Number of load instructions +system.cpu.num_store_insts 167826901 # Number of store instructions +system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles +system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219534054 # Number of branches fetched +system.cpu.Branches 219532347 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction +system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction @@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154935820 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11606642 # number of replacements +system.cpu.op_class::total 1154931007 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11605970 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -316,88 +316,88 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits -system.cpu.dcache.overall_hits::total 330945053 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits +system.cpu.dcache.overall_hits::total 330944693 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses -system.cpu.dcache.overall_misses::total 11404487 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses +system.cpu.dcache.overall_misses::total 11403820 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks -system.cpu.dcache.writebacks::total 8917390 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14265253 # number of replacements +system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks +system.cpu.dcache.writebacks::total 8916642 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14265273 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy @@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 184 system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits -system.cpu.icache.overall_hits::total 968529210 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses -system.cpu.icache.overall_misses::total 14265770 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses +system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits +system.cpu.icache.overall_hits::total 968524390 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses +system.cpu.icache.overall_misses::total 14265790 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses @@ -439,199 +439,200 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks -system.cpu.icache.writebacks::total 14265253 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1725806 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks. +system.cpu.icache.writebacks::writebacks 14265273 # number of writebacks +system.cpu.icache.writebacks::total 14265273 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1725823 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65319.568119 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46895862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1788839 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.215809 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 447.819467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.912411 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21282.908549 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567632 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.625793 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.901085 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.914096 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.567636 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006833 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006865 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.324751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324715 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 320 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1023 317 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 320 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 425623617 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 425623617 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509088 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11205 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1689414 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1689414 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182764 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7499286 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7499286 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694547 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694547 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 509091 # number of demand (read+write) hits +system.cpu.l2cache.ReadReq_hits::total 765041 # number of ReadReq hits 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ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694560 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694560 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 509088 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14182764 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9188700 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24136508 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 509091 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 14182781 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9188003 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24135825 # number of demand (read+write) hits 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UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 39927 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39927 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 827599 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 827599 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83006 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 83006 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344098 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344098 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 552223 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 552223 # number of InvalidateReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 827609 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 827609 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83009 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 83009 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344111 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344111 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 552212 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 552212 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 83006 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1171697 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1267016 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 83009 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1171720 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1267042 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 83006 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1171697 # number of overall misses -system.cpu.l2cache.overall_misses::total 1267016 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515567 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 83009 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1171720 # number of overall misses +system.cpu.l2cache.overall_misses::total 1267042 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515564 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 777357 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8917390 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8917390 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14263676 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14263676 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51129 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 51129 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 777354 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8916642 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8916642 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14263696 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14263696 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51131 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 51131 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516995 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2516995 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265790 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14265790 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842728 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7842728 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515564 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14265790 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10359723 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25402867 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515564 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14265790 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10359723 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25402867 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780877 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780877 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328808 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328808 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043876 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043876 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442913 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks -system.cpu.l2cache.writebacks::total 1507080 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks +system.cpu.l2cache.writebacks::total 1507088 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1957577 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1957594 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40242 # Transaction distribution system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -674,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy @@ -691,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039650 # Number of tag accesses system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses @@ -739,64 +740,65 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524946 # Transaction distribution +system.membus.trans_dist::ReadResp 524962 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution -system.membus.trans_dist::CleanEvict 226320 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution +system.membus.trans_dist::CleanEvict 226329 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution -system.membus.trans_dist::ReadExReq 827042 # Transaction distribution -system.membus.trans_dist::ReadExResp 827042 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution +system.membus.trans_dist::ReadExReq 827052 # Transaction distribution +system.membus.trans_dist::ReadExResp 827052 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3924997 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 3925032 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3924997 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 3925032 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -839,28 +841,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/system.terminal index 7a2b5d086..e00102254 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/system.terminal @@ -77,7 +77,7 @@ [ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131281] NET: Registered protocol family 1
-[ 3.131310] RPC: Registered named UNIX socket transport module.
+[ 3.131311] RPC: Registered named UNIX socket transport module.
[ 3.131311] RPC: Registered udp transport module.
[ 3.131312] RPC: Registered tcp transport module.
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
@@ -87,7 +87,7 @@ [ 3.132687] fuse init (API version 7.23)
[ 3.132738] msgmni has been set to 469
[ 3.133992] io scheduler noop registered
-[ 3.134024] io scheduler cfq registered (default)
+[ 3.134025] io scheduler cfq registered (default)
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
@@ -98,24 +98,24 @@ [ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134354] pci_bus 0000:00: fixups for bus
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
-[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
@@ -158,9 +158,9 @@ [ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.446951] udevd[607]: starting version 182
+[ 3.446950] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.532266] random: dd urandom read with 19 bits of entropy available
+[ 3.532262] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini index 7268469a8..4ef1d1b22 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -168,8 +190,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -192,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -208,9 +240,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -246,8 +287,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -305,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -321,9 +372,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -334,13 +390,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -358,6 +418,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -368,6 +429,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -384,8 +449,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -393,9 +463,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -423,6 +499,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -441,6 +518,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -462,13 +543,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -487,8 +572,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -511,9 +601,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -527,9 +622,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -540,13 +640,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -565,8 +669,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -624,9 +733,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -640,9 +754,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -653,13 +772,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -677,6 +800,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -687,6 +811,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -703,8 +831,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -712,9 +845,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -759,9 +898,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -775,13 +919,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -800,8 +948,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -812,13 +965,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -837,20 +994,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -862,11 +1030,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -877,16 +1050,28 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -901,10 +1086,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -985,14 +1175,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1001,13 +1196,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1017,6 +1217,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1087,10 +1288,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1170,17 +1376,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1206,12 +1417,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1219,14 +1436,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1312,14 +1534,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1328,13 +1555,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1343,13 +1575,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1357,11 +1594,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1375,11 +1617,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1393,19 +1640,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1451,14 +1704,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1467,11 +1735,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1481,21 +1754,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1505,12 +1788,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1519,10 +1807,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1532,12 +1825,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1547,26 +1845,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1575,10 +1883,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1586,10 +1899,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1597,21 +1915,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1625,11 +1953,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1640,11 +1973,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1652,10 +1990,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1671,9 +2014,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr index a78b01f0e..ec34e9426 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr @@ -2,9 +2,12 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout index 722fe47ae..520d50f95 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 13:36:23 -gem5 executing on e104799-lin, pid 11118 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:49:27 +gem5 executing on e108600-lin, pid 23294 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47216814145000 because m5_exit instruction encountered +Exiting @ tick 47296281748500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 613ee48d7..99716a632 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.216815 # Number of seconds simulated -sim_ticks 47216814802000 # Number of ticks simulated -final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.296282 # Number of seconds simulated +sim_ticks 47296281748500 # Number of ticks simulated +final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 917426 # Simulator instruction rate (inst/s) -host_op_rate 1079212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44335256452 # Simulator tick rate (ticks/s) -host_mem_usage 692848 # Number of bytes of host memory used -host_seconds 1064.99 # Real time elapsed on the host -sim_insts 977053655 # Number of instructions simulated -sim_ops 1149354696 # Number of ops (including micro ops) simulated +host_inst_rate 717114 # Simulator instruction rate (inst/s) +host_op_rate 843581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34713303168 # Simulator tick rate (ticks/s) +host_mem_usage 688104 # Number of bytes of host memory used +host_seconds 1362.48 # Real time elapsed on the host +sim_insts 977055082 # Number of instructions simulated +sim_ops 1149364510 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417728 # Number of bytes read from this memory -system.physmem.bytes_read::total 81375732 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3895860 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2668232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6564092 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101375872 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 151424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 124352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3875572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35081800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 221312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2647048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38747248 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 401984 # Number of bytes read from this memory +system.physmem.bytes_read::total 81473076 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3875572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2647048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6522620 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101454976 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 101396456 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2349 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 101280 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 546090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41798 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 605103 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1312039 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1583998 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101475560 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 100963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 548166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 605442 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6281 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1313560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1585234 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1586572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 740180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 820164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1723448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 139020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2147029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1587808 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 81942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 741745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 819245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1722611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 81942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55967 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 137910 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2145094 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2147029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.physmem.bw_write::total 2145529 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2145094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 81942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 742181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 819245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3868140 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -100,9 +100,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -110,7 +110,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -140,47 +140,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 124420 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 125159 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 125159 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 125159 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 125159 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 125159 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95857 89.92% 89.92% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10751 10.08% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106608 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 96412 89.79% 89.79% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10963 10.21% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107375 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125159 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106608 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125159 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107375 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106608 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 231028 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107375 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 232534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91801710 # DTB read hits -system.cpu0.dtb.read_misses 88193 # DTB read misses -system.cpu0.dtb.write_hits 84999619 # DTB write hits -system.cpu0.dtb.write_misses 36227 # DTB write misses +system.cpu0.dtb.read_hits 92471463 # DTB read hits +system.cpu0.dtb.read_misses 88826 # DTB read misses +system.cpu0.dtb.write_hits 85455153 # DTB write hits +system.cpu0.dtb.write_misses 36333 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36431 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4810 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91889903 # DTB read accesses -system.cpu0.dtb.write_accesses 85035846 # DTB write accesses +system.cpu0.dtb.perms_faults 10399 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92560289 # DTB read accesses +system.cpu0.dtb.write_accesses 85491486 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176801329 # DTB hits -system.cpu0.dtb.misses 124420 # DTB misses -system.cpu0.dtb.accesses 176925749 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 177926616 # DTB hits +system.cpu0.dtb.misses 125159 # DTB misses +system.cpu0.dtb.accesses 178051775 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -210,463 +210,464 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 60852 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 61082 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61082 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 61082 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61082 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61082 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54793 98.83% 98.83% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 650 1.17% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 55443 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54995 98.82% 98.82% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 656 1.18% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55651 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60852 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60852 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61082 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61082 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55443 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55443 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 116295 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493637993 # ITB inst hits -system.cpu0.itb.inst_misses 60852 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55651 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55651 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 116733 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 496679820 # ITB inst hits +system.cpu0.itb.inst_misses 61082 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25053 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25177 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses -system.cpu0.itb.hits 493637993 # DTB hits -system.cpu0.itb.misses 60852 # DTB misses -system.cpu0.itb.accesses 493698845 # DTB accesses -system.cpu0.numPwrStateTransitions 26456 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13226 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3548051502.510434 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 89670925641.729767 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3168 23.95% 23.95% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10031 75.84% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 496740902 # ITB inst accesses +system.cpu0.itb.hits 496679820 # DTB hits +system.cpu0.itb.misses 61082 # DTB misses +system.cpu0.itb.accesses 496740902 # DTB accesses +system.cpu0.numPwrStateTransitions 26445 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13222 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3555001605.490697 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 88683028869.484894 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3170 23.98% 23.98% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10025 75.82% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7470356053852 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13226 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 290285629797 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46926529172203 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94433642835 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7351153278004 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13222 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 292050520702 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94592576721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed -system.cpu0.committedInsts 493402150 # Number of instructions committed -system.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 521057 # Number of float alu accesses -system.cpu0.num_func_calls 28738017 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75812609 # number of instructions that are conditional controls -system.cpu0.num_int_insts 531778274 # number of integer instructions -system.cpu0.num_fp_insts 521057 # number of float instructions -system.cpu0.num_int_register_reads 778807297 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421918818 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 841474 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 439940 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132610797 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132275173 # number of times the CC registers were written -system.cpu0.num_mem_refs 176902115 # number of memory refs -system.cpu0.num_load_insts 91875039 # Number of load instructions -system.cpu0.num_store_insts 85027076 # Number of store instructions -system.cpu0.num_idle_cycles 93853071494.060760 # Number of idle cycles -system.cpu0.num_busy_cycles 580571340.939238 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006148 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993852 # Percentage of idle cycles -system.cpu0.Branches 110403926 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13223 # number of quiesce instructions executed +system.cpu0.committedInsts 496443686 # Number of instructions committed +system.cpu0.committedOps 583761680 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 535025290 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 524584 # Number of float alu accesses +system.cpu0.num_func_calls 28899937 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76311856 # number of instructions that are conditional controls +system.cpu0.num_int_insts 535025290 # number of integer instructions +system.cpu0.num_fp_insts 524584 # number of float instructions +system.cpu0.num_int_register_reads 783282318 # number of times the integer registers were read +system.cpu0.num_int_register_writes 424505870 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 845921 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 445948 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133408683 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 133073326 # number of times the CC registers were written +system.cpu0.num_mem_refs 178027643 # number of memory refs +system.cpu0.num_load_insts 92545018 # Number of load instructions +system.cpu0.num_store_insts 85482625 # Number of store instructions +system.cpu0.num_idle_cycles 94008475597.936935 # Number of idle cycles +system.cpu0.num_busy_cycles 584101123.063064 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006175 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993825 # Percentage of idle cycles +system.cpu0.Branches 111093071 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 402310075 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1222689 0.21% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 59704 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 72217 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction -system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction +system.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72938 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 92545018 15.84% 85.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 85482625 14.64% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 580566843 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6218107 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. +system.cpu0.op_class::total 584096590 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6248912 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 171607959 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6249424 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.459804 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.980430 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076595 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2076595 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2038168 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2038168 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165891148 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165891148 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 166105825 # number of overall hits -system.cpu0.dcache.overall_hits::total 166105825 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3280646 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3280646 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1472125 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1472125 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768471 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 768471 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 819890 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 819890 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 117360 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 117360 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154684 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 154684 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5572661 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5572661 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6341132 # number of overall misses -system.cpu0.dcache.overall_misses::total 6341132 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88668606 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88668606 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81714928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81714928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 983148 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 983148 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1080275 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1080275 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193955 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2193955 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2192852 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2192852 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171463809 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171463809 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172446957 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172446957 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036999 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036999 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018015 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018015 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781643 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781643 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758964 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758964 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032501 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032501 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036771 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036771 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 362271537 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 362271537 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80672636 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80672636 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261023 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 261023 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2087977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051999 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2051999 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 166957831 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 166957831 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167174100 # number of overall hits +system.cpu0.dcache.overall_hits::total 167174100 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1479208 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1479208 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824176 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 824176 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119749 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119749 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154638 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 154638 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5601806 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5601806 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6371369 # number of overall misses +system.cpu0.dcache.overall_misses::total 6371369 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82151844 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 985832 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 985832 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1085199 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1085199 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207726 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2207726 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2206637 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2206637 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 172559637 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 172559637 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 173545469 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018006 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018006 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759470 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759470 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054241 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054241 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070079 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070079 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032463 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032463 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036713 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036713 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks -system.cpu0.dcache.writebacks::total 6218107 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5488502 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor +system.cpu0.dcache.writebacks::writebacks 6248912 # number of writebacks +system.cpu0.dcache.writebacks::total 6248912 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5509619 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 491225335 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5510131 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 89.149484 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits -system.cpu0.icache.overall_hits::total 488204417 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5489019 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5489019 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5489019 # number of overall misses -system.cpu0.icache.overall_misses::total 5489019 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 493693436 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 493693436 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 493693436 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 493693436 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 493693436 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 493693436 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011118 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011118 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011118 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011118 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011118 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011118 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 998981078 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 998981078 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 491225335 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 491225335 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 491225335 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 491225335 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 491225335 # number of overall hits +system.cpu0.icache.overall_hits::total 491225335 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5510136 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5510136 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5510136 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5510136 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5510136 # number of overall misses +system.cpu0.icache.overall_misses::total 5510136 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 496735471 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 496735471 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 496735471 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011093 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011093 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011093 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011093 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011093 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011093 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks -system.cpu0.icache.writebacks::total 5488502 # number of writebacks -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 5509619 # number of writebacks +system.cpu0.icache.writebacks::total 5509619 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2643580 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2653803 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16139.372932 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15525451 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2669765 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.815287 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 37.515300 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.980883 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002415 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002290 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985588 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 16063.015838 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 35.657747 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 40.699347 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.980409 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002176 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002484 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985069 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15949 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15909 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1444 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4368 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4524 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 738 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 633298 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 633298 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4991790 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4991790 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937635 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2937635 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218374 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 218374 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 293436 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155846 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4991790 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3570933 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9012005 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 293436 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155846 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4991790 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3570933 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9012005 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11306 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8709 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 20015 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136695 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 136695 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154684 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 154684 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701772 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 701772 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1228842 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1228842 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601138 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 601138 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11306 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8709 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1930614 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2447858 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11306 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8709 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1930614 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2447858 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 304742 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164555 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 469297 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4423360 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4423360 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7281875 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7281875 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137433 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 137433 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154684 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 154684 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1335070 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1335070 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5489019 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5489019 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4166477 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4166477 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819512 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 819512 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 304742 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164555 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5489019 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5501547 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11459863 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 304742 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164555 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5489019 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5501547 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11459863 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052925 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.042649 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994630 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994630 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971008 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 395826781 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 395826781 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 296735 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157755 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 454490 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4439476 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4439476 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7317657 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7317657 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 746 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 746 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 639086 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 639086 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5010934 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5010934 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2954772 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2954772 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 221315 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 221315 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 296735 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157755 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5010934 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3593858 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9059282 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 296735 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157755 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5010934 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3593858 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9059282 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11441 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8530 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 19971 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138499 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 138499 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154638 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 154638 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701212 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 701212 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 499202 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 499202 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1232962 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1232962 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 602526 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 602526 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11441 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8530 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 499202 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1934174 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2453347 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11441 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8530 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 499202 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1934174 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2453347 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 308176 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166285 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 474461 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4439476 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4439476 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7317657 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7317657 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139245 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 139245 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154638 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 154638 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510136 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5510136 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187734 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4187734 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 308176 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166285 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5510136 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5528032 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11512629 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 308176 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166285 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5510136 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5528032 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11512629 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051297 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.042092 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994643 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994643 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525644 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525644 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090586 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090586 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294936 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294936 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733532 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733532 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052925 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090586 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350922 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.213603 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052925 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090586 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350922 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.213603 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.523176 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.523176 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090597 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090597 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294422 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294422 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731362 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731362 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051297 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090597 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349885 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.213101 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051297 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090597 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349885 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.213101 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks -system.cpu0.l2cache.writebacks::total 1554149 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 292117 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1335070 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1335070 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5489019 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4166477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 819512 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 819512 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16552790 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19577101 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 363556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723958 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37217405 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 702733844 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 750256336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1454224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2895832 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1457340236 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6073545 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 30354370 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.066939 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.249960 # Request fanout histogram +system.cpu0.l2cache.writebacks::writebacks 1559963 # number of writebacks +system.cpu0.l2cache.writebacks::total 1559963 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 24176858 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12314856 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1775409 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1775098 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 311 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10320487 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4439476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7319055 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 139245 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154638 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 293883 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187734 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616141 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19673024 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37382017 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705436820 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753922812 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1463731040 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6082125 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 101619328 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 30471409 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.066979 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.250027 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28430762 93.30% 93.30% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2040336 6.70% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 311 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.snoop_fanout::total 30471409 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -696,47 +697,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 144355 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 111959 88.88% 88.88% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14012 11.12% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 125971 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144355 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 144363 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144363 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144363 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144363 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144363 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 111796 88.76% 88.76% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14154 11.24% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 125950 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144363 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144355 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125971 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144363 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125950 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125971 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 270326 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125950 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 270313 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91325952 # DTB read hits -system.cpu1.dtb.read_misses 111931 # DTB read misses -system.cpu1.dtb.write_hits 82141676 # DTB write hits -system.cpu1.dtb.write_misses 32424 # DTB write misses +system.cpu1.dtb.read_hits 90656208 # DTB read hits +system.cpu1.dtb.read_misses 111973 # DTB read misses +system.cpu1.dtb.write_hits 81688076 # DTB write hits +system.cpu1.dtb.write_misses 32390 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44794 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44622 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4399 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91437883 # DTB read accesses -system.cpu1.dtb.write_accesses 82174100 # DTB write accesses +system.cpu1.dtb.perms_faults 11479 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90768181 # DTB read accesses +system.cpu1.dtb.write_accesses 81720466 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 173467628 # DTB hits -system.cpu1.dtb.misses 144355 # DTB misses -system.cpu1.dtb.accesses 173611983 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 172344284 # DTB hits +system.cpu1.dtb.misses 144363 # DTB misses +system.cpu1.dtb.accesses 172488647 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -766,460 +767,462 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 61638 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54650 99.05% 99.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 526 0.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55176 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 61351 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61351 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61351 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61351 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61351 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54387 99.05% 99.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 524 0.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 54911 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61638 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61638 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61351 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61351 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55176 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55176 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 116814 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 483902380 # ITB inst hits -system.cpu1.itb.inst_misses 61638 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54911 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54911 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 116262 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 480862179 # ITB inst hits +system.cpu1.itb.inst_misses 61351 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31448 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31395 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses -system.cpu1.itb.hits 483902380 # DTB hits -system.cpu1.itb.misses 61638 # DTB misses -system.cpu1.itb.accesses 483964018 # DTB accesses -system.cpu1.numPwrStateTransitions 12326 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 6163 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 7615138435.844394 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 188025849317.388916 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4489 72.84% 72.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1652 26.81% 99.64% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.10% 99.74% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 480923530 # ITB inst accesses +system.cpu1.itb.hits 480862179 # DTB hits +system.cpu1.itb.misses 61351 # DTB misses +system.cpu1.itb.accesses 480923530 # DTB accesses +system.cpu1.numPwrStateTransitions 12248 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 6124 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 7676898273.449706 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 188572680414.552032 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4459 72.81% 72.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1644 26.85% 99.66% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.74% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813542449500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 6163 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 284716621891 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46932098180109 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94433635768 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 11813542452500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 6124 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 282956721894 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94592569622 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu1.committedInsts 483651505 # Number of instructions committed -system.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 379089 # Number of float alu accesses -system.cpu1.num_func_calls 28525698 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 74077236 # number of instructions that are conditional controls -system.cpu1.num_int_insts 522328734 # number of integer instructions -system.cpu1.num_fp_insts 379089 # number of float instructions -system.cpu1.num_int_register_reads 771436981 # number of times the integer registers were read -system.cpu1.num_int_register_writes 415765246 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 615128 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 311192 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 127876698 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 127597836 # number of times the CC registers were written -system.cpu1.num_mem_refs 173588529 # number of memory refs -system.cpu1.num_load_insts 91424864 # Number of load instructions -system.cpu1.num_store_insts 82163665 # Number of store instructions -system.cpu1.num_idle_cycles 93864202487.047195 # Number of idle cycles -system.cpu1.num_busy_cycles 569433280.952807 # Number of busy cycles -system.cpu1.not_idle_fraction 0.006030 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.993970 # Percentage of idle cycles -system.cpu1.Branches 107756231 # Number of branches fetched +system.cpu1.kern.inst.quiesce 6124 # number of quiesce instructions executed +system.cpu1.committedInsts 480611396 # Number of instructions committed +system.cpu1.committedOps 565602830 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 519092247 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 374666 # Number of float alu accesses +system.cpu1.num_func_calls 28363152 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 73579507 # number of instructions that are conditional controls +system.cpu1.num_int_insts 519092247 # number of integer instructions +system.cpu1.num_fp_insts 374666 # number of float instructions +system.cpu1.num_int_register_reads 766987939 # number of times the integer registers were read +system.cpu1.num_int_register_writes 413187755 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 609913 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 303136 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 127077975 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 126798720 # number of times the CC registers were written +system.cpu1.num_mem_refs 172465256 # number of memory refs +system.cpu1.num_load_insts 90755131 # Number of load instructions +system.cpu1.num_store_insts 81710125 # Number of store instructions +system.cpu1.num_idle_cycles 94026656141.566330 # Number of idle cycles +system.cpu1.num_busy_cycles 565913480.433670 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005983 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994017 # Percentage of idle cycles +system.cpu1.Branches 107067845 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 394594292 69.30% 69.30% # Class of executed instruction -system.cpu1.op_class::IntMult 1146816 0.20% 69.50% # Class of executed instruction -system.cpu1.op_class::IntDiv 61459 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 37349 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::IntAlu 392212619 69.31% 69.31% # Class of executed instruction +system.cpu1.op_class::IntMult 1132978 0.20% 69.51% # Class of executed instruction +system.cpu1.op_class::IntDiv 61173 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 36628 0.01% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 90755131 16.04% 85.56% # Class of executed instruction +system.cpu1.op_class::MemWrite 81710125 14.44% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 569428445 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 6003966 # number of replacements -system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2067288 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2067288 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2056969 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2056969 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 162861135 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 162861135 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 163048661 # number of overall hits -system.cpu1.dcache.overall_hits::total 163048661 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3388721 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3388721 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1469364 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1469364 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 795051 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 795051 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 438458 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 438458 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 148516 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 148516 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157576 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 157576 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5296543 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5296543 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6091594 # number of overall misses -system.cpu1.dcache.overall_misses::total 6091594 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 88220769 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 88220769 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 79433024 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 79433024 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 982577 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 982577 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 503885 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 503885 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2215804 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2215804 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2214545 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2214545 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 168157678 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 168157678 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 169140255 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 169140255 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038412 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038412 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018498 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018498 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870155 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870155 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067026 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067026 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071155 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071155 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031497 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031497 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036015 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036015 # miss rate for overall accesses +system.cpu1.op_class::total 565908654 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5970882 # number of replacements +system.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 166384450 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5971393 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.863591 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.826865 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 350957209 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 350957209 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 84198599 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 84198599 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 77532107 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77532107 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64879 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 64879 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055501 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2055501 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044925 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2044925 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 161795585 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 161795585 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 161982848 # number of overall hits +system.cpu1.dcache.overall_hits::total 161982848 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3367289 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3367289 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1465578 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1465578 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433878 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 433878 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147104 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 147104 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156474 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 156474 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5266745 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5266745 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6060368 # number of overall misses +system.cpu1.dcache.overall_misses::total 6060368 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 78997685 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980886 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 980886 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498757 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 498757 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2202605 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2202605 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2201399 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2201399 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 167062330 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 167062330 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 168043216 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018552 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018552 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869919 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869919 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066786 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066786 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071079 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071079 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031526 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031526 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036064 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.036064 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks -system.cpu1.dcache.writebacks::total 6003966 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4799154 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 5970882 # number of writebacks +system.cpu1.dcache.writebacks::total 5970882 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4768482 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 476148096 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4768994 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.842461 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.452247 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969633 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969633 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits -system.cpu1.icache.overall_hits::total 479157890 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4799666 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4799666 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4799666 # number of overall misses -system.cpu1.icache.overall_misses::total 4799666 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 483957556 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 483957556 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 483957556 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 483957556 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 483957556 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 483957556 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009918 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009918 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009918 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009918 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009918 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009918 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 966603174 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 966603174 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 476148096 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 476148096 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 476148096 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 476148096 # 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number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 480917090 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 480917090 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.948066 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.807418 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003129 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004025 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.814572 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2262891 # 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Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.815263 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15892 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1574 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6119 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4359 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3688 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.969971 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 363588050 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 363588050 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 348760 # 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number of overall hits +system.cpu1.l2cache.overall_hits::total 8511379 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12218 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9629 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 21847 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143649 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 143649 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156474 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 156474 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 707649 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 707649 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 462285 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 462285 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1220972 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1220972 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268887 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 268887 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12218 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9629 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 462285 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1928621 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2412753 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12218 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9629 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 462285 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1928621 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2412753 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360978 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165058 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 526036 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4050331 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4050331 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6688666 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6688666 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144703 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 144703 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156474 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 156474 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308016 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4308016 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360978 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165058 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5629102 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10924132 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360978 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165058 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5629102 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10924132 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.041531 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992716 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992716 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535264 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535264 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097215 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097215 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.282838 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.282838 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620897 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620897 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058179 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097215 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341947 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.220626 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058179 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097215 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341947 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.220626 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535657 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535657 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096936 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096936 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283419 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283419 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620031 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620031 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058337 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096936 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342616 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.220865 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058337 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096936 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342616 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.220865 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks -system.cpu1.l2cache.writebacks::total 1211269 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 302533 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1324652 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1324652 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4799666 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4332288 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 438213 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 438213 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14398746 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18822028 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368476 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836878 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34426128 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614325000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 746331191 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1473904 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3347512 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1365477607 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5687998 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 28144557 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.072239 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.258905 # Request fanout histogram +system.cpu1.l2cache.writebacks::writebacks 1200117 # number of writebacks +system.cpu1.l2cache.writebacks::total 1200117 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 22145801 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314039 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1748963 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1748793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9684671 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4050331 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6689033 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 144703 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156474 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 301177 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308016 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18721524 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34231694 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432303 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1357645047 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5675394 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 79399936 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 28001988 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.072258 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.258938 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 25978793 92.77% 92.77% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2023025 7.22% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.snoop_fanout::total 28001988 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40301 # Transaction distribution system.iobus.trans_dist::ReadResp 40301 # Transaction distribution system.iobus.trans_dist::WriteReq 136636 # Transaction distribution @@ -1262,24 +1265,24 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7338888 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115590 # number of replacements -system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use +system.iocache.tags.tagsinuse 11.298808 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.845510 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.453298 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240344 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465831 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706176 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040838 # Number of tag accesses system.iocache.tags.data_accesses 1040838 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses @@ -1327,278 +1330,279 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1772279 # number of replacements -system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use -system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1774395 # number of replacements +system.l2c.tags.tagsinuse 63409.930559 # Cycle average of tags in use +system.l2c.tags.total_refs 4611925 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1833378 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.515534 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 43.277467 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3264.617227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6940.607740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 274.307726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 426.439632 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2871.138387 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 14482.680343 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.531803 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000545 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000660 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.049814 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004186 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.043810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.220988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964219 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 59404 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 73419992 # Number of tag accesses -system.l2c.tags.data_accesses 73419992 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 200286 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 176214 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 376500 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6410 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4846 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 439050 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 727042 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5703 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3689 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 424901 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 685160 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2296801 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 115689 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 102800 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 218489 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6410 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 439050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 927328 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5703 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3689 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 424901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 861374 # number of demand (read+write) hits -system.l2c.demand_hits::total 2673301 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6410 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4846 # number of overall hits -system.l2c.overall_hits::cpu0.inst 439050 # number of overall hits -system.l2c.overall_hits::cpu0.data 927328 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5703 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3689 # number of overall hits -system.l2c.overall_hits::cpu1.inst 424901 # number of overall hits -system.l2c.overall_hits::cpu1.data 861374 # number of overall hits -system.l2c.overall_hits::total 2673301 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 64906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 60031 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 124937 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 6479 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 6386 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 12865 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 376689 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 423433 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 800122 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2349 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1944 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 58179 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 178934 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3469 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3479 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 41697 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 188396 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 478447 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 477304 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 163191 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 640495 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2349 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1944 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 58179 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 555623 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3479 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41697 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 611829 # number of demand (read+write) misses -system.l2c.demand_misses::total 1278569 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2349 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1944 # number of overall misses -system.l2c.overall_misses::cpu0.inst 58179 # number of overall misses -system.l2c.overall_misses::cpu0.data 555623 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3479 # number of overall misses -system.l2c.overall_misses::cpu1.inst 41697 # number of overall misses -system.l2c.overall_misses::cpu1.data 611829 # number of overall misses -system.l2c.overall_misses::total 1278569 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2765418 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2765418 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 82685 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 75606 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 158291 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9067 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8790 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17857 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 576975 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 599647 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1176622 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8759 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6790 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 905976 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9172 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7168 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 466598 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 873556 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2775248 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 592993 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 265991 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 858984 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6790 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1482951 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9172 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7168 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 466598 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1473203 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3951870 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6790 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1482951 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9172 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7168 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 466598 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1473203 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3951870 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784979 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793998 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.789287 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.714569 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726507 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.720446 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.652869 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.706137 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680016 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117006 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.197504 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485352 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089364 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215666 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.172398 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804907 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.613521 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.745643 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.286303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.117006 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.374674 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.485352 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.089364 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.415305 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.323535 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.286303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.117006 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.374674 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.485352 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.089364 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.415305 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.323535 # miss rate for overall accesses +system.l2c.tags.occ_blocks::writebacks 34658.678488 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 33.446161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 43.299197 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3299.237288 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7180.746684 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.688902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 432.688870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2834.364418 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 14654.780551 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.528849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.109569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004161 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006602 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.043249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.223614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.967559 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 232 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58751 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 231 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 463 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3223 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49760 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.896469 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 73267769 # Number of tag accesses +system.l2c.tags.data_accesses 73267769 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2760080 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2760080 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 17858 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15288 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 33146 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2554 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2409 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4963 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 196672 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 175397 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 372069 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6428 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4634 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 441340 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 728132 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5456 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3654 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 420919 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 680845 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2291408 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 115975 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 102728 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 218703 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6428 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4634 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 441340 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 924804 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5456 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3654 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 420919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 856242 # number of demand (read+write) hits +system.l2c.demand_hits::total 2663477 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6428 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4634 # number of overall hits +system.l2c.overall_hits::cpu0.inst 441340 # number of overall hits +system.l2c.overall_hits::cpu0.data 924804 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5456 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3654 # number of overall hits +system.l2c.overall_hits::cpu1.inst 420919 # number of overall hits +system.l2c.overall_hits::cpu1.data 856242 # number of overall hits +system.l2c.overall_hits::total 2663477 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 65292 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 60363 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 125655 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 6568 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 6268 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 12836 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 377580 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 423134 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 800714 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2366 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1943 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 57862 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 180178 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3474 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3458 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 41366 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 189464 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 480111 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 478573 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 160244 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 638817 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1943 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 57862 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 557758 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3474 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3458 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 612598 # number of demand (read+write) misses +system.l2c.demand_misses::total 1280825 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2366 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1943 # number of overall misses +system.l2c.overall_misses::cpu0.inst 57862 # number of overall misses +system.l2c.overall_misses::cpu0.data 557758 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3474 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3458 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41366 # number of overall misses +system.l2c.overall_misses::cpu1.data 612598 # number of overall misses +system.l2c.overall_misses::total 1280825 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2760080 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2760080 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 83150 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 75651 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 158801 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9122 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8677 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17799 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 574252 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 598531 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1172783 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8794 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6577 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 499202 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 908310 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8930 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7112 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 462285 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 870309 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2771519 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 594548 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 262972 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 857520 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8794 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 499202 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1482562 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8930 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7112 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 462285 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1468840 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3944302 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8794 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 499202 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1482562 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8930 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7112 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 462285 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1468840 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3944302 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785232 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.797914 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.791273 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.720018 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.722369 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.721164 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.657516 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.706954 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.682747 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.295423 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.115909 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198366 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.486220 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089482 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.217697 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.173230 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804936 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.609358 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.744959 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.295423 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.115909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.376212 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.486220 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.089482 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.417062 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.324728 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.295423 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.115909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.376212 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.486220 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.089482 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.417062 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.324728 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1477304 # number of writebacks -system.l2c.writebacks::total 1477304 # number of writebacks -system.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1478540 # number of writebacks +system.l2c.writebacks::total 1478540 # number of writebacks +system.membus.snoop_filter.tot_requests 4495065 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2597713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3483 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 82119 # Transaction distribution -system.membus.trans_dist::ReadResp 569484 # Transaction distribution -system.membus.trans_dist::WriteReq 38800 # Transaction distribution -system.membus.trans_dist::WriteResp 38800 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution -system.membus.trans_dist::CleanEvict 246737 # Transaction distribution -system.membus.trans_dist::UpgradeReq 335468 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution -system.membus.trans_dist::UpgradeResp 157952 # Transaction distribution -system.membus.trans_dist::ReadExReq 787861 # Transaction distribution -system.membus.trans_dist::ReadExResp 784470 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 487365 # Transaction distribution -system.membus.trans_dist::InvalidateReq 742728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 742728 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 82130 # Transaction distribution +system.membus.trans_dist::ReadResp 571159 # Transaction distribution +system.membus.trans_dist::WriteReq 38798 # Transaction distribution +system.membus.trans_dist::WriteResp 38798 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1585234 # Transaction distribution +system.membus.trans_dist::CleanEvict 247687 # Transaction distribution +system.membus.trans_dist::UpgradeReq 337993 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306149 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159131 # Transaction distribution +system.membus.trans_dist::ReadExReq 787924 # Transaction distribution +system.membus.trans_dist::ReadExResp 784573 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 489029 # Transaction distribution +system.membus.trans_dist::InvalidateReq 741049 # Transaction distribution +system.membus.trans_dist::InvalidateResp 741049 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6408698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6558890 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6413605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6563815 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6905778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6910703 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175567900 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 175778835 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175760092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 175971063 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 183178003 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 183370231 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4612344 # Request fanout histogram -system.membus.snoop_fanout::mean 0.007156 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.084293 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 4615993 # Request fanout histogram +system.membus.snoop_fanout::mean 0.007281 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.085020 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram -system.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4582382 99.27% 99.27% # Request fanout histogram +system.membus.snoop_fanout::1 33611 0.73% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4612344 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4615993 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1608,11 +1612,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1641,67 +1645,68 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 660932 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1356975 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1356975 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3459973 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 858984 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 858984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9470177 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8222341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17692518 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254644772 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231031359 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 485676131 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1806287 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13039342 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.283997 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.453251 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 11098491 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5714084 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1638499 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 134977 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 121387 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 13590 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3539371 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 2760080 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2007636 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 350499 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 311112 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 661611 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1354403 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1354403 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3457239 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 857520 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 857520 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9497179 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8173943 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17671122 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255360528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229634423 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 484994951 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1809010 # Total snoops (count) +system.toL2Bus.snoopTraffic 94667072 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 13026748 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.284748 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.453600 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9349855 71.70% 71.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3675839 28.19% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 13648 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9330997 71.63% 71.63% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3682161 28.27% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 13590 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13039342 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13026748 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal index 251986706..8c0552b36 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal @@ -91,7 +91,7 @@ [ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.143451] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.143452] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.143453] pci_bus 0000:00: scanning bus
[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
@@ -100,7 +100,7 @@ [ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.143482] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.143483] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.143503] pci_bus 0000:00: fixups for bus
@@ -130,17 +130,17 @@ [ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.144382] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290388] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290389] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290387] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290388] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290395] ata1.00: configured for UDMA/33
-[ 2.290412] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.290466] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.290469] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.290411] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.290465] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.290468] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.290486] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.290493] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.290548] sda: sda1
-[ 2.290610] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.290485] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.290492] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.290547] sda: sda1
+[ 2.290609] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
@@ -158,9 +158,9 @@ [ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.446371] udevd[609]: starting version 182
+[ 2.446370] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.521978] random: dd urandom read with 17 bits of entropy available
+[ 2.521984] random: dd urandom read with 17 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.620600] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.620646] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini index 78dc4998c..d912070c6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -168,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -192,9 +219,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -208,9 +240,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -246,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -305,9 +351,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -321,9 +372,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -334,13 +390,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -359,8 +419,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -368,9 +433,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -415,9 +486,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -431,13 +507,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -456,8 +536,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -465,9 +550,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -481,11 +572,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -501,11 +597,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -520,10 +621,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -604,14 +710,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -620,13 +731,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -636,6 +752,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -706,10 +823,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -789,17 +911,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -825,12 +952,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -838,14 +971,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -931,14 +1069,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -947,13 +1090,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -962,13 +1110,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -976,11 +1129,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -994,11 +1152,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1012,19 +1175,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1070,14 +1239,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1086,11 +1270,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1100,21 +1289,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1124,12 +1323,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1138,10 +1342,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1151,12 +1360,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1166,26 +1380,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1194,10 +1418,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1205,10 +1434,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1216,21 +1450,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1244,11 +1488,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1259,11 +1508,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1271,10 +1525,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr index a78b01f0e..3c9ae873c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simerr @@ -2,6 +2,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout index 7ce5547c3..a995dd49e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 14:02:50 -gem5 executing on e104799-lin, pid 13724 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:53:59 +gem5 executing on e108600-lin, pid 23916 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51111152682000 because m5_exit instruction encountered +Exiting @ tick 51111167192000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 95caaea31..e11d9e780 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167216500 # Number of ticks simulated -final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 51111167192000 # Number of ticks simulated +final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 967952 # Simulator instruction rate (inst/s) -host_op_rate 1137552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50369548013 # Simulator tick rate (ticks/s) -host_mem_usage 676592 # Number of bytes of host memory used -host_seconds 1014.72 # Real time elapsed on the host -sim_insts 982203438 # Number of instructions simulated -sim_ops 1154301153 # Number of ops (including micro ops) simulated +host_inst_rate 779536 # Simulator instruction rate (inst/s) +host_op_rate 916124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40565130498 # Simulator tick rate (ticks/s) +host_mem_usage 670816 # Number of bytes of host memory used +host_seconds 1259.98 # Real time elapsed on the host +sim_insts 982198638 # Number of instructions simulated +sim_ops 1154296340 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory +system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory +system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,7 +109,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 266586 # Table walker walks requested system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency @@ -118,8 +118,8 @@ system.cpu.dtb.walker.walkWaitTime::total 266586 # T system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -130,10 +130,10 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183545125 # DTB read hits -system.cpu.dtb.read_misses 195347 # DTB read misses -system.cpu.dtb.write_hits 167774776 # DTB write hits -system.cpu.dtb.write_misses 71239 # DTB write misses +system.cpu.dtb.read_hits 183544097 # DTB read hits +system.cpu.dtb.read_misses 195348 # DTB read misses +system.cpu.dtb.write_hits 167774773 # DTB write hits +system.cpu.dtb.write_misses 71238 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID @@ -143,13 +143,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183740472 # DTB read accesses -system.cpu.dtb.write_accesses 167846015 # DTB write accesses +system.cpu.dtb.read_accesses 183739445 # DTB read accesses +system.cpu.dtb.write_accesses 167846011 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351319901 # DTB hits +system.cpu.dtb.hits 351318870 # DTB hits system.cpu.dtb.misses 266586 # DTB misses -system.cpu.dtb.accesses 351586487 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 351585456 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 126834 # Table walker walks requested system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency @@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 982680284 # ITB inst hits +system.cpu.itb.inst_hits 982675484 # ITB inst hits system.cpu.itb.inst_misses 126834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -215,14 +215,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982807118 # ITB inst accesses -system.cpu.itb.hits 982680284 # DTB hits +system.cpu.itb.inst_accesses 982802318 # ITB inst accesses +system.cpu.itb.hits 982675484 # DTB hits system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982807118 # DTB accesses +system.cpu.itb.accesses 982802318 # DTB accesses system.cpu.numPwrStateTransitions 33550 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state @@ -234,41 +234,41 @@ system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 102222351209 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 102222351160 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 982203438 # Number of instructions committed -system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses +system.cpu.committedInsts 982198638 # Number of instructions committed +system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56834581 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057882257 # number of integer instructions +system.cpu.num_func_calls 56833909 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls +system.cpu.num_int_insts 1057877800 # number of integer instructions system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read -system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written +system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read +system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written -system.cpu.num_mem_refs 351539335 # number of memory refs -system.cpu.num_load_insts 183712430 # Number of load instructions -system.cpu.num_store_insts 167826905 # Number of store instructions -system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles -system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles +system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written +system.cpu.num_mem_refs 351538306 # number of memory refs +system.cpu.num_load_insts 183711405 # Number of load instructions +system.cpu.num_store_insts 167826901 # Number of store instructions +system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles +system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219534054 # Number of branches fetched +system.cpu.Branches 219532347 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction +system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction @@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154935820 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11606642 # number of replacements +system.cpu.op_class::total 1154931007 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11605970 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -316,88 +316,88 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits -system.cpu.dcache.overall_hits::total 330945053 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits +system.cpu.dcache.overall_hits::total 330944693 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses -system.cpu.dcache.overall_misses::total 11404487 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses +system.cpu.dcache.overall_misses::total 11403820 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks -system.cpu.dcache.writebacks::total 8917390 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14265253 # number of replacements +system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks +system.cpu.dcache.writebacks::total 8916642 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14265273 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy @@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 184 system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits -system.cpu.icache.overall_hits::total 968529210 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses -system.cpu.icache.overall_misses::total 14265770 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses +system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits +system.cpu.icache.overall_hits::total 968524390 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses +system.cpu.icache.overall_misses::total 14265790 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses @@ -439,199 +439,200 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks -system.cpu.icache.writebacks::total 14265253 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1725806 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1788825 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # 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miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks -system.cpu.l2cache.writebacks::total 1507080 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks +system.cpu.l2cache.writebacks::total 1507088 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1957577 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1957594 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40242 # Transaction distribution system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -674,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy @@ -691,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039650 # Number of tag accesses system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses @@ -739,64 +740,65 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524946 # Transaction distribution +system.membus.trans_dist::ReadResp 524962 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution -system.membus.trans_dist::CleanEvict 226320 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution +system.membus.trans_dist::CleanEvict 226329 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution -system.membus.trans_dist::ReadExReq 827042 # Transaction distribution -system.membus.trans_dist::ReadExResp 827042 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution +system.membus.trans_dist::ReadExReq 827052 # Transaction distribution +system.membus.trans_dist::ReadExResp 827052 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3924997 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 3925032 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3924997 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 3925032 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -839,28 +841,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal index 7a2b5d086..e00102254 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/system.terminal @@ -77,7 +77,7 @@ [ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131281] NET: Registered protocol family 1
-[ 3.131310] RPC: Registered named UNIX socket transport module.
+[ 3.131311] RPC: Registered named UNIX socket transport module.
[ 3.131311] RPC: Registered udp transport module.
[ 3.131312] RPC: Registered tcp transport module.
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
@@ -87,7 +87,7 @@ [ 3.132687] fuse init (API version 7.23)
[ 3.132738] msgmni has been set to 469
[ 3.133992] io scheduler noop registered
-[ 3.134024] io scheduler cfq registered (default)
+[ 3.134025] io scheduler cfq registered (default)
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
@@ -98,24 +98,24 @@ [ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134354] pci_bus 0000:00: fixups for bus
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
-[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
@@ -158,9 +158,9 @@ [ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.446951] udevd[607]: starting version 182
+[ 3.446950] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.532266] random: dd urandom read with 19 bits of entropy available
+[ 3.532262] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini index 2e70349df..2a00a6a90 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -24,12 +25,12 @@ exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -59,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -87,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -105,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +135,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -140,12 +157,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -164,8 +186,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -188,9 +215,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -204,9 +236,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -217,12 +254,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -241,8 +283,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -300,9 +347,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -316,9 +368,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -329,12 +386,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -352,6 +414,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -362,6 +425,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -378,8 +445,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -387,10 +459,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -418,6 +495,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -435,6 +513,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -453,12 +535,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -477,8 +564,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -501,9 +593,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -517,9 +614,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -530,12 +632,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -554,8 +661,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -613,9 +725,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -629,9 +746,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -642,12 +764,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -665,6 +792,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -675,6 +803,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -691,8 +823,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -700,10 +837,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -748,9 +890,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -764,12 +911,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -788,8 +940,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -800,12 +957,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -824,21 +986,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -850,11 +1022,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -865,6 +1042,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -899,6 +1083,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -910,7 +1095,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -953,10 +1142,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1037,14 +1231,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1053,13 +1252,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1069,6 +1273,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1139,10 +1344,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1222,17 +1432,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1258,12 +1473,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1271,14 +1492,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1364,14 +1590,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1380,13 +1611,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1395,13 +1631,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1409,11 +1650,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1427,11 +1673,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1445,19 +1696,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1503,14 +1760,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1519,11 +1791,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1533,21 +1810,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1557,12 +1844,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1571,10 +1863,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1584,12 +1881,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1599,26 +1901,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1627,10 +1939,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1638,10 +1955,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1649,21 +1971,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1677,11 +2009,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1692,11 +2029,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1704,10 +2046,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1723,10 +2070,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr index 3c2cf37c0..8786c1b6c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simerr @@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout index f29d24301..c648cad5f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:52:28 -gem5 executing on phenom, pid 15986 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:41:50 +gem5 executing on e108600-lin, pid 23131 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47460623015500 because m5_exit instruction encountered +Exiting @ tick 47403574916500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 7576c0a8a..815a8f351 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.522770 # Number of seconds simulated -sim_ticks 47522770414500 # Number of ticks simulated -final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.403575 # Number of seconds simulated +sim_ticks 47403574916500 # Number of ticks simulated +final_tick 47403574916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594104 # Simulator instruction rate (inst/s) -host_op_rate 698838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32027606991 # Simulator tick rate (ticks/s) -host_mem_usage 752504 # Number of bytes of host memory used -host_seconds 1483.81 # Real time elapsed on the host -sim_insts 881535802 # Number of instructions simulated -sim_ops 1036940641 # Number of ops (including micro ops) simulated +host_inst_rate 473223 # Simulator instruction rate (inst/s) +host_op_rate 556671 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25492174892 # Simulator tick rate (ticks/s) +host_mem_usage 749540 # Number of bytes of host memory used +host_seconds 1859.53 # Real time elapsed on the host +sim_insts 879974755 # Number of instructions simulated +sim_ops 1035148021 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9313680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12080896 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 425472 # Number of bytes read from this memory -system.physmem.bytes_read::total 56631876 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3323828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2499960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5823788 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75221696 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 121792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3082292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13718664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15413504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 111872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 105344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2806840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9358928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11301824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428736 # Number of bytes read from this memory +system.physmem.bytes_read::total 56576516 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3082292 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2806840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5889132 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75184384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75242280 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1465 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1507 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 92342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 215816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 229901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2146 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2116 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 145539 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 188764 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6648 # Number of read requests responded to by this memory -system.physmem.num_reads::total 925394 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1175339 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75204968 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1903 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 88568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 214367 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 240836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 43945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 146246 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 176591 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6699 # Number of read requests responded to by this memory +system.physmem.num_reads::total 924529 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1174756 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1177913 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 69942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 290627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 309613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 195984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 254213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1191679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 122547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1582856 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1177330 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 65022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 289401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 325155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 197431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 238417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1193507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 65022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 124234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1586049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1583289 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1582856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 291060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 309613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 195984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 254213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2774968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 925394 # Number of read requests accepted -system.physmem.writeReqs 1177913 # Number of write requests accepted -system.physmem.readBursts 925394 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1177913 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59200512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24704 # Total number of bytes read from write queue -system.physmem.bytesWritten 75241664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56631876 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75242280 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 386 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1586483 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1586049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 65022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 289836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 325155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 197431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 238417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2779990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 924529 # Number of read requests accepted +system.physmem.writeReqs 1177330 # Number of write requests accepted +system.physmem.readBursts 924529 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1177330 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59142848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27008 # Total number of bytes read from write queue +system.physmem.bytesWritten 75203008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56576516 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75204968 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 422 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2259 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 52385 # Per bank write bursts -system.physmem.perBankRdBursts::1 62471 # Per bank write bursts -system.physmem.perBankRdBursts::2 52469 # Per bank write bursts -system.physmem.perBankRdBursts::3 57006 # Per bank write bursts -system.physmem.perBankRdBursts::4 52192 # Per bank write bursts -system.physmem.perBankRdBursts::5 61065 # Per bank write bursts -system.physmem.perBankRdBursts::6 52770 # Per bank write bursts -system.physmem.perBankRdBursts::7 53841 # Per bank write bursts -system.physmem.perBankRdBursts::8 49119 # Per bank write bursts -system.physmem.perBankRdBursts::9 95933 # Per bank write bursts -system.physmem.perBankRdBursts::10 50791 # Per bank write bursts -system.physmem.perBankRdBursts::11 57135 # Per bank write bursts -system.physmem.perBankRdBursts::12 57588 # Per bank write bursts -system.physmem.perBankRdBursts::13 62036 # Per bank write bursts -system.physmem.perBankRdBursts::14 54549 # Per bank write bursts -system.physmem.perBankRdBursts::15 53658 # Per bank write bursts -system.physmem.perBankWrBursts::0 70290 # Per bank write bursts -system.physmem.perBankWrBursts::1 77699 # Per bank write bursts -system.physmem.perBankWrBursts::2 70837 # Per bank write bursts -system.physmem.perBankWrBursts::3 75524 # Per bank write bursts -system.physmem.perBankWrBursts::4 70767 # Per bank write bursts -system.physmem.perBankWrBursts::5 75365 # Per bank write bursts -system.physmem.perBankWrBursts::6 70544 # Per bank write bursts -system.physmem.perBankWrBursts::7 72537 # Per bank write bursts -system.physmem.perBankWrBursts::8 71114 # Per bank write bursts -system.physmem.perBankWrBursts::9 74364 # Per bank write bursts -system.physmem.perBankWrBursts::10 70757 # Per bank write bursts -system.physmem.perBankWrBursts::11 75591 # Per bank write bursts -system.physmem.perBankWrBursts::12 74466 # Per bank write bursts -system.physmem.perBankWrBursts::13 78806 # Per bank write bursts -system.physmem.perBankWrBursts::14 73579 # Per bank write bursts -system.physmem.perBankWrBursts::15 73411 # Per bank write bursts +system.physmem.perBankRdBursts::0 51848 # Per bank write bursts +system.physmem.perBankRdBursts::1 60547 # Per bank write bursts +system.physmem.perBankRdBursts::2 52943 # Per bank write bursts +system.physmem.perBankRdBursts::3 59873 # Per bank write bursts +system.physmem.perBankRdBursts::4 53995 # Per bank write bursts +system.physmem.perBankRdBursts::5 59394 # Per bank write bursts +system.physmem.perBankRdBursts::6 55656 # Per bank write bursts +system.physmem.perBankRdBursts::7 56350 # Per bank write bursts +system.physmem.perBankRdBursts::8 47470 # Per bank write bursts +system.physmem.perBankRdBursts::9 98045 # Per bank write bursts +system.physmem.perBankRdBursts::10 51346 # Per bank write bursts +system.physmem.perBankRdBursts::11 58216 # Per bank write bursts +system.physmem.perBankRdBursts::12 52575 # Per bank write bursts +system.physmem.perBankRdBursts::13 60842 # Per bank write bursts +system.physmem.perBankRdBursts::14 50185 # Per bank write bursts +system.physmem.perBankRdBursts::15 54822 # Per bank write bursts +system.physmem.perBankWrBursts::0 69717 # Per bank write bursts +system.physmem.perBankWrBursts::1 76530 # Per bank write bursts +system.physmem.perBankWrBursts::2 71410 # Per bank write bursts +system.physmem.perBankWrBursts::3 77292 # Per bank write bursts +system.physmem.perBankWrBursts::4 71372 # Per bank write bursts +system.physmem.perBankWrBursts::5 75019 # Per bank write bursts +system.physmem.perBankWrBursts::6 75211 # Per bank write bursts +system.physmem.perBankWrBursts::7 75617 # Per bank write bursts +system.physmem.perBankWrBursts::8 67898 # Per bank write bursts +system.physmem.perBankWrBursts::9 76939 # Per bank write bursts +system.physmem.perBankWrBursts::10 70016 # Per bank write bursts +system.physmem.perBankWrBursts::11 75357 # Per bank write bursts +system.physmem.perBankWrBursts::12 71664 # Per bank write bursts +system.physmem.perBankWrBursts::13 78615 # Per bank write bursts +system.physmem.perBankWrBursts::14 70257 # Per bank write bursts +system.physmem.perBankWrBursts::15 72133 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 43 # Number of times write queue was full causing retry -system.physmem.totGap 47522767065000 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 47403571626000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 882169 # Read request sizes (log2) +system.physmem.readPktSize::6 881304 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1175339 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 655692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 79783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28749 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1174756 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 659566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 77579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 24996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 21849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -189,171 +189,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 73364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 73677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 78266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 71127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 65923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 971842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 138.337154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 95.235739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 185.809364 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 667325 68.67% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 188611 19.41% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42123 4.33% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19056 1.96% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13469 1.39% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8562 0.88% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6056 0.62% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5131 0.53% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21509 2.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 971842 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61007 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.162244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.580515 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61004 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 31459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 50403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 77625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 73262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 73463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 77885 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 970623 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 138.411655 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 95.318742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 185.703174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 665453 68.56% 68.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189210 19.49% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 42199 4.35% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19114 1.97% 94.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13470 1.39% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8660 0.89% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6031 0.62% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4990 0.51% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21496 2.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 970623 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60964 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.158028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.577791 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60961 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61007 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61007 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.270756 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.528593 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.773323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49057 80.41% 80.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4844 7.94% 88.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2913 4.77% 93.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1752 2.87% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 961 1.58% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 299 0.49% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 177 0.29% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 148 0.24% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 74 0.12% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 52 0.09% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 27 0.04% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.09% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 405 0.66% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 51 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 50 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 25 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60964 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60964 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.274441 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.533375 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.742081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49066 80.48% 80.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4709 7.72% 88.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2977 4.88% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1753 2.88% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 988 1.62% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 316 0.52% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 174 0.29% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 124 0.20% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 67 0.11% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 44 0.07% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 37 0.06% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 48 0.08% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 425 0.70% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 48 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 48 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 40 0.07% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 26 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61007 # Writes before turning the bus around for reads -system.physmem.totQLat 29196891613 # Total ticks spent queuing -system.physmem.totMemAccLat 46540791613 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4625040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31563.93 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 10 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60964 # Writes before turning the bus around for reads +system.physmem.totQLat 29056215697 # Total ticks spent queuing +system.physmem.totMemAccLat 46383221947 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4620535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31442.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50313.93 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 50192.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 690198 # Number of row buffer hits during reads -system.physmem.writeRowHits 438618 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.31 # Row buffer hit rate for writes -system.physmem.avgGap 22594308.42 # Average gap between requests -system.physmem.pageHitRate 53.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3631876920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1981678875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3464752200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3781488240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1186873055955 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27472545160500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31776234305010 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.652826 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45702691627494 # Time in different power states -system.physmem_0.memoryStateTime::REF 1586889720000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.95 # Average write queue length when enqueuing +system.physmem.readRowHits 688543 # Number of row buffer hits during reads +system.physmem.writeRowHits 439987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.44 # Row buffer hit rate for writes +system.physmem.avgGap 22553164.43 # Average gap between requests +system.physmem.pageHitRate 53.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3707333280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2022850500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3514687800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3837248640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1188225117900 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27399839328750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31697317314150 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.669411 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45581711195731 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582909380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 233188460006 # Time in different power states +system.physmem_0.memoryStateTime::ACT 238953890769 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3715248600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2027169375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3750271200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3836730240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1194406095015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.682174 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states -system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states +system.physmem_1.actEnergy 3630576600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1980969375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3693307800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3777055920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1193695955100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27395040340500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31697988952575 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683580 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45573641620138 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582909380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states +system.physmem_1.memoryStateTime::ACT 247019106112 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -380,9 +378,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -390,7 +388,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -420,75 +418,75 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 111522 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 111497 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 114038 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 114038 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12642 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85549 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 114019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.228032 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 76.998938 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 114018 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 111498 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 96090 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22204.527006 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20954.891968 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12694.708371 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 91679 95.41% 95.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3478 3.62% 99.03% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 141 0.15% 99.18% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 658 0.68% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 14 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 23 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 114019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 98210 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 93486 95.19% 95.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3452 3.51% 98.70% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 155 0.16% 98.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 934 0.95% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 20 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 48 0.05% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 37 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 30 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 96090 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 2194735056 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.089935 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -197382796 -8.99% -8.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 2392117852 108.99% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 2194735056 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84024 87.46% 87.46% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12043 12.54% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 96067 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111522 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 98210 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 3576910072 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.522403 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -1868589580 -52.24% -52.24% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 5445499652 152.24% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 3576910072 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 85549 87.13% 87.13% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12642 12.87% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 98191 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 114038 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111522 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96067 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 114038 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 98191 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96067 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 207589 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 98191 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 212229 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86856517 # DTB read hits -system.cpu0.dtb.read_misses 84644 # DTB read misses -system.cpu0.dtb.write_hits 78666499 # DTB write hits -system.cpu0.dtb.write_misses 26878 # DTB write misses +system.cpu0.dtb.read_hits 86092375 # DTB read hits +system.cpu0.dtb.read_misses 87013 # DTB read misses +system.cpu0.dtb.write_hits 77928513 # DTB write hits +system.cpu0.dtb.write_misses 27025 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37412 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 38112 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4351 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86941161 # DTB read accesses -system.cpu0.dtb.write_accesses 78693377 # DTB write accesses +system.cpu0.dtb.perms_faults 9561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86179388 # DTB read accesses +system.cpu0.dtb.write_accesses 77955538 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165523016 # DTB hits -system.cpu0.dtb.misses 111522 # DTB misses -system.cpu0.dtb.accesses 165634538 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 164020888 # DTB hits +system.cpu0.dtb.misses 114038 # DTB misses +system.cpu0.dtb.accesses 164134926 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -518,886 +516,891 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 57441 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 24992.593377 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23133.831517 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17289.167601 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 50947 98.14% 98.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 829 1.60% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 33 0.06% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 45 0.09% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 51913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 57747 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57747 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51498 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57747 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57747 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57747 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52059 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48075 92.35% 92.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2753 5.29% 97.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 34 0.07% 97.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 1024 1.97% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 15 0.03% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 43 0.08% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 19 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 37 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 21 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52059 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51280 98.78% 98.78% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 633 1.22% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 51913 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 51498 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 561 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52059 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57441 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57441 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57747 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57747 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51913 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51913 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 109354 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 461199865 # ITB inst hits -system.cpu0.itb.inst_misses 57441 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52059 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52059 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 109806 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 458544228 # ITB inst hits +system.cpu0.itb.inst_misses 57747 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26562 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 26949 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses -system.cpu0.itb.hits 461199865 # DTB hits -system.cpu0.itb.misses 57441 # DTB misses -system.cpu0.itb.accesses 461257306 # DTB accesses -system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 95045540829 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 458601975 # ITB inst accesses +system.cpu0.itb.hits 458544228 # DTB hits +system.cpu0.itb.misses 57747 # DTB misses +system.cpu0.itb.accesses 458601975 # DTB accesses +system.cpu0.numPwrStateTransitions 27516 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13758 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3404463734.886103 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 97180881292.374130 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3759 27.32% 27.32% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9972 72.48% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.09% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7033293879000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13758 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 564962851937 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94807149833 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed -system.cpu0.committedInsts 460929213 # Number of instructions committed -system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 434558 # Number of float alu accesses -system.cpu0.num_func_calls 27781850 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69589132 # number of instructions that are conditional controls -system.cpu0.num_int_insts 497492129 # number of integer instructions -system.cpu0.num_fp_insts 434558 # number of float instructions -system.cpu0.num_int_register_reads 719293830 # number of times the integer registers were read -system.cpu0.num_int_register_writes 394367415 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 718787 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 331792 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119457726 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119087316 # number of times the CC registers were written -system.cpu0.num_mem_refs 165514046 # number of memory refs -system.cpu0.num_load_insts 86852092 # Number of load instructions -system.cpu0.num_store_insts 78661954 # Number of store instructions -system.cpu0.num_idle_cycles 93905101360.384018 # Number of idle cycles -system.cpu0.num_busy_cycles 1140439468.615976 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011999 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988001 # Percentage of idle cycles -system.cpu0.Branches 102755128 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 374676211 69.19% 69.19% # Class of executed instruction -system.cpu0.op_class::IntMult 1194745 0.22% 69.41% # Class of executed instruction -system.cpu0.op_class::IntDiv 63344 0.01% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 45411 0.01% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 13758 # number of quiesce instructions executed +system.cpu0.committedInsts 458270897 # Number of instructions committed +system.cpu0.committedOps 538093671 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 494447989 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 420942 # Number of float alu accesses +system.cpu0.num_func_calls 27507374 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 69395953 # number of instructions that are conditional controls +system.cpu0.num_int_insts 494447989 # number of integer instructions +system.cpu0.num_fp_insts 420942 # number of float instructions +system.cpu0.num_int_register_reads 717601691 # number of times the integer registers were read +system.cpu0.num_int_register_writes 392303230 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 699105 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 312628 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 119518995 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 119177994 # number of times the CC registers were written +system.cpu0.num_mem_refs 164010919 # number of memory refs +system.cpu0.num_load_insts 86087147 # Number of load instructions +system.cpu0.num_store_insts 77923772 # Number of store instructions +system.cpu0.num_idle_cycles 93677224129.124023 # Number of idle cycles +system.cpu0.num_busy_cycles 1129925703.875976 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011918 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988082 # Percentage of idle cycles +system.cpu0.Branches 102213618 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 373117768 69.30% 69.30% # Class of executed instruction +system.cpu0.op_class::IntMult 1177948 0.22% 69.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 60910 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 42581 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 86087147 15.99% 85.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 77923772 14.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 541493758 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5689621 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks. +system.cpu0.op_class::total 538410126 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5755741 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.832715 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 158017240 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5756252 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.451411 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1824290 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1824290 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1791894 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1791894 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155334822 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155334822 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155534211 # number of overall hits -system.cpu0.dcache.overall_hits::total 155534211 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3104051 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3104051 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1401631 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1401631 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634089 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 634089 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792659 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 792659 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174131 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 174131 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 205146 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 205146 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5298341 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5298341 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5932430 # number of overall misses -system.cpu0.dcache.overall_misses::total 5932430 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46355544000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 46355544000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29179707500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29179707500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25804948000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25804948000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2634324500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2634324500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5093103500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5093103500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3129500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3129500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 101340199500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 101340199500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 101340199500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 101340199500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83997021 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83997021 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75681254 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75681254 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 833478 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 833478 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954888 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 954888 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998421 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1998421 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1997040 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1997040 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160633163 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 160633163 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161466641 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 161466641 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036954 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018520 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018520 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760775 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760775 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.830107 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.830107 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087134 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087134 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102725 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102725 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032984 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036741 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036741 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14933.886073 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.886073 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20818.394784 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20818.394784 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32554.917058 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32554.917058 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15128.406200 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15128.406200 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24826.725844 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24826.725844 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.832715 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921548 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.921548 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 333769183 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 333769183 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 80089936 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80089936 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73524451 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73524451 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195750 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 195750 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 158273 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 158273 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1825906 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1825906 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1807959 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1807959 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153772660 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153772660 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153968410 # number of overall hits +system.cpu0.dcache.overall_hits::total 153968410 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3122111 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3122111 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1430717 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1430717 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657703 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 657703 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 783281 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 783281 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173414 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 173414 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190134 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 190134 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5336109 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5336109 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5993812 # number of overall misses +system.cpu0.dcache.overall_misses::total 5993812 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46238724000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 46238724000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29544894000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29544894000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25637315000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25637315000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2487014500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2487014500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4740803500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4740803500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2810500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2810500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 101420933000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 101420933000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83212047 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83212047 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74955168 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74955168 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853453 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 853453 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 941554 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 941554 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1999320 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1999320 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1998093 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1998093 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 159108769 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 159108769 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 159962222 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 159962222 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019088 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019088 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770638 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770638 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.831902 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.831902 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086736 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086736 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033537 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033537 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037470 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037470 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19126.779401 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19126.779401 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17082.409653 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17082.409653 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5689621 # number of writebacks -system.cpu0.dcache.writebacks::total 5689621 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25484 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25484 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21272 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21272 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45280 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45280 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 46756 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 46756 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 46756 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 46756 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3078567 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3078567 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380359 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1380359 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 632927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 632927 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792659 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 792659 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128851 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128851 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 205146 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 205146 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5251585 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5251585 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5884512 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5884512 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27617 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54182 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42188847000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42188847000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27459987000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27459987000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13648405000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13648405000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25012289000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25012289000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1718421000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1718421000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4888014500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4888014500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3072500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3072500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94661123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 94661123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108309528000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 108309528000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5072174500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5072174500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5072174500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5072174500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036651 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036651 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018239 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759381 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759381 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830107 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830107 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064476 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064476 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102725 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102725 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032693 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032693 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036444 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036444 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13704.053542 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13704.053542 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19893.366146 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19893.366146 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21563.948133 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21563.948133 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31554.917058 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31554.917058 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13336.497194 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.497194 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23827.003695 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23827.003695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5755741 # number of writebacks +system.cpu0.dcache.writebacks::total 5755741 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25545 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25545 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21233 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21233 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44607 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44607 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 46778 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 46778 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 46778 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 46778 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3096566 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3096566 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1409484 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1409484 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656541 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 656541 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 783281 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 783281 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128807 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128807 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190134 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 190134 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5289331 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5289331 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5945872 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5945872 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54115 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42074729000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42074729000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27794776000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27794776000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13747691500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13747691500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24854034000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24854034000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1645535500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1645535500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4550721500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4550721500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2758500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2758500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94723539000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 94723539000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5071681500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5071681500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5071681500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5071681500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037213 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037213 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769276 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.769276 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.831902 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.831902 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064425 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064425 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095158 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095158 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033243 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037170 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.037170 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5142905 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks. +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4916262 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.907947 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 453627454 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4916774 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 92.261197 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907947 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits -system.cpu0.icache.overall_hits::total 456056448 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5143417 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5143417 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5143417 # number of overall misses -system.cpu0.icache.overall_misses::total 5143417 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54463305000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 54463305000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 54463305000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 54463305000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 54463305000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 54463305000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 461199865 # 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miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10588.934360 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10588.934360 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10588.934360 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10588.934360 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 922005230 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 922005230 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 453627454 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 453627454 # 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number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 52276659500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 52276659500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 52276659500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 52276659500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 458544228 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 458544228 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 458544228 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 458544228 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 458544228 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 458544228 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010723 # 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number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5143417 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5143417 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 4916262 # number of writebacks +system.cpu0.icache.writebacks::total 4916262 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4916774 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4916774 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4916774 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4916774 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4916774 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4916774 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51891596500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 51891596500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51891596500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 51891596500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51891596500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 51891596500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 49818272500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 49818272500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 49818272500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 49818272500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 49818272500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 49818272500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011152 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010723 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010723 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010723 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10132.308807 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7829609 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7829625 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2348165 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2364235 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.485817 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1043159 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2362641 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16162.227513 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 14986861 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2378231 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.301684 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15208.455915 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.858641 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.489283 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 784.884937 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.928250 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003776 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004852 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047906 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984783 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14708 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 179 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 589 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 529 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4517 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3841 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346781000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850886500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346919000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039214 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850748500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346781000 # 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mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212561 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212561 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089571 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.244101 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244101 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730498 # 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mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208334 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208334 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092312 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.237547 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237547 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734749 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734749 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157547 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225203 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30740.646006 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45077.596675 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.248301 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20773.248301 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16322.336666 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16322.336666 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 330625 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 330625 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43135.713443 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43135.713443 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28827.661168 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29046.893485 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29046.893485 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32766.637985 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32766.637985 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31087.443131 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35316.144748 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229341 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175648.567911 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117990.995448 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 441648 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 374962 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 517397 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1188175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1165072 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5143417 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4741538 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 839102 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 790706 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15515989 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18442402 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326965 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 595128 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34880484 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 658497108 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690726071 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1243360 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2186248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1352652787 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6279047 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 18012222 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.113865 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.317693 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 22110497 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11343995 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 879 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1795730 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1795410 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 572087 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9462372 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26540 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26540 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5352908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6850414 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2268094 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 917561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 438813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347856 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 497865 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1218452 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1195725 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4916774 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4752404 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 832834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 781464 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14836060 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18594952 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327877 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 607160 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34366049 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 629486804 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699379029 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1242688 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2226528 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1332335049 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6259200 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 105003768 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 17822799 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.114255 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.318177 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15961520 88.61% 88.61% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2050439 11.38% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 263 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15786774 88.58% 88.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2035705 11.42% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 320 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 18012222 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 22247152499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 17822799 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21920125505 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 190413774 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 184217084 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7418286000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8250668056 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 172541000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 328844000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1427,69 +1430,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 105013 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 105005 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 105006 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 89755 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22913.865523 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21179.498457 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15867.258739 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 88364 98.45% 98.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1205 1.34% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 34 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.08% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 89755 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -3159480544 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.804201 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.396815 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -618623648 19.58% 19.58% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -2540856896 80.42% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -3159480544 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 79078 88.11% 88.11% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10670 11.89% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 89748 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105013 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 102344 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 102344 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10188 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77277 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 102334 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.244298 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 78.150189 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 102333 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 102334 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 87475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 86378 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 960 1.10% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 39 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 87475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -5328755248 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.736470 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.440547 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1404285148 26.35% 26.35% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -3924470100 73.65% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -5328755248 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 77278 88.35% 88.35% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10188 11.65% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 87466 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102344 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105013 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89748 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102344 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87466 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89748 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 194761 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87466 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 189810 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79229823 # DTB read hits -system.cpu1.dtb.read_misses 76992 # DTB read misses -system.cpu1.dtb.write_hits 72255246 # DTB write hits -system.cpu1.dtb.write_misses 28021 # DTB write misses +system.cpu1.dtb.read_hits 79660508 # DTB read hits +system.cpu1.dtb.read_misses 74735 # DTB read misses +system.cpu1.dtb.write_hits 72705787 # DTB write hits +system.cpu1.dtb.write_misses 27609 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37114 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 36374 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4588 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79306815 # DTB read accesses -system.cpu1.dtb.write_accesses 72283267 # DTB write accesses +system.cpu1.dtb.perms_faults 10004 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79735243 # DTB read accesses +system.cpu1.dtb.write_accesses 72733396 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 151485069 # DTB hits -system.cpu1.dtb.misses 105013 # DTB misses -system.cpu1.dtb.accesses 151590082 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 152366295 # DTB hits +system.cpu1.dtb.misses 102344 # DTB misses +system.cpu1.dtb.accesses 152468639 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1519,895 +1522,897 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 58945 # Table walker walks requested -system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26471.741928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23919.780193 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 20610.282304 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 48130 89.77% 89.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4065 7.58% 97.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 53 0.10% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 1140 2.13% 99.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 18 0.03% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 57 0.11% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 51 0.10% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 22 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 16 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 58593 # Table walker walks requested +system.cpu1.itb.walker.walksLong 58593 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 620 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52801 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 58593 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 58593 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 58593 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53421 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47948 89.75% 89.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 4330 8.11% 97.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 49 0.09% 97.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.73% 99.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.05% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 42 0.08% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1503172148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1503172148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1503172148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 53052 98.95% 98.95% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 561 1.05% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53613 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 53421 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1503171148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1503171148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1503171148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 52801 98.84% 98.84% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 620 1.16% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53421 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58945 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58945 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58593 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58593 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 112558 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 420888418 # ITB inst hits -system.cpu1.itb.inst_misses 58945 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 112014 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 421982441 # ITB inst hits +system.cpu1.itb.inst_misses 58593 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25811 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 25297 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses -system.cpu1.itb.hits 420888418 # DTB hits -system.cpu1.itb.misses 58945 # DTB misses -system.cpu1.itb.accesses 420947363 # DTB accesses -system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 95045540824 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 422041034 # ITB inst accesses +system.cpu1.itb.hits 421982441 # DTB hits +system.cpu1.itb.misses 58593 # DTB misses +system.cpu1.itb.accesses 422041034 # DTB accesses +system.cpu1.numPwrStateTransitions 9904 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 4952 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9471329494.171041 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 145765994017.543427 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3395 68.56% 68.56% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1531 30.92% 99.47% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.72% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.28% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7470352176392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 4952 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 501551261365 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94807149833 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed -system.cpu1.committedInsts 420606589 # Number of instructions committed -system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 465343 # Number of float alu accesses -system.cpu1.num_func_calls 25050170 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 64233743 # number of instructions that are conditional controls -system.cpu1.num_int_insts 455422102 # number of integer instructions -system.cpu1.num_fp_insts 465343 # number of float instructions -system.cpu1.num_int_register_reads 665130045 # number of times the integer registers were read -system.cpu1.num_int_register_writes 361560137 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 742394 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 410584 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 110025684 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 109785328 # number of times the CC registers were written -system.cpu1.num_mem_refs 151477231 # number of memory refs -system.cpu1.num_load_insts 79227868 # Number of load instructions -system.cpu1.num_store_insts 72249363 # Number of store instructions -system.cpu1.num_idle_cycles 94048242615.068481 # Number of idle cycles -system.cpu1.num_busy_cycles 997298208.931515 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010493 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989507 # Percentage of idle cycles -system.cpu1.Branches 93889993 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 343412693 69.23% 69.23% # Class of executed instruction -system.cpu1.op_class::IntMult 1029907 0.21% 69.44% # Class of executed instruction -system.cpu1.op_class::IntDiv 56328 0.01% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 66396 0.01% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 4952 # number of quiesce instructions executed +system.cpu1.committedInsts 421703858 # Number of instructions committed +system.cpu1.committedOps 497054350 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 456781482 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 475663 # Number of float alu accesses +system.cpu1.num_func_calls 25188507 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 64210733 # number of instructions that are conditional controls +system.cpu1.num_int_insts 456781482 # number of integer instructions +system.cpu1.num_fp_insts 475663 # number of float instructions +system.cpu1.num_int_register_reads 664763727 # number of times the integer registers were read +system.cpu1.num_int_register_writes 362355133 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 757340 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 426036 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 109701618 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 109432507 # number of times the CC registers were written +system.cpu1.num_mem_refs 152358964 # number of memory refs +system.cpu1.num_load_insts 79658830 # Number of load instructions +system.cpu1.num_store_insts 72700134 # Number of store instructions +system.cpu1.num_idle_cycles 93804047310.268021 # Number of idle cycles +system.cpu1.num_busy_cycles 1003102522.731979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010580 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989420 # Percentage of idle cycles +system.cpu1.Branches 94064671 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 343802607 69.13% 69.13% # Class of executed instruction +system.cpu1.op_class::IntMult 1044362 0.21% 69.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 57840 0.01% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 69226 0.01% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::MemRead 79658830 16.02% 85.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 72700134 14.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 496042597 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5018466 # number of replacements -system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1665176 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1665176 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1621987 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1621987 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 142401211 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 142401211 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 142575772 # number of overall hits -system.cpu1.dcache.overall_hits::total 142575772 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2838030 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2838030 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1310627 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1310627 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 624714 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 624714 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447850 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 447850 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162703 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 162703 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204676 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 204676 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4596507 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4596507 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5221221 # number of overall misses -system.cpu1.dcache.overall_misses::total 5221221 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40862074000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 40862074000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24688918000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 24688918000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10778682000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10778682000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2442456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2442456000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5069864000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5069864000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3108000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3108000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 76329674000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 76329674000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 76329674000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 76329674000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76591652 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76591652 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69796106 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69796106 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799275 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 799275 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 609960 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 609960 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1827879 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1827879 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1826663 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1826663 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 146997718 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146997718 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 147796993 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 147796993 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037054 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037054 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018778 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018778 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.781601 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.781601 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734228 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734228 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089012 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089012 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112049 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112049 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031269 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031269 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035327 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035327 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14398.041599 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14398.041599 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18837.486180 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18837.486180 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24067.616389 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24067.616389 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15011.745327 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15011.745327 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24770.192890 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24770.192890 # average StoreCondReq miss latency +system.cpu1.op_class::total 497333042 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5003393 # number of replacements +system.cpu1.dcache.tags.tagsinuse 453.941998 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 147178696 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5003905 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.412768 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8378733231000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.941998 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886605 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.886605 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 309758535 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 309758535 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 74209320 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74209320 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68941180 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68941180 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175621 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 175621 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 163479 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 163479 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1660182 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1660182 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1630108 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1630108 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 143313979 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 143313979 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 143489600 # number of overall hits +system.cpu1.dcache.overall_hits::total 143489600 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2836392 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2836392 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1297238 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1297238 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 605603 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 605603 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 460373 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 460373 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162387 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 162387 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 191354 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 191354 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4594003 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4594003 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5199606 # number of overall misses +system.cpu1.dcache.overall_misses::total 5199606 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40714366500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 40714366500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24361465000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 24361465000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11037691000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11037691000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2429522000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2429522000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4779056000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4779056000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2991500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2991500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 76113522500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 76113522500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 76113522500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 76113522500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 77045712 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 77045712 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70238418 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70238418 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 781224 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 781224 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 623852 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 623852 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1822569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1822569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1821462 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1821462 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 147907982 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 147907982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 148689206 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 148689206 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036814 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036814 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018469 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018469 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775198 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775198 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.737952 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.737952 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089098 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089098 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105055 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105055 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031060 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031060 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034970 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034970 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16606.017134 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16606.017134 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14619.123381 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14619.123381 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5018466 # number of writebacks -system.cpu1.dcache.writebacks::total 5018466 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16365 # 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number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1310222 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 624714 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 624714 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 447850 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 447850 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204676 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 204676 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4579737 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4579737 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204451 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5204451 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11035 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22984 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37160053500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37160053500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23356658000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23356658000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12967475000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12967475000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10330832000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10330832000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654542500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1654542500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4865246000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4865246000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3050000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3050000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70847543500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 70847543500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83815018500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 83815018500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1894238000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1894238000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1894238000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1894238000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036840 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036840 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018772 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018772 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.781601 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.781601 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734228 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734228 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065945 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065945 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112049 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112049 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031155 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031155 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035214 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035214 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13169.548299 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13169.548299 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17826.488946 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17826.488946 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20757.458613 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20757.458613 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23067.616389 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23067.616389 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13726.086776 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.086776 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23770.476265 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23770.476265 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5003393 # number of writebacks +system.cpu1.dcache.writebacks::total 5003393 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17753 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 17753 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 420 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 420 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44380 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44380 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 18173 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 18173 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 18173 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 18173 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2818639 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2818639 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1296818 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1296818 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 605603 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 605603 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460373 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 460373 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118007 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118007 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 191354 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 191354 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4575830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4575830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5181433 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5181433 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11021 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22945 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36912397500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36912397500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23044975500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23044975500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12992134000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12992134000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10577318000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10577318000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1572635000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1572635000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4587759000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4587759000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2934500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2934500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70534691000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 70534691000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83526825000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 83526825000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1888408000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1888408000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1888408000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1888408000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036584 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036584 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018463 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018463 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775198 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775198 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.737952 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.737952 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064748 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064748 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105055 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105055 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030937 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030937 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034847 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034847 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4797887 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5018955 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.221127 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 416962969 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5019467 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.069172 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378705112000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.221127 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969182 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969182 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits -system.cpu1.icache.overall_hits::total 416090013 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4798405 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4798405 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4798405 # number of overall misses -system.cpu1.icache.overall_misses::total 4798405 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50998473000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50998473000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50998473000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50998473000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50998473000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50998473000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 420888418 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 420888418 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 420888418 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 420888418 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 420888418 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 420888418 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011401 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011401 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011401 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011401 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011401 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011401 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10628.213542 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10628.213542 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10628.213542 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10628.213542 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 848984354 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 848984354 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 416962969 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 416962969 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 416962969 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 416962969 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 416962969 # number of overall hits +system.cpu1.icache.overall_hits::total 416962969 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5019472 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5019472 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5019472 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5019472 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5019472 # number of overall misses +system.cpu1.icache.overall_misses::total 5019472 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53186343000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 53186343000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 53186343000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 53186343000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 53186343000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 53186343000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 421982441 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 421982441 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 421982441 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 421982441 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 421982441 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 421982441 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011895 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011895 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011895 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011895 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011895 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011895 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10596.003524 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10596.003524 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10596.003524 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10596.003524 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4797887 # number of writebacks -system.cpu1.icache.writebacks::total 4797887 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4798405 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4798405 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4798405 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4798405 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4798405 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4798405 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5018955 # number of writebacks +system.cpu1.icache.writebacks::total 5018955 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5019472 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5019472 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5019472 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5019472 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5019472 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5019472 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48599271000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 48599271000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48599271000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 48599271000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48599271000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 48599271000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011401 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011401 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011401 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10128.213646 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50676607000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 50676607000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50676607000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 50676607000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50676607000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 50676607000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011895 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011895 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011895 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6881080 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6881096 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1970256 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1985806 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.166669 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10058718427000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.190300 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 64.411311 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 905.409563 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.749966 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002697 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003931 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055262 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.811856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1582 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13889 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 690 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2519 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5802 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5375 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.096558 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 333785497 # 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number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 241732 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150683 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4339488 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3517269 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8249172 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10752 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9335 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20087 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 209731 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 209731 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 204666 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 204666 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 10 # 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number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4798405 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4668904 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 9879811 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.048696 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997389 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997389 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 855832 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1952199 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13310.052713 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 14647404 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1968271 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.441762 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9691338413500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12374.908537 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.710351 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 42.105943 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 846.327882 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.755304 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002851 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 976 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4506 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5198 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3947 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080261 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897583 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 339868675 # 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mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.559345 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159812 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.234134 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 34156.170658 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40544.234544 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20963.093200 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20963.093200 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16265.559497 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16265.559497 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261449.900000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261449.900000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.607626 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33154.607626 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27413.278436 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26323.631135 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26323.631135 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27139.318892 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27139.318892 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27775.004552 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31570.422456 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163610.104214 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162838.851503 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 390891 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 375101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 483493 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1131381 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1109621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4798405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4426002 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 496716 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 445955 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14394916 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16294669 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 336160 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 556294 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 31582039 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614163064 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 626579614 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1280144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2019872 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1244042694 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5755928 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 16349135 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.122449 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.327837 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226443 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 20762161 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10650842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1727817 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1727605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 482395 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9130479 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4254476 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6851297 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2274133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 818827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 384823 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346834 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 460171 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1120311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1099104 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5019472 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4398430 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 506547 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 458275 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15058119 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16186537 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 334443 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 542756 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32121855 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 642459768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 622853650 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1275376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1972104 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1268560898 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5663025 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75880456 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 16447181 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.119069 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.323910 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14347367 87.76% 87.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2001594 12.24% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 174 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14489040 88.09% 88.09% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1957929 11.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 212 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 16349135 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20146131499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 16447181 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20541870997 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 187574309 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 171936035 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7529318000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7396555908 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 175021499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 296243499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40346 # Transaction distribution system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136634 # Transaction distribution -system.iobus.trans_dist::WriteResp 136634 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 136621 # Transaction distribution +system.iobus.trans_dist::WriteResp 136621 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2420,13 +2425,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122674 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231238 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2439,21 +2444,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338968 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496707 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36949503 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496777 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36887001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2465,77 +2470,77 @@ system.iobus.reqLayer15.occupancy 8500 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26494000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26455501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37417500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569241095 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147934000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115585 # number of replacements -system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115616 # number of replacements +system.iocache.tags.tagsinuse 11.233110 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115632 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9095552544000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412176 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.820935 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463261 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.238808 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.702069 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040784 # Number of tag accesses -system.iocache.tags.data_accesses 1040784 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040928 # Number of tag accesses +system.iocache.tags.data_accesses 1040928 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8891 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8928 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses -system.iocache.demand_misses::total 115643 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115619 # number of demand (read+write) misses +system.iocache.demand_misses::total 115659 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115603 # number of overall misses -system.iocache.overall_misses::total 115643 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1623231612 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1628431112 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115619 # number of overall misses +system.iocache.overall_misses::total 115659 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1628324544 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1633522544 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12905416814 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12905416814 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14528648426 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14534216926 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14528648426 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14534216926 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12891433551 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12891433551 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14519758095 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14525325095 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14519758095 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14525325095 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8891 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8928 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115619 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115659 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115619 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115659 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2549,53 +2554,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182899.336563 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182723.419210 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182966.234767 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120918.754348 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120918.754348 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125681.769982 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125681.769982 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31595 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125587.503739 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125587.503739 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31812 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3498 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.192610 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.094340 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106695 # number of writebacks system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8875 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8891 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8928 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115603 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115643 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115619 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115659 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115603 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115643 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179481612 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1182831112 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115619 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115659 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183774544 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1187122544 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7559977711 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7559977711 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8739459323 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8743027823 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8739459323 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8743027823 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7546042407 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7546042407 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8729816951 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8733383951 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8729816951 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8733383951 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2609,657 +2614,659 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132899.336563 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132723.419210 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1336257 # number of replacements -system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use -system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1394864 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.864457 # Average number of references to valid blocks. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1334376 # number of replacements +system.l2c.tags.tagsinuse 63294.471519 # Cycle average of tags in use +system.l2c.tags.total_refs 5390543 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1393372 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.868703 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 23096.089917 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.068224 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 220.083460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4065.866850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8220.853874 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.282047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.986041 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 269.420690 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2932.882407 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5116.369986 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10693.582513 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.352418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003358 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.125440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002502 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.078070 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.163171 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964958 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10513 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 47867 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 208 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 519 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9786 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1623 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40883 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.160416 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 69855982 # Number of tag accesses -system.l2c.tags.data_accesses 69855982 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 130434 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 288383 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36828 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 37034 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 73862 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 45889 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57251 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103140 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4670 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3337 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 411404 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 536957 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 268808 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6004 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5313 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 419752 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 541221 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283166 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2480632 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 118921 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 122409 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 241330 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 411404 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 582846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 268808 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6004 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5313 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 419752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 598472 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 283166 # number of demand (read+write) hits -system.l2c.demand_hits::total 2583772 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4670 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3337 # number of overall hits -system.l2c.overall_hits::cpu0.inst 411404 # number of overall hits -system.l2c.overall_hits::cpu0.data 582846 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 268808 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6004 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5313 # number of overall hits -system.l2c.overall_hits::cpu1.inst 419752 # number of overall hits -system.l2c.overall_hits::cpu1.data 598472 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 283166 # number of overall hits -system.l2c.overall_hits::total 2583772 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 61222 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 59774 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 120996 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13056 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 12621 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25677 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 80578 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 52729 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133307 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1465 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1507 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 49296 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 137179 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 229932 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2146 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2116 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 39165 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 95585 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 188965 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 747356 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 446352 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 114497 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 560849 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1465 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1507 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 49296 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 217757 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 229932 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2146 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2116 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 148314 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 188965 # number of demand (read+write) misses -system.l2c.demand_misses::total 880663 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1465 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1507 # number of overall misses -system.l2c.overall_misses::cpu0.inst 49296 # number of overall misses -system.l2c.overall_misses::cpu0.data 217757 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 229932 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2146 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2116 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39165 # number of overall misses -system.l2c.overall_misses::cpu1.data 148314 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 188965 # number of overall misses -system.l2c.overall_misses::total 880663 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 367859500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 359764000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 727623500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 70353500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 71619000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 141972500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7055893500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4403905000 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2618.991189 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.339099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003990 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.006964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.053434 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.159135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.255156 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000638 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.048699 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.039963 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.965797 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10362 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 274 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48360 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 240 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 245 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9869 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 274 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1630 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5501 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 41094 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.158112 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004181 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.737915 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 69824789 # Number of tag accesses +system.l2c.tags.data_accesses 69824789 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2605015 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2605015 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 157240 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 131498 # 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number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5997 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5496 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 419901 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 588510 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 275271 # number of demand (read+write) hits +system.l2c.demand_hits::total 2580085 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4832 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3674 # number of overall hits +system.l2c.overall_hits::cpu0.inst 408343 # number of overall hits +system.l2c.overall_hits::cpu0.data 586641 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 281420 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5997 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5496 # 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average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24758.927154 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24820.062840 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24790.027679 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77420.562538 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73582.192289 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75949.234159 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78536.396441 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81766.937359 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96011.218611 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19970.157087 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20362.317730 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20051.936203 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157644.476482 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145634.098069 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106095.762484 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80352.654147 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3668271 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2217535 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81885 # Transaction distribution -system.membus.trans_dist::ReadResp 837971 # Transaction distribution -system.membus.trans_dist::WriteReq 38514 # Transaction distribution -system.membus.trans_dist::WriteResp 38514 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution -system.membus.trans_dist::CleanEvict 216465 # Transaction distribution -system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81829 # Transaction distribution +system.membus.trans_dist::ReadResp 838129 # Transaction distribution +system.membus.trans_dist::WriteReq 38464 # Transaction distribution +system.membus.trans_dist::WriteResp 38464 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1174756 # Transaction distribution +system.membus.trans_dist::CleanEvict 216961 # Transaction distribution +system.membus.trans_dist::UpgradeReq 398327 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 309165 # Transaction distribution system.membus.trans_dist::UpgradeResp 22 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 147056 # Transaction distribution -system.membus.trans_dist::ReadExResp 129063 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 756086 # Transaction distribution -system.membus.trans_dist::InvalidateReq 664574 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122674 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 145872 # Transaction distribution +system.membus.trans_dist::ReadExResp 127949 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 756300 # Transaction distribution +system.membus.trans_dist::InvalidateReq 666856 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26434 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4433526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4582726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237876 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237876 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4820602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155781 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4552154 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4790128 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52868 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124620204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124829057 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 132083009 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 605187 # Total snoops (count) -system.membus.snoop_fanout::samples 2426230 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013777 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.116566 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124524268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124732755 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131989971 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 572885 # Total snoops (count) +system.membus.snoopTraffic 188480 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2396814 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013654 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.116050 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2392803 98.62% 98.62% # Request fanout histogram -system.membus.snoop_fanout::1 33427 1.38% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2364088 98.63% 98.63% # Request fanout histogram +system.membus.snoop_fanout::1 32726 1.37% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2426230 # Request fanout histogram -system.membus.reqLayer0.occupancy 101268497 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2396814 # Request fanout histogram +system.membus.reqLayer0.occupancy 101168498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21745999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8211058586 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4830240380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45484396 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3302,77 +3309,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1093112 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 292338 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 292338 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4001459 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 832376 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 802179 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8623692 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7234411 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15858103 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 210145531 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 178915910 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 389061441 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2781791 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7676067 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.360389 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.483218 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10770571 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5860830 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1720391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 132185 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 120739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11446 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81831 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4048119 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38464 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38464 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3673076 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2310912 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 679438 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 381379 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1060817 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 109 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291982 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291982 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3967045 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 832947 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 803400 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8640930 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144066 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15784996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 212830169 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175839034 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 388669203 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2716758 # Total snoops (count) +system.toL2Bus.snoopTraffic 119453392 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7607581 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.354994 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.481646 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4921172 64.11% 64.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2743418 35.74% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11477 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4918380 64.65% 64.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2677755 35.20% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11446 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7676067 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8520913919 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7607581 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8483488339 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2554437 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2591888 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3920667694 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3918166834 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3580148330 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3514899349 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal index ac6936025..8a6e02412 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000032] Console: colour dummy device 80x25
-[ 0.000036] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000037] pid_max: default: 32768 minimum: 301
-[ 0.000053] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000054] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000245] hw perfevents: no hardware support available
-[ 0.060065] CPU1: Booted secondary processor
-[ 1.080104] CPU2: failed to come online
-[ 2.100199] CPU3: failed to come online
-[ 2.100203] Brought up 2 CPUs
-[ 2.100204] SMP: Total of 2 processors activated.
-[ 2.100286] devtmpfs: initialized
-[ 2.100949] atomic64_test: passed
-[ 2.101011] regulator-dummy: no parameters
-[ 2.101476] NET: Registered protocol family 16
-[ 2.101658] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101666] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.103275] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.103279] Serial: AMBA PL011 UART driver
-[ 2.103525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.103576] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.104152] console [ttyAMA0] enabled
-[ 2.104323] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.104394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.104465] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.104535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.150406] 3V3: 3300 mV
-[ 2.150465] vgaarb: loaded
-[ 2.150535] SCSI subsystem initialized
-[ 2.150576] libata version 3.00 loaded.
-[ 2.150646] usbcore: registered new interface driver usbfs
-[ 2.150667] usbcore: registered new interface driver hub
-[ 2.150693] usbcore: registered new device driver usb
-[ 2.150726] pps_core: LinuxPPS API ver. 1 registered
-[ 2.150736] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.150757] PTP clock support registered
-[ 2.150931] Switched to clocksource arch_sys_counter
-[ 2.152285] NET: Registered protocol family 2
-[ 2.152391] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.152411] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.152431] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.152471] TCP: reno registered
-[ 2.152479] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.152493] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.152538] NET: Registered protocol family 1
-[ 2.152603] RPC: Registered named UNIX socket transport module.
-[ 2.152613] RPC: Registered udp transport module.
-[ 2.152622] RPC: Registered tcp transport module.
-[ 2.152630] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.152643] PCI: CLS 0 bytes, default 64
-[ 2.152855] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.152973] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.155121] fuse init (API version 7.23)
-[ 2.155231] msgmni has been set to 469
-[ 2.157249] io scheduler noop registered
-[ 2.157315] io scheduler cfq registered (default)
-[ 2.158049] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.158063] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.158075] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.158088] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.158099] pci_bus 0000:00: scanning bus
-[ 2.158111] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.158125] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.158141] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.158181] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.158194] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.158205] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.158216] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.158227] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.158239] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.158251] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.158291] pci_bus 0000:00: fixups for bus
-[ 2.158300] pci_bus 0000:00: bus scan returning with max=00
-[ 2.158312] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.158334] pci 0000:00:00.0: fixup irq: got 33
-[ 2.158343] pci 0000:00:00.0: assigning IRQ 33
-[ 2.158355] pci 0000:00:01.0: fixup irq: got 34
-[ 2.158364] pci 0000:00:01.0: assigning IRQ 34
-[ 2.158377] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.158390] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.158404] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.158417] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.158429] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.158441] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.158453] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.158465] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.159060] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.159386] ata_piix 0000:00:01.0: version 2.13
-[ 2.159397] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.159432] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.159775] scsi0 : ata_piix
-[ 2.159868] scsi1 : ata_piix
-[ 2.159904] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.159917] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.160058] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.160070] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.160086] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.160098] e1000 0000:00:00.0: enabling bus mastering
-[ 2.300957] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.300967] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.300998] ata1.00: configured for UDMA/33
-[ 2.301069] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.301206] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.301211] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.301241] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.301251] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.301279] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.301443] sda: sda1
-[ 2.301585] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.421256] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.421269] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.421295] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.421306] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.421330] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.421342] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.421439] usbcore: registered new interface driver usb-storage
-[ 2.421506] mousedev: PS/2 mouse device common for all mice
-[ 2.421699] usbcore: registered new interface driver usbhid
-[ 2.421709] usbhid: USB HID core driver
-[ 2.421746] TCP: cubic registered
-[ 2.421755] NET: Registered protocol family 17
- -[ 2.422264] devtmpfs: mounted
-[ 2.422355] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000027] Console: colour dummy device 80x25
+[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000032] pid_max: default: 32768 minimum: 301
+[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000186] hw perfevents: no hardware support available
+[ 0.060051] CPU1: Booted secondary processor
+[ 1.080095] CPU2: failed to come online
+[ 2.100183] CPU3: failed to come online
+[ 2.100186] Brought up 2 CPUs
+[ 2.100188] SMP: Total of 2 processors activated.
+[ 2.100259] devtmpfs: initialized
+[ 2.100898] atomic64_test: passed
+[ 2.100952] regulator-dummy: no parameters
+[ 2.101389] NET: Registered protocol family 16
+[ 2.101557] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101563] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.102363] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.102366] Serial: AMBA PL011 UART driver
+[ 2.102592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.102637] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.103214] console [ttyAMA0] enabled
+[ 2.103383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.103459] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.103535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.103603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.130362] 3V3: 3300 mV
+[ 2.130420] vgaarb: loaded
+[ 2.130477] SCSI subsystem initialized
+[ 2.130513] libata version 3.00 loaded.
+[ 2.130567] usbcore: registered new interface driver usbfs
+[ 2.130587] usbcore: registered new interface driver hub
+[ 2.130614] usbcore: registered new device driver usb
+[ 2.130645] pps_core: LinuxPPS API ver. 1 registered
+[ 2.130654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.130674] PTP clock support registered
+[ 2.130822] Switched to clocksource arch_sys_counter
+[ 2.132478] NET: Registered protocol family 2
+[ 2.132574] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.132642] TCP: reno registered
+[ 2.132649] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132663] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132704] NET: Registered protocol family 1
+[ 2.132763] RPC: Registered named UNIX socket transport module.
+[ 2.132774] RPC: Registered udp transport module.
+[ 2.132782] RPC: Registered tcp transport module.
+[ 2.132791] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.132804] PCI: CLS 0 bytes, default 64
+[ 2.133012] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.133128] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.135205] fuse init (API version 7.23)
+[ 2.135350] msgmni has been set to 469
+[ 2.135656] io scheduler noop registered
+[ 2.135718] io scheduler cfq registered (default)
+[ 2.136286] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.136300] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.136311] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.136324] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.136335] pci_bus 0000:00: scanning bus
+[ 2.136346] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.136360] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.136375] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136416] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.136429] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.136440] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.136452] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.136463] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.136474] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.136486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136527] pci_bus 0000:00: fixups for bus
+[ 2.136536] pci_bus 0000:00: bus scan returning with max=00
+[ 2.136548] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.136569] pci 0000:00:00.0: fixup irq: got 33
+[ 2.136578] pci 0000:00:00.0: assigning IRQ 33
+[ 2.136589] pci 0000:00:01.0: fixup irq: got 34
+[ 2.136598] pci 0000:00:01.0: assigning IRQ 34
+[ 2.136609] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.136623] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.136636] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.136650] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.136662] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.136674] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.136686] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.136698] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.137491] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.137826] ata_piix 0000:00:01.0: version 2.13
+[ 2.137837] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.137864] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.138204] scsi0 : ata_piix
+[ 2.138329] scsi1 : ata_piix
+[ 2.138380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.138393] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.138543] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.138556] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.138573] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.138585] e1000 0000:00:00.0: enabling bus mastering
+[ 2.280852] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.280862] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.280892] ata1.00: configured for UDMA/33
+[ 2.280951] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.281082] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.281116] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.281160] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.281170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.281192] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.281337] sda: sda1
+[ 2.281470] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.401164] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.401177] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.401211] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.401224] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.401253] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.401268] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.401414] usbcore: registered new interface driver usb-storage
+[ 2.401486] mousedev: PS/2 mouse device common for all mice
+[ 2.401677] usbcore: registered new interface driver usbhid
+[ 2.401687] usbhid: USB HID core driver
+[ 2.401726] TCP: cubic registered
+[ 2.401734] NET: Registered protocol family 17
+ +[ 2.402215] devtmpfs: mounted
+[ 2.402270] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.462786] udevd[609]: starting version 182
+[ 2.442337] udevd[608]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.544201] random: dd urandom read with 18 bits of entropy available
+[ 2.533997] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.681165] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.671053] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index 27116f25e..ebadfb41e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -121,6 +135,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -139,13 +157,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -164,8 +186,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -188,9 +215,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -204,9 +236,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -217,13 +254,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -242,8 +283,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -301,9 +347,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -317,9 +368,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -330,13 +386,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -355,8 +415,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -364,9 +429,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -411,9 +482,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -427,13 +503,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -452,8 +532,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -461,9 +546,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -477,11 +568,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -526,6 +622,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -537,7 +634,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -580,10 +681,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -664,14 +770,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -680,13 +791,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -696,6 +812,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -766,10 +883,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -849,17 +971,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -885,12 +1012,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -898,14 +1031,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -991,14 +1129,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1007,13 +1150,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1022,13 +1170,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1036,11 +1189,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1054,11 +1212,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1072,19 +1235,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1130,14 +1299,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1146,11 +1330,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1160,21 +1349,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1184,12 +1383,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1198,10 +1402,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1211,12 +1420,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1226,26 +1440,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1254,10 +1478,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1265,10 +1494,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1276,21 +1510,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1304,11 +1548,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1319,11 +1568,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1331,10 +1585,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr index 3c2cf37c0..082803b1b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr @@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout index 9326fddff..ad2b5e63e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 14:13:19 -gem5 executing on e104799-lin, pid 14780 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:07:38 +gem5 executing on e108600-lin, pid 24412 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51811415265500 because m5_exit instruction encountered +Exiting @ tick 51759347706500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 04a520211..89d0e34be 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.759374 # Number of seconds simulated -sim_ticks 51759374264500 # Number of ticks simulated -final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.759348 # Number of seconds simulated +sim_ticks 51759347706500 # Number of ticks simulated +final_tick 51759347706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622194 # Simulator instruction rate (inst/s) -host_op_rate 731170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38479042536 # Simulator tick rate (ticks/s) -host_mem_usage 677104 # Number of bytes of host memory used -host_seconds 1345.13 # Real time elapsed on the host -sim_insts 836933434 # Number of instructions simulated -sim_ops 983519389 # Number of ops (including micro ops) simulated +host_inst_rate 706961 # Simulator instruction rate (inst/s) +host_op_rate 830795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43773319280 # Simulator tick rate (ticks/s) +host_mem_usage 670816 # Number of bytes of host memory used +host_seconds 1182.44 # Real time elapsed on the host +sim_insts 835939132 # Number of instructions simulated +sim_ops 982366087 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory -system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 152192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 158144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4715828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 36073224 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 410496 # Number of bytes read from this memory +system.physmem.bytes_read::total 41509884 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4715828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4715828 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 62909632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory -system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 62930212 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 114092 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 563657 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::total 689012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 982963 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 985536 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 91111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 696941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 801978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1215426 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 693427 # Number of read requests accepted -system.physmem.writeReqs 989027 # Number of write requests accepted -system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue -system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1215823 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1215426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 697339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2017802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 689012 # Number of read requests accepted +system.physmem.writeReqs 985536 # Number of write requests accepted +system.physmem.readBursts 689012 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 985536 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 44056384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40384 # Total number of bytes read from write queue +system.physmem.bytesWritten 62928960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41509884 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 62930212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 631 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 40853 # Per bank write bursts -system.physmem.perBankRdBursts::1 42497 # Per bank write bursts -system.physmem.perBankRdBursts::2 39380 # Per bank write bursts -system.physmem.perBankRdBursts::3 40815 # Per bank write bursts -system.physmem.perBankRdBursts::4 36874 # Per bank write bursts -system.physmem.perBankRdBursts::5 45606 # Per bank write bursts -system.physmem.perBankRdBursts::6 38207 # Per bank write bursts -system.physmem.perBankRdBursts::7 36804 # Per bank write bursts -system.physmem.perBankRdBursts::8 38817 # Per bank write bursts -system.physmem.perBankRdBursts::9 83381 # Per bank write bursts -system.physmem.perBankRdBursts::10 47849 # Per bank write bursts -system.physmem.perBankRdBursts::11 45678 # Per bank write bursts -system.physmem.perBankRdBursts::12 39735 # Per bank write bursts -system.physmem.perBankRdBursts::13 40223 # Per bank write bursts -system.physmem.perBankRdBursts::14 37028 # Per bank write bursts -system.physmem.perBankRdBursts::15 38885 # Per bank write bursts -system.physmem.perBankWrBursts::0 61132 # Per bank write bursts -system.physmem.perBankWrBursts::1 62574 # Per bank write bursts -system.physmem.perBankWrBursts::2 60681 # Per bank write bursts -system.physmem.perBankWrBursts::3 62576 # Per bank write bursts -system.physmem.perBankWrBursts::4 57559 # Per bank write bursts -system.physmem.perBankWrBursts::5 64093 # Per bank write bursts -system.physmem.perBankWrBursts::6 59756 # Per bank write bursts -system.physmem.perBankWrBursts::7 59796 # Per bank write bursts -system.physmem.perBankWrBursts::8 61252 # Per bank write bursts -system.physmem.perBankWrBursts::9 63246 # Per bank write bursts -system.physmem.perBankWrBursts::10 66784 # Per bank write bursts -system.physmem.perBankWrBursts::11 64593 # Per bank write bursts -system.physmem.perBankWrBursts::12 60371 # Per bank write bursts -system.physmem.perBankWrBursts::13 61779 # Per bank write bursts -system.physmem.perBankWrBursts::14 59591 # Per bank write bursts -system.physmem.perBankWrBursts::15 60974 # Per bank write bursts +system.physmem.perBankRdBursts::0 41424 # Per bank write bursts +system.physmem.perBankRdBursts::1 42196 # Per bank write bursts +system.physmem.perBankRdBursts::2 39305 # Per bank write bursts +system.physmem.perBankRdBursts::3 41228 # Per bank write bursts +system.physmem.perBankRdBursts::4 37796 # Per bank write bursts +system.physmem.perBankRdBursts::5 46284 # Per bank write bursts +system.physmem.perBankRdBursts::6 37646 # Per bank write bursts +system.physmem.perBankRdBursts::7 36984 # Per bank write bursts +system.physmem.perBankRdBursts::8 37874 # Per bank write bursts +system.physmem.perBankRdBursts::9 85067 # Per bank write bursts +system.physmem.perBankRdBursts::10 43899 # Per bank write bursts +system.physmem.perBankRdBursts::11 46232 # Per bank write bursts +system.physmem.perBankRdBursts::12 39321 # Per bank write bursts +system.physmem.perBankRdBursts::13 40035 # Per bank write bursts +system.physmem.perBankRdBursts::14 35465 # Per bank write bursts +system.physmem.perBankRdBursts::15 37625 # Per bank write bursts +system.physmem.perBankWrBursts::0 61899 # Per bank write bursts +system.physmem.perBankWrBursts::1 62487 # Per bank write bursts +system.physmem.perBankWrBursts::2 61087 # Per bank write bursts +system.physmem.perBankWrBursts::3 63695 # Per bank write bursts +system.physmem.perBankWrBursts::4 58991 # Per bank write bursts +system.physmem.perBankWrBursts::5 64628 # Per bank write bursts +system.physmem.perBankWrBursts::6 58592 # Per bank write bursts +system.physmem.perBankWrBursts::7 59025 # Per bank write bursts +system.physmem.perBankWrBursts::8 60354 # Per bank write bursts +system.physmem.perBankWrBursts::9 64900 # Per bank write bursts +system.physmem.perBankWrBursts::10 63044 # Per bank write bursts +system.physmem.perBankWrBursts::11 64791 # Per bank write bursts +system.physmem.perBankWrBursts::12 60176 # Per bank write bursts +system.physmem.perBankWrBursts::13 61598 # Per bank write bursts +system.physmem.perBankWrBursts::14 57895 # Per bank write bursts +system.physmem.perBankWrBursts::15 60103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 51759371327500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 51759344769500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 650311 # Read request sizes (log2) +system.physmem.readPktSize::6 645896 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 986454 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 982963 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 659454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 23139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,167 +160,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 54935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 55206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 55686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 56443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 55845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 56872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 57169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 58902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 55823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 54603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 54399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 438828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 243.797169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.013209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 285.979705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 194919 44.42% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 116778 26.61% 71.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38832 8.85% 79.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20430 4.66% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13130 2.99% 87.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8793 2.00% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7414 1.69% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5819 1.33% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32713 7.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 438828 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.201312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 141.003763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 52140 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 52143 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.857085 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.140227 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.284435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48446 92.91% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1855 3.56% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 116 0.22% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 101 0.19% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 48 0.09% 96.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 101 0.19% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 252 0.48% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.05% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 307 0.59% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 75 0.14% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.06% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 51 0.10% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 313 0.60% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 41 0.08% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 37 0.07% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 129 0.25% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 166 0.32% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 15 0.03% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads -system.physmem.totQLat 9243736951 # Total ticks spent queuing -system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52143 # Writes before turning the bus around for reads +system.physmem.totQLat 9222624910 # Total ticks spent queuing +system.physmem.totMemAccLat 22129768660 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3441905000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13397.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32147.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing -system.physmem.readRowHits 510166 # Number of row buffer hits during reads -system.physmem.writeRowHits 727396 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes -system.physmem.avgGap 30764211.88 # Average gap between requests -system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.514508 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states -system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 507228 # Number of row buffer hits during reads +system.physmem.writeRowHits 725589 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.79 # Row buffer hit rate for writes +system.physmem.avgGap 30909442.29 # Average gap between requests +system.physmem.pageHitRate 73.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1651557600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 901147500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2518331400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3177817920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1280908967265 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29932003411500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34601830107105 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.513662 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49794254360042 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728358320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states +system.physmem_0.memoryStateTime::ACT 236733614958 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.532817 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states -system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states +system.physmem_1.actEnergy 1665982080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 909018000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2851001400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3193739280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1282600048680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29930520006750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34602408670110 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.524840 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49791748874504 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728358320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states +system.physmem_1.memoryStateTime::ACT 239239854996 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -337,9 +338,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -347,7 +348,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -377,73 +378,72 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 187211 # Table walker walks requested -system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 186389 # Table walker walks requested +system.cpu.dtb.walker.walksLong 186389 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 11673 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 145933 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 186369 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.214628 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.564506 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 186367 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 186369 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 157626 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24833.263548 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20845.971920 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18169.669952 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 156391 99.22% 99.22% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.22% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1058 0.67% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 78 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 18 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 45 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 157626 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -5176298892 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 1.304609 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::0 1576748204 -30.46% -30.46% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -6753047096 130.46% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -5176298892 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 145934 92.59% 92.59% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 11673 7.41% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 157607 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 186389 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 186389 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157607 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 157607 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 343996 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 157500215 # DTB read hits -system.cpu.dtb.read_misses 138721 # DTB read misses -system.cpu.dtb.write_hits 142992331 # DTB write hits -system.cpu.dtb.write_misses 48490 # DTB write misses +system.cpu.dtb.read_hits 157302470 # DTB read hits +system.cpu.dtb.read_misses 138254 # DTB read misses +system.cpu.dtb.write_hits 142797891 # DTB write hits +system.cpu.dtb.write_misses 48135 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70937 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 71109 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6989 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 157638936 # DTB read accesses -system.cpu.dtb.write_accesses 143040821 # DTB write accesses +system.cpu.dtb.read_accesses 157440724 # DTB read accesses +system.cpu.dtb.write_accesses 142846026 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 300492546 # DTB hits -system.cpu.dtb.misses 187211 # DTB misses -system.cpu.dtb.accesses 300679757 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 300100361 # DTB hits +system.cpu.dtb.misses 186389 # DTB misses +system.cpu.dtb.accesses 300286750 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -473,68 +473,67 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 119486 # Table walker walks requested -system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 119383 # Table walker walks requested +system.cpu.itb.walker.walksLong 119383 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107813 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 119383 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 119383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 119383 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 108935 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28686.574563 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24766.127594 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21816.949759 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107446 98.63% 98.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1285 1.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 37 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 72 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 42 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 108935 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 107813 98.97% 98.97% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 108935 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119383 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 119383 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 837449249 # ITB inst hits -system.cpu.itb.inst_misses 119486 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108935 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 108935 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 228318 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 836454912 # ITB inst hits +system.cpu.itb.inst_misses 119383 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50613 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 50925 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 837568735 # ITB inst accesses -system.cpu.itb.hits 837449249 # DTB hits -system.cpu.itb.misses 119486 # DTB misses -system.cpu.itb.accesses 837568735 # DTB accesses +system.cpu.itb.inst_accesses 836574295 # ITB inst accesses +system.cpu.itb.hits 836454912 # DTB hits +system.cpu.itb.misses 119383 # DTB misses +system.cpu.itb.accesses 836574295 # DTB accesses system.cpu.numPwrStateTransitions 32056 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3133737148.696906 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60742072610.602715 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3133878336.314075 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60741761061.559830 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state @@ -547,42 +546,42 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1531835245186 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50227539019314 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103518748529 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1529545732058 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50229801974442 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103518695413 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed -system.cpu.committedInsts 836933434 # Number of instructions committed -system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses -system.cpu.num_func_calls 50188688 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls -system.cpu.num_int_insts 904020212 # number of integer instructions -system.cpu.num_fp_insts 901230 # number of float instructions -system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read -system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read -system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written -system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read -system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written -system.cpu.num_mem_refs 300471292 # number of memory refs -system.cpu.num_load_insts 157490392 # Number of load instructions -system.cpu.num_store_insts 142980900 # Number of store instructions -system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles -system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970405 # Percentage of idle cycles -system.cpu.Branches 186768786 # Number of branches fetched +system.cpu.committedInsts 835939132 # Number of instructions committed +system.cpu.committedOps 982366087 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 902933087 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900158 # Number of float alu accesses +system.cpu.num_func_calls 50090187 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 126876498 # number of instructions that are conditional controls +system.cpu.num_int_insts 902933087 # number of integer instructions +system.cpu.num_fp_insts 900158 # number of float instructions +system.cpu.num_int_register_reads 1308206945 # number of times the integer registers were read +system.cpu.num_int_register_writes 715740470 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1453094 # number of times the floating registers were read +system.cpu.num_fp_register_writes 759824 # number of times the floating registers were written +system.cpu.num_cc_register_reads 216985275 # number of times the CC registers were read +system.cpu.num_cc_register_writes 216380044 # number of times the CC registers were written +system.cpu.num_mem_refs 300079118 # number of memory refs +system.cpu.num_load_insts 157292666 # Number of load instructions +system.cpu.num_store_insts 142786452 # Number of store instructions +system.cpu.num_idle_cycles 100459603948.882050 # Number of idle cycles +system.cpu.num_busy_cycles 3059091464.117941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029551 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970449 # Percentage of idle cycles +system.cpu.Branches 186526742 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction -system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction -system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction +system.cpu.op_class::IntAlu 680504734 69.23% 69.23% # Class of executed instruction +system.cpu.op_class::IntMult 2132093 0.22% 69.45% # Class of executed instruction +system.cpu.op_class::IntDiv 96706 0.01% 69.46% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction @@ -609,537 +608,538 @@ system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 157292666 16.00% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 142786452 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 984078328 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9381962 # number of replacements +system.cpu.op_class::total 982924991 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9370067 # number of replacements system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 290532688 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9370579 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.004774 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits -system.cpu.dcache.overall_hits::total 283908330 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses -system.cpu.dcache.overall_misses::total 9251082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3623892 # 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miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # 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number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1137538 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1137538 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1221988 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1221988 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 286320 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 286320 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 8102364 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8102364 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9239902 # number of overall misses +system.cpu.dcache.overall_misses::total 9239902 # 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number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3622649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3622649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3621013 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3621013 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 291261899 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 291261899 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292772985 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292772985 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032121 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032121 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014492 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014492 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752795 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.752795 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786421 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786421 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.027818 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027818 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031560 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031560 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17222.587196 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17222.587196 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35101.289149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35101.289149 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39378.370328 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39378.370328 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15398.866653 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15398.866653 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24963.438016 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24963.438016 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21890.152244 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21890.152244 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks -system.cpu.dcache.writebacks::total 7313678 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 43235 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 43235 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 43235 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 43235 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4873010 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 4873010 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1976876 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1976876 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # 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number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13331164 # number of replacements -system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78024875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 78024875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67036106500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67036106500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21307541000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21307541000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 46897908000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 46897908000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989370500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989370500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 160000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191958889500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191958889500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213266430500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 213266430500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199627500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199627500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199627500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199627500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014338 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014338 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751627 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751627 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786421 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786421 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059931 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059931 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031409 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031409 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16036.323229 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16036.323229 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33985.248461 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33985.248461 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18760.386979 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18760.386979 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38378.370328 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38378.370328 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13768.921284 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13768.921284 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23816.230527 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23816.230527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23191.781803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23191.781803 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183954.290547 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183954.290547 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91968.958611 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91968.958611 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13316326 # number of replacements +system.cpu.icache.tags.tagsinuse 511.820794 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 823138069 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13316838 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 61.811826 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.820794 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses -system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits -system.cpu.icache.overall_hits::total 824117568 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13331681 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13331681 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13331681 # number of overall misses -system.cpu.icache.overall_misses::total 13331681 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182292722500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182292722500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182292722500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182292722500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182292722500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182292722500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 837449249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 837449249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 837449249 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency +system.cpu.icache.tags.tag_accesses 849771755 # Number of tag accesses +system.cpu.icache.tags.data_accesses 849771755 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 823138069 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 823138069 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 823138069 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 823138069 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 823138069 # number of overall hits +system.cpu.icache.overall_hits::total 823138069 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13316843 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13316843 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13316843 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13316843 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13316843 # number of overall misses +system.cpu.icache.overall_misses::total 13316843 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182043679500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182043679500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182043679500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182043679500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182043679500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182043679500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 836454912 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 836454912 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 836454912 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 836454912 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 836454912 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 836454912 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015921 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015921 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015921 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13670.182903 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13670.182903 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13670.182903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13670.182903 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777547500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675272000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787095 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787095 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005332 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036150 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036150 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.392764 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.392764 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029090 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029090 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127766.962260 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67939.425823 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67939.425823 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121287.465079 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121287.465079 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122456.389781 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122456.389781 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123386.224335 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123386.224335 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67660.836582 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67660.836582 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.404724 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.087157 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85707.573060 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.205998 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 45899412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23211953 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2701 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2701 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 979874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20515947 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1612380 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8293329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13316326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2221598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 42266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 42268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1930243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1930243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13316843 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6227282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1328652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1221988 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40036262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28331504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 860807 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69830315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1704695316 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 989618926 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2516088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2698790258 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1604803 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 65712840 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 25003730 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.138299 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24515981 98.05% 98.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 487749 1.95% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25003730 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43858380000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1560894 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20018389500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12905646976 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 356751000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 546296000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40345 # Transaction distribution -system.iobus.trans_dist::ReadResp 40345 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40338 # Transaction distribution +system.iobus.trans_dist::ReadResp 40338 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1311,11 +1312,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1330,16 +1331,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1357,75 +1358,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38601000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566926866 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115506 # number of replacements -system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115499 # number of replacements +system.iocache.tags.tagsinuse 10.446740 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 5.847996 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.598744 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.365500 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.287422 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652921 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040073 # Number of tag accesses -system.iocache.tags.data_accesses 1040073 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040010 # Number of tag accesses +system.iocache.tags.data_accesses 1040010 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses -system.iocache.demand_misses::total 115564 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses +system.iocache.demand_misses::total 115557 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115524 # number of overall misses -system.iocache.overall_misses::total 115564 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115517 # number of overall misses +system.iocache.overall_misses::total 115557 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1655174117 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1660244617 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13409764249 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13409764249 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15064938366 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15070359866 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15064938366 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15070359866 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1439,53 +1440,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186961.947024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186754.175141 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125719.682826 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125719.682826 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130414.945577 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130414.945577 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33045 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.788211 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1212524117 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1215744617 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071395398 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8071395398 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9283919515 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9287341015 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9283919515 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9287341015 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1499,88 +1500,89 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136961.947024 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136754.175141 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75671.223637 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75671.223637 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 389416 # Transaction distribution +system.membus.trans_dist::ReadResp 386363 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution -system.membus.trans_dist::CleanEvict 164302 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::WritebackDirty 982963 # Transaction distribution +system.membus.trans_dist::CleanEvict 160860 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33836 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 341030 # Transaction distribution -system.membus.trans_dist::ReadExResp 341030 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution -system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution +system.membus.trans_dist::ReadExReq 339489 # Transaction distribution +system.membus.trans_dist::ReadExResp 339489 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 309536 # Transaction distribution +system.membus.trans_dist::InvalidateReq 586610 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2913100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3042792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3280262 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3315 # Total snoops (count) -system.membus.snoop_fanout::samples 2537144 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97205216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97375042 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7234880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7234880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 104609922 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3136 # Total snoops (count) +system.membus.snoopTraffic 200256 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2523850 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2523850 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2537144 # Request fanout histogram -system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2523850 # Request fanout histogram +system.membus.reqLayer0.occupancy 106906000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5727500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6514212892 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3604018785 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44774812 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1623,28 +1625,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal index dd5c13da3..0cb0b7645 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000045] Console: colour dummy device 80x25
-[ 0.000049] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000051] pid_max: default: 32768 minimum: 301
-[ 0.000075] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000077] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000352] hw perfevents: no hardware support available
+[ 0.000044] Console: colour dummy device 80x25
+[ 0.000048] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000050] pid_max: default: 32768 minimum: 301
+[ 0.000073] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000075] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000316] hw perfevents: no hardware support available
[ 1.060136] CPU1: failed to come online
-[ 2.080266] CPU2: failed to come online
+[ 2.080267] CPU2: failed to come online
[ 3.100398] CPU3: failed to come online
[ 3.100403] Brought up 1 CPUs
[ 3.100405] SMP: Total of 1 processors activated.
-[ 3.100521] devtmpfs: initialized
-[ 3.101636] atomic64_test: passed
-[ 3.101724] regulator-dummy: no parameters
-[ 3.102567] NET: Registered protocol family 16
-[ 3.102857] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.102869] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.105189] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.105197] Serial: AMBA PL011 UART driver
-[ 3.105593] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.105667] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.106251] console [ttyAMA0] enabled
-[ 3.106398] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.106448] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.106498] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.106544] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130846] 3V3: 3300 mV
-[ 3.130933] vgaarb: loaded
-[ 3.131030] SCSI subsystem initialized
-[ 3.131104] libata version 3.00 loaded.
-[ 3.131195] usbcore: registered new interface driver usbfs
-[ 3.131222] usbcore: registered new interface driver hub
-[ 3.131280] usbcore: registered new device driver usb
-[ 3.131327] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131337] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131361] PTP clock support registered
-[ 3.131603] Switched to clocksource arch_sys_counter
-[ 3.133813] NET: Registered protocol family 2
-[ 3.133980] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.134012] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.134052] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.134106] TCP: reno registered
-[ 3.134114] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134134] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134210] NET: Registered protocol family 1
-[ 3.134289] RPC: Registered named UNIX socket transport module.
-[ 3.134300] RPC: Registered udp transport module.
-[ 3.134309] RPC: Registered tcp transport module.
-[ 3.134318] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.134332] PCI: CLS 0 bytes, default 64
-[ 3.134677] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.134913] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.138682] fuse init (API version 7.23)
-[ 3.138854] msgmni has been set to 469
-[ 3.143616] io scheduler noop registered
-[ 3.143713] io scheduler cfq registered (default)
-[ 3.144776] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.144790] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.144803] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.144817] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.144829] pci_bus 0000:00: scanning bus
-[ 3.144843] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.144859] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.144876] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144939] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.144953] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.144966] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.144978] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.144991] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.145004] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.145017] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.145077] pci_bus 0000:00: fixups for bus
-[ 3.145087] pci_bus 0000:00: bus scan returning with max=00
-[ 3.145101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.145130] pci 0000:00:00.0: fixup irq: got 33
-[ 3.145140] pci 0000:00:00.0: assigning IRQ 33
-[ 3.145154] pci 0000:00:01.0: fixup irq: got 34
-[ 3.145164] pci 0000:00:01.0: assigning IRQ 34
-[ 3.145178] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.145193] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.145208] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.145222] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.145236] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.145249] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.145262] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.145276] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.146194] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.146724] ata_piix 0000:00:01.0: version 2.13
-[ 3.146736] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.146781] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.147384] scsi0 : ata_piix
-[ 3.147568] scsi1 : ata_piix
-[ 3.147622] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.147635] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.147840] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.147853] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.147876] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.147889] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301640] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301651] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301686] ata1.00: configured for UDMA/33
-[ 3.301774] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301972] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.302008] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.302066] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.302077] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.302106] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.302309] sda: sda1
-[ 3.302514] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421965] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.421980] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.422010] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.422021] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.422052] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.422065] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.422197] usbcore: registered new interface driver usb-storage
-[ 3.422291] mousedev: PS/2 mouse device common for all mice
-[ 3.422584] usbcore: registered new interface driver usbhid
-[ 3.422595] usbhid: USB HID core driver
-[ 3.422651] TCP: cubic registered
-[ 3.422660] NET: Registered protocol family 17
- -[ 3.423338] devtmpfs: mounted
-[ 3.423462] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 3.100517] devtmpfs: initialized
+[ 3.101614] atomic64_test: passed
+[ 3.101697] regulator-dummy: no parameters
+[ 3.102519] NET: Registered protocol family 16
+[ 3.102798] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102809] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.104232] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.104240] Serial: AMBA PL011 UART driver
+[ 3.104622] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.104693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.105277] console [ttyAMA0] enabled
+[ 3.105422] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.105471] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.105522] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.105568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130937] 3V3: 3300 mV
+[ 3.131019] vgaarb: loaded
+[ 3.131116] SCSI subsystem initialized
+[ 3.131186] libata version 3.00 loaded.
+[ 3.131272] usbcore: registered new interface driver usbfs
+[ 3.131299] usbcore: registered new interface driver hub
+[ 3.131354] usbcore: registered new device driver usb
+[ 3.131399] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131409] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131433] PTP clock support registered
+[ 3.131670] Switched to clocksource arch_sys_counter
+[ 3.133769] NET: Registered protocol family 2
+[ 3.133932] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.133964] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.134004] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.134042] TCP: reno registered
+[ 3.134050] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134070] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134144] NET: Registered protocol family 1
+[ 3.134216] RPC: Registered named UNIX socket transport module.
+[ 3.134227] RPC: Registered udp transport module.
+[ 3.134236] RPC: Registered tcp transport module.
+[ 3.134245] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134259] PCI: CLS 0 bytes, default 64
+[ 3.134575] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134796] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138336] fuse init (API version 7.23)
+[ 3.138502] msgmni has been set to 469
+[ 3.143073] io scheduler noop registered
+[ 3.143173] io scheduler cfq registered (default)
+[ 3.144095] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.144109] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.144122] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.144136] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.144147] pci_bus 0000:00: scanning bus
+[ 3.144161] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.144177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.144195] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.144272] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.144285] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.144297] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.144310] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.144322] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.144336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144395] pci_bus 0000:00: fixups for bus
+[ 3.144405] pci_bus 0000:00: bus scan returning with max=00
+[ 3.144419] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.144446] pci 0000:00:00.0: fixup irq: got 33
+[ 3.144456] pci 0000:00:00.0: assigning IRQ 33
+[ 3.144470] pci 0000:00:01.0: fixup irq: got 34
+[ 3.144480] pci 0000:00:01.0: assigning IRQ 34
+[ 3.144494] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.144509] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.144524] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.144538] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.144552] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.144565] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.144578] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.144591] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.145478] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.146000] ata_piix 0000:00:01.0: version 2.13
+[ 3.146012] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.146049] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.146644] scsi0 : ata_piix
+[ 3.146827] scsi1 : ata_piix
+[ 3.146881] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.146894] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.147093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.147106] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.147129] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.147142] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301707] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301718] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301753] ata1.00: configured for UDMA/33
+[ 3.301838] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302037] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302073] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302130] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302141] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302170] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302373] sda: sda1
+[ 3.302577] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422032] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422047] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422076] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422087] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422118] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422131] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422262] usbcore: registered new interface driver usb-storage
+[ 3.422357] mousedev: PS/2 mouse device common for all mice
+[ 3.422646] usbcore: registered new interface driver usbhid
+[ 3.422657] usbhid: USB HID core driver
+[ 3.422710] TCP: cubic registered
+[ 3.422720] NET: Registered protocol family 17
+ +[ 3.423384] devtmpfs: mounted
+[ 3.423472] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.470418] udevd[607]: starting version 182
+[ 3.470435] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.586551] random: dd urandom read with 21 bits of entropy available
+[ 3.596617] random: dd urandom read with 22 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.791840] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.791906] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini index 43d12537e..80aff2637 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -168,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -192,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -208,9 +240,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -246,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -305,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -321,9 +372,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -338,6 +394,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -356,6 +413,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -387,9 +448,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -403,9 +469,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.isa] @@ -458,9 +529,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -474,9 +550,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -507,9 +588,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -523,13 +609,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -548,8 +638,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -560,13 +655,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -585,20 +684,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -610,11 +720,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -625,16 +740,28 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -649,10 +776,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -733,14 +865,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -749,13 +886,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -765,6 +907,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -835,10 +978,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -918,17 +1066,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -954,12 +1107,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -967,14 +1126,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1060,14 +1224,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1076,13 +1245,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1091,13 +1265,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1105,11 +1284,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1123,11 +1307,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1141,19 +1330,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1199,14 +1394,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1215,11 +1425,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1229,21 +1444,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1253,12 +1478,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1267,10 +1497,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1280,12 +1515,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1295,26 +1535,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1323,10 +1573,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1334,10 +1589,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1345,21 +1605,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1373,11 +1643,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1388,11 +1663,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1400,10 +1680,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1419,9 +1704,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr index 4c76ae25b..273d7bcba 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr @@ -2,8 +2,11 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 +warn: ClockedObject: Already in the requested power state, request ignored warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to read RealView I/O at offset 0x8 that doesn't exist @@ -592,15 +595,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout index 9f2f9de0b..65569f1e5 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 12:10:26 -gem5 executing on e104799-lin, pid 2423 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:22 +gem5 executing on e108600-lin, pid 23081 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 505f419d1..233e6de0a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111166 # Number of seconds simulated -sim_ticks 51111166190000 # Number of ticks simulated -final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111167 # Number of seconds simulated +sim_ticks 51111167268500 # Number of ticks simulated +final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 942692 # Simulator instruction rate (inst/s) -host_op_rate 1107850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49008962729 # Simulator tick rate (ticks/s) -host_mem_usage 679656 # Number of bytes of host memory used -host_seconds 1042.89 # Real time elapsed on the host -sim_insts 983128290 # Number of instructions simulated -sim_ops 1155370468 # Number of ops (including micro ops) simulated +host_inst_rate 810187 # Simulator instruction rate (inst/s) +host_op_rate 952145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42160127212 # Simulator tick rate (ticks/s) +host_mem_usage 675168 # Number of bytes of host memory used +host_seconds 1212.31 # Real time elapsed on the host +sim_insts 982198023 # Number of instructions simulated +sim_ops 1154295627 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 206080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 186880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3298228 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38035976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 206656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 186304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2187520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 36841280 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 435200 # Number of bytes read from this memory -system.physmem.bytes_read::total 81584124 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3298228 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2187520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5485748 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103274624 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 206336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 188224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3277940 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38030472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 207616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 185152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2205440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36882176 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory +system.physmem.bytes_read::total 81620156 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3277940 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2205440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5483380 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103277952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103295204 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2920 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91942 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 594325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 34180 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 575645 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6800 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315172 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613666 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103298532 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 594239 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2893 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 576284 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315735 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613718 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616239 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 64530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 744181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 720807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 64530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020588 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1616291 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 744074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 721607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020653 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2020991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 64530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 744584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 720807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3617200 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.physmem.bw_write::total 2021056 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 744476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 721607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3617970 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -87,9 +87,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -97,7 +97,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -127,47 +127,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 145178 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 145178 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 145178 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 145178 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 145178 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 145515 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 145515 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 145515 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 145515 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 145515 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 108127 85.58% 85.58% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 18215 14.42% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 126342 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 145178 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 108307 85.67% 85.67% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18122 14.33% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126429 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 145515 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 145178 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126342 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 145515 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126429 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126342 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 271520 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126429 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271944 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91916513 # DTB read hits -system.cpu0.dtb.read_misses 107962 # DTB read misses -system.cpu0.dtb.write_hits 84123596 # DTB write hits -system.cpu0.dtb.write_misses 37216 # DTB write misses +system.cpu0.dtb.read_hits 91812952 # DTB read hits +system.cpu0.dtb.read_misses 108269 # DTB read misses +system.cpu0.dtb.write_hits 84016904 # DTB write hits +system.cpu0.dtb.write_misses 37246 # DTB write misses system.cpu0.dtb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56742 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25430 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56668 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4782 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10952 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92024475 # DTB read accesses -system.cpu0.dtb.write_accesses 84160812 # DTB write accesses +system.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91921221 # DTB read accesses +system.cpu0.dtb.write_accesses 84054150 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176040109 # DTB hits -system.cpu0.dtb.misses 145178 # DTB misses -system.cpu0.dtb.accesses 176185287 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 175829856 # DTB hits +system.cpu0.dtb.misses 145515 # DTB misses +system.cpu0.dtb.accesses 175975371 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -197,311 +197,311 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 70488 # Table walker walks requested -system.cpu0.itb.walker.walksLong 70488 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 70488 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 70488 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70488 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 70816 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70816 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70816 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70816 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70816 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61740 96.00% 96.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2570 4.00% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64310 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 62041 96.03% 96.03% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2564 3.97% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64605 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70488 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70488 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70816 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70816 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64310 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64310 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 134798 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493160707 # ITB inst hits -system.cpu0.itb.inst_misses 70488 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64605 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64605 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135421 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 492374883 # ITB inst hits +system.cpu0.itb.inst_misses 70816 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40436 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25430 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40442 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493231195 # ITB inst accesses -system.cpu0.itb.hits 493160707 # DTB hits -system.cpu0.itb.misses 70488 # DTB misses -system.cpu0.itb.accesses 493231195 # DTB accesses -system.cpu0.numPwrStateTransitions 16910 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 8455 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 5871638061.761680 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 113702139546.283386 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3675 43.47% 43.47% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4716 55.78% 99.24% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.25% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 492445699 # ITB inst accesses +system.cpu0.itb.hits 492374883 # DTB hits +system.cpu0.itb.misses 70816 # DTB misses +system.cpu0.itb.accesses 492445699 # DTB accesses +system.cpu0.numPwrStateTransitions 16972 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8486 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 5850237301.708461 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 113494821184.972778 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3706 43.67% 43.67% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4716 55.57% 99.25% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.26% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.53% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 5 0.06% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 12 0.14% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 3977575082060 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 8455 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1466466377805 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 49644699812195 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 98036837820 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 3977575161560 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8486 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1466053526202 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 49645113742298 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 98039867564 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.committedInsts 492942676 # Number of instructions committed -system.cpu0.committedOps 578945163 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 530362809 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 453024 # Number of float alu accesses -system.cpu0.num_func_calls 28530371 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76157318 # number of instructions that are conditional controls -system.cpu0.num_int_insts 530362809 # number of integer instructions -system.cpu0.num_fp_insts 453024 # number of float instructions -system.cpu0.num_int_register_reads 784322084 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421327896 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 740492 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 361708 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 133053105 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132724899 # number of times the CC registers were written -system.cpu0.num_mem_refs 176163553 # number of memory refs -system.cpu0.num_load_insts 92011132 # Number of load instructions -system.cpu0.num_store_insts 84152421 # Number of store instructions -system.cpu0.num_idle_cycles 96928545322.027405 # Number of idle cycles -system.cpu0.num_busy_cycles 1108292497.972592 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011305 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988695 # Percentage of idle cycles -system.cpu0.Branches 110262676 # Number of branches fetched +system.cpu0.committedInsts 492156218 # Number of instructions committed +system.cpu0.committedOps 578106768 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 529626923 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 450865 # Number of float alu accesses +system.cpu0.num_func_calls 28493046 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76041586 # number of instructions that are conditional controls +system.cpu0.num_int_insts 529626923 # number of integer instructions +system.cpu0.num_fp_insts 450865 # number of float instructions +system.cpu0.num_int_register_reads 782885196 # number of times the integer registers were read +system.cpu0.num_int_register_writes 420741799 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 732662 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 369512 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 132705210 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132383544 # number of times the CC registers were written +system.cpu0.num_mem_refs 175953589 # number of memory refs +system.cpu0.num_load_insts 91907608 # Number of load instructions +system.cpu0.num_store_insts 84045981 # Number of store instructions +system.cpu0.num_idle_cycles 96932341935.251450 # Number of idle cycles +system.cpu0.num_busy_cycles 1107525628.748547 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011297 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988703 # Percentage of idle cycles +system.cpu0.Branches 110098917 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 401826971 69.37% 69.37% # Class of executed instruction -system.cpu0.op_class::IntMult 1176436 0.20% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 51169 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 52500 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 92011132 15.88% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 84152421 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 401201785 69.36% 69.36% # Class of executed instruction +system.cpu0.op_class::IntMult 1174308 0.20% 69.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 49945 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 53536 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::MemRead 91907608 15.89% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 84045981 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 579270629 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 11609443 # number of replacements +system.cpu0.op_class::total 578433163 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 11606055 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 340216355 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11609955 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.303848 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 339854312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11606567 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.281209 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 262.381327 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 249.618393 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.512464 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.487536 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 263.642169 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 248.357550 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.514926 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.485073 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1418915240 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1418915240 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 85703422 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 85585649 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171289071 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79649076 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79602210 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159251286 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209671 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214329 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 424000 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 145368 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 191474 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 336842 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2140895 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2164816 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4305711 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2265304 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2292996 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4558300 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165497866 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165379333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 330877199 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165707537 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165593662 # number of overall hits -system.cpu0.dcache.overall_hits::total 331301199 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3022640 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2983261 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6005901 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1299985 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1269181 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2569166 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 790936 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 794497 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1585433 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 765655 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 480562 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1246217 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 125328 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129063 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 254391 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1417450148 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1417450148 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 85600060 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 85509890 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 171109950 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79543301 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 79530135 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 159073436 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209327 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214988 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 424315 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 144230 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 192053 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2149020 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2154529 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 4303549 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2274909 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280735 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165287591 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 165232078 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 330519669 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165496918 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 165447066 # number of overall hits +system.cpu0.dcache.overall_hits::total 330943984 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3016323 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2986728 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6003051 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1295379 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1272732 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2568111 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 788168 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 797714 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1585882 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 761557 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 485215 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 126793 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127105 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 253898 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5088280 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 4733004 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 9821284 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5879216 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 5527501 # number of overall misses -system.cpu0.dcache.overall_misses::total 11406717 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88726062 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88568910 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 177294972 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 80949061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 80871391 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 161820452 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1000607 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1008826 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 2009433 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 911023 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 672036 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1583059 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2266223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2293879 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4560102 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2265304 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2292997 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4558301 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 170586146 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 170112337 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 340698483 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 171586753 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 171121163 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 342707916 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034067 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033683 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033875 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016059 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015694 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015877 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790456 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787546 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788995 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.840434 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.715084 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787221 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055303 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056264 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055786 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 5073259 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 4744675 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 9817934 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5861427 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 5542389 # number of overall misses +system.cpu0.dcache.overall_misses::total 11403816 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88616383 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 88496618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 80838680 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 80802867 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2274909 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2280736 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 170360850 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 169976753 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 171358345 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 170989455 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 342347800 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034038 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033750 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033894 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016024 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015751 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790147 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787709 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788919 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.840768 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.716430 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055713 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055708 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055711 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029828 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027823 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028827 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034264 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032302 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.033284 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029779 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027914 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028848 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034206 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032414 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 8920157 # number of writebacks -system.cpu0.dcache.writebacks::total 8920157 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 14275419 # number of replacements +system.cpu0.dcache.writebacks::writebacks 8916863 # number of writebacks +system.cpu0.dcache.writebacks::total 8916863 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 14265255 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 969443892 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14275931 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.907578 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.598488 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.386111 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524606 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475363 # Average percentage of cache occupancy +system.cpu0.icache.tags.total_refs 968523793 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.597080 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.387519 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524604 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475366 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 997995764 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 997995764 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 486058611 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 483385281 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 969443892 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 486058611 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 483385281 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 969443892 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 486058611 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 483385281 # number of overall hits -system.cpu0.icache.overall_hits::total 969443892 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7166406 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 7109530 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14275936 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7166406 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 7109530 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14275936 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7166406 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 7109530 # number of overall misses -system.cpu0.icache.overall_misses::total 14275936 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 493225017 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 490494811 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 983719828 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 493225017 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 490494811 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 983719828 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 493225017 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 490494811 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 983719828 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014530 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014495 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014512 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014530 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014495 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014512 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014530 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014495 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014512 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 997055337 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 997055337 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 485300804 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 483222989 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 968523793 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 485300804 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 483222989 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 968523793 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 485300804 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 483222989 # number of overall hits +system.cpu0.icache.overall_hits::total 968523793 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7138684 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7127088 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14265772 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7138684 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7127088 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14265772 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7138684 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7127088 # number of overall misses +system.cpu0.icache.overall_misses::total 14265772 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 492439488 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 490350077 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 492439488 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 490350077 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 492439488 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 490350077 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014535 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014535 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014535 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 14275419 # number of writebacks -system.cpu0.icache.writebacks::total 14275419 # number of writebacks -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 14265255 # number of writebacks +system.cpu0.icache.writebacks::total 14265255 # number of writebacks +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -531,47 +531,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 143940 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 143940 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 143940 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 143940 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 143940 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 143141 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143141 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143141 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143141 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143141 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 107031 85.37% 85.37% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 18349 14.63% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 125380 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143940 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 106696 85.47% 85.47% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18135 14.53% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124831 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143141 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143940 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125380 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143141 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124831 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125380 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 269320 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124831 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 267972 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91791346 # DTB read hits -system.cpu1.dtb.read_misses 106897 # DTB read misses -system.cpu1.dtb.write_hits 83829592 # DTB write hits -system.cpu1.dtb.write_misses 37043 # DTB write misses +system.cpu1.dtb.read_hits 91711544 # DTB read hits +system.cpu1.dtb.read_misses 106091 # DTB read misses +system.cpu1.dtb.write_hits 83754683 # DTB write hits +system.cpu1.dtb.write_misses 37050 # DTB write misses system.cpu1.dtb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56630 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24341 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56242 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4731 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4763 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10699 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91898243 # DTB read accesses -system.cpu1.dtb.write_accesses 83866635 # DTB write accesses +system.cpu1.dtb.perms_faults 10698 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91817635 # DTB read accesses +system.cpu1.dtb.write_accesses 83791733 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175620938 # DTB hits -system.cpu1.dtb.misses 143940 # DTB misses -system.cpu1.dtb.accesses 175764878 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 175466227 # DTB hits +system.cpu1.dtb.misses 143141 # DTB misses +system.cpu1.dtb.accesses 175609368 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -601,128 +601,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 69853 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69853 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 69853 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69853 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69853 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 69344 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69344 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69344 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69344 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69344 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61351 96.02% 96.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2542 3.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63893 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 60893 96.02% 96.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2524 3.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63417 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69853 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69853 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69344 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69344 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63893 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63893 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 133746 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 490430918 # ITB inst hits -system.cpu1.itb.inst_misses 69853 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63417 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63417 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 132761 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 490286660 # ITB inst hits +system.cpu1.itb.inst_misses 69344 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41017 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24341 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40468 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 490500771 # ITB inst accesses -system.cpu1.itb.hits 490430918 # DTB hits -system.cpu1.itb.misses 69853 # DTB misses -system.cpu1.itb.accesses 490500771 # DTB accesses -system.cpu1.numPwrStateTransitions 16606 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8303 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 6010299946.497049 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 129216116342.205185 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3765 45.35% 45.35% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4474 53.88% 99.23% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 490356004 # ITB inst accesses +system.cpu1.itb.hits 490286660 # DTB hits +system.cpu1.itb.misses 69344 # DTB misses +system.cpu1.itb.accesses 490356004 # DTB accesses +system.cpu1.numPwrStateTransitions 16542 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8271 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 6033690194.397533 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 129465330065.337860 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3733 45.13% 45.13% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4474 54.09% 99.23% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.02% 99.25% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 4 0.05% 99.30% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 44 0.53% 99.83% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 3 0.04% 99.88% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 5966367262704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8303 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 1207645734235 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 49903520455765 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 97462088232 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 5966367222968 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8271 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 1206515670638 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 49904651597862 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 97462078889 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 490185614 # Number of instructions committed -system.cpu1.committedOps 576425305 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 528528005 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 428357 # Number of float alu accesses -system.cpu1.num_func_calls 28391089 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75589435 # number of instructions that are conditional controls -system.cpu1.num_int_insts 528528005 # number of integer instructions -system.cpu1.num_fp_insts 428357 # number of float instructions -system.cpu1.num_int_register_reads 777707533 # number of times the integer registers were read -system.cpu1.num_int_register_writes 419943205 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 679275 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 386980 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131115369 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 130866277 # number of times the CC registers were written -system.cpu1.num_mem_refs 175739961 # number of memory refs -system.cpu1.num_load_insts 91884045 # Number of load instructions -system.cpu1.num_store_insts 83855916 # Number of store instructions -system.cpu1.num_idle_cycles 96357307601.045395 # Number of idle cycles -system.cpu1.num_busy_cycles 1104780630.954602 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011335 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988665 # Percentage of idle cycles -system.cpu1.Branches 109487364 # Number of branches fetched +system.cpu1.committedInsts 490041805 # Number of instructions committed +system.cpu1.committedOps 576188859 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 528250212 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 430484 # Number of float alu accesses +system.cpu1.num_func_calls 28340797 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75581054 # number of instructions that are conditional controls +system.cpu1.num_int_insts 528250212 # number of integer instructions +system.cpu1.num_fp_insts 430484 # number of float instructions +system.cpu1.num_int_register_reads 777868472 # number of times the integer registers were read +system.cpu1.num_int_register_writes 419771352 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 687105 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 379048 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131312247 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131056135 # number of times the CC registers were written +system.cpu1.num_mem_refs 175584466 # number of memory refs +system.cpu1.num_load_insts 91803674 # Number of load instructions +system.cpu1.num_store_insts 83780792 # Number of store instructions +system.cpu1.num_idle_cycles 96359431608.339264 # Number of idle cycles +system.cpu1.num_busy_cycles 1102647280.660740 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011314 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988686 # Percentage of idle cycles +system.cpu1.Branches 109433272 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 399711275 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1178043 0.20% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 49858 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55322 0.01% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::MemRead 91884045 15.93% 85.46% # Class of executed instruction -system.cpu1.op_class::MemWrite 83855916 14.54% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 399627658 69.32% 69.32% # Class of executed instruction +system.cpu1.op_class::IntMult 1180080 0.20% 69.52% # Class of executed instruction +system.cpu1.op_class::IntDiv 50598 0.01% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 54286 0.01% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::MemRead 91803674 15.92% 85.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 83780792 14.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 576734502 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40249 # Transaction distribution -system.iobus.trans_dist::ReadResp 40249 # Transaction distribution +system.cpu1.op_class::total 576497131 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40242 # Transaction distribution +system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) @@ -739,11 +739,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353528 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -758,55 +758,55 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492000 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115466 # number of replacements +system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113303009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852512 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses -system.iocache.demand_misses::total 115524 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses +system.iocache.demand_misses::total 115517 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115484 # number of overall misses -system.iocache.overall_misses::total 115524 # number of overall misses +system.iocache.overall_misses::realview.ide 115477 # number of overall misses +system.iocache.overall_misses::total 115517 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -828,283 +828,284 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1725552 # number of replacements -system.l2c.tags.tagsinuse 65318.589868 # Cycle average of tags in use -system.l2c.tags.total_refs 46997821 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1788325 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.280358 # Average number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1725785 # number of replacements +system.l2c.tags.tagsinuse 65319.566840 # Cycle average of tags in use +system.l2c.tags.total_refs 46977185 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1788801 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 26.261828 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37152.914726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.952834 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.226181 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3473.573916 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9619.511696 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.800333 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 210.267974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2624.848804 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11683.493403 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.566908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002395 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37198.027902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 157.533597 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.219072 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3426.787378 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9571.465720 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.009111 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 207.682961 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2648.640796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11713.200303 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.567597 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002404 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.003711 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.053003 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146782 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002347 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040052 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.178276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996683 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 268 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62505 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 604 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2729 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4885 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54176 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.953751 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 426507397 # Number of tag accesses -system.l2c.tags.data_accesses 426507397 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 281107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 145752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 278085 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 143361 # number of ReadReq hits -system.l2c.ReadReq_hits::total 848305 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8920157 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8920157 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 14273844 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 14273844 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5706 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5507 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11213 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 857396 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 833383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1690779 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 7117565 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 7075337 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 14192902 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3760971 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3740845 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 7501816 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 343266 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 350428 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 693694 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 281107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 145752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7117565 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4618367 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 278085 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 143361 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7075337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4574228 # number of demand (read+write) hits -system.l2c.demand_hits::total 24233802 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 281107 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 145752 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7117565 # number of overall hits -system.l2c.overall_hits::cpu0.data 4618367 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 278085 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 143361 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7075337 # number of overall hits -system.l2c.overall_hits::cpu1.data 4574228 # number of overall hits -system.l2c.overall_hits::total 24233802 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3220 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2920 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3229 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2911 # number of ReadReq misses -system.l2c.ReadReq_misses::total 12280 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 20037 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19894 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 39931 # number of UpgradeReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.052289 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146049 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002335 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003169 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.178729 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996697 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 315 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62701 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 315 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54255 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004807 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.956741 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 426273955 # Number of tag accesses +system.l2c.tags.data_accesses 426273955 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 280712 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 145885 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 277418 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 142199 # number of ReadReq hits +system.l2c.ReadReq_hits::total 846214 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8916863 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8916863 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 14263678 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 5752 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5452 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11204 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 852175 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 837197 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1689372 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 7090160 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 7092615 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 14182775 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3753750 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3744981 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 7498731 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 340284 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 354276 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 694560 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 280712 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 145885 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7090160 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4605925 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 277418 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 142199 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7092615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4582178 # number of demand (read+write) hits +system.l2c.demand_hits::total 24217092 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 280712 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 145885 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7090160 # number of overall hits +system.l2c.overall_hits::cpu0.data 4605925 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 277418 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 142199 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7092615 # number of overall hits +system.l2c.overall_hits::cpu1.data 4582178 # number of overall hits +system.l2c.overall_hits::total 24217092 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3224 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2941 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3244 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2893 # number of ReadReq misses +system.l2c.ReadReq_misses::total 12302 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 20291 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19639 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 39930 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 416846 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 410397 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 827243 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 48841 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 34193 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 83034 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 177933 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 165976 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 343909 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 422389 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 130134 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 552523 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3220 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2920 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 48841 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 594779 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3229 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2911 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 34193 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 576373 # number of demand (read+write) misses -system.l2c.demand_misses::total 1266466 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3220 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2920 # number of overall misses -system.l2c.overall_misses::cpu0.inst 48841 # number of overall misses -system.l2c.overall_misses::cpu0.data 594779 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3229 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2911 # number of overall misses -system.l2c.overall_misses::cpu1.inst 34193 # number of overall misses -system.l2c.overall_misses::cpu1.data 576373 # number of overall misses -system.l2c.overall_misses::total 1266466 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 284327 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 148672 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 281314 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 146272 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 860585 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 8920157 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 8920157 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 14273844 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 14273844 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25743 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 25401 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51144 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 417161 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 410444 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 827605 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 48524 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 34473 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 82997 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 177534 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 166566 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 344100 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 421273 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 130939 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 552212 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3224 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2941 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 48524 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 594695 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3244 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2893 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34473 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 577010 # number of demand (read+write) misses +system.l2c.demand_misses::total 1267004 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3224 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2941 # number of overall misses +system.l2c.overall_misses::cpu0.inst 48524 # number of overall misses +system.l2c.overall_misses::cpu0.data 594695 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3244 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2893 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34473 # number of overall misses +system.l2c.overall_misses::cpu1.data 577010 # number of overall misses +system.l2c.overall_misses::total 1267004 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 283936 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 148826 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 280662 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 145092 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 858516 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 8916863 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 8916863 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 26043 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 25091 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51134 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1274242 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1243780 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2518022 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 7166406 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 7109530 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 14275936 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 3938904 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 3906821 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 7845725 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 765655 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 480562 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 1246217 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 284327 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 148672 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 7166406 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 5213146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 281314 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 146272 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 7109530 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 5150601 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 25500268 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 284327 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 148672 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 7166406 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 5213146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 281314 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 146272 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7109530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 5150601 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 25500268 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019641 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019901 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.014269 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778348 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783198 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.780756 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 1269336 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1247641 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 7138684 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 7127088 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 3931284 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 3911547 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 7842831 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 761557 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 485215 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 283936 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 148826 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7138684 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 5200620 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 280662 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 145092 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7127088 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 5159188 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25484096 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 283936 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 148826 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7138684 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 5200620 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 280662 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 145092 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7127088 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 5159188 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25484096 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019761 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019939 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.014329 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779135 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782711 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.780889 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.327133 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.329959 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.328529 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006815 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004809 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.005816 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045173 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042484 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.043834 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.551670 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.270795 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.443360 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.114092 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004809 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.111904 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049665 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.114092 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004809 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.111904 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049665 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.328645 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.328976 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328809 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006797 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004837 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045159 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042583 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043874 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.553173 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269858 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019761 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006797 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.114351 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.019939 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004837 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.111841 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049717 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019761 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006797 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.114351 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.019939 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004837 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.111841 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049717 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1507035 # number of writebacks -system.l2c.writebacks::total 1507035 # number of writebacks -system.membus.snoop_filter.tot_requests 3814231 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1911351 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2893 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1507087 # number of writebacks +system.l2c.writebacks::total 1507087 # number of writebacks +system.membus.snoop_filter.tot_requests 3814674 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1911370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524759 # Transaction distribution +system.membus.trans_dist::ReadResp 524928 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613666 # Transaction distribution -system.membus.trans_dist::CleanEvict 226120 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40498 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613718 # Transaction distribution +system.membus.trans_dist::CleanEvict 226292 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40499 # Transaction distribution -system.membus.trans_dist::ReadExReq 826686 # Transaction distribution -system.membus.trans_dist::ReadExResp 826686 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448080 # Transaction distribution -system.membus.trans_dist::InvalidateReq 659180 # Transaction distribution -system.membus.trans_dist::InvalidateResp 659180 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40498 # Transaction distribution +system.membus.trans_dist::ReadExReq 827048 # Transaction distribution +system.membus.trans_dist::ReadExResp 827048 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448249 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5533540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5662732 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6009246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5534223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5663415 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6009908 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177661536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 177830586 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185221818 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177699296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 177868346 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185259130 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3924516 # Request fanout histogram -system.membus.snoop_fanout::mean 0.009389 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.096443 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 3924959 # Request fanout histogram +system.membus.snoop_fanout::mean 0.009320 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.096090 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3887667 99.06% 99.06% # Request fanout histogram -system.membus.snoop_fanout::1 36849 0.94% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3888378 99.07% 99.07% # Request fanout histogram +system.membus.snoop_fanout::1 36581 0.93% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3924516 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 3924959 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1147,73 +1148,74 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 52432480 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26546586 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1741 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 52404582 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26532237 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1321968 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23443629 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1320370 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23428973 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8920157 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 14275419 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2689286 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51144 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8916863 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2689192 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51134 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51145 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2518022 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2518022 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 14275936 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7845725 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1246217 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1246217 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42913541 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35065981 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 831270 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1659308 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 80470100 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1827459220 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234359526 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3325080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6637232 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3071781058 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1762525 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 54939201 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.011226 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105357 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 51135 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7842831 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42883049 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35055805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830232 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657150 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 80426236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1233896614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3070004370 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1762480 # Total snoops (count) +system.toL2Bus.snoopTraffic 96494080 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 54910458 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011218 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105318 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 54322443 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 616758 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 54294485 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 615973 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 54939201 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 54910458 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal index 7a2b5d086..e00102254 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal @@ -77,7 +77,7 @@ [ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131281] NET: Registered protocol family 1
-[ 3.131310] RPC: Registered named UNIX socket transport module.
+[ 3.131311] RPC: Registered named UNIX socket transport module.
[ 3.131311] RPC: Registered udp transport module.
[ 3.131312] RPC: Registered tcp transport module.
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
@@ -87,7 +87,7 @@ [ 3.132687] fuse init (API version 7.23)
[ 3.132738] msgmni has been set to 469
[ 3.133992] io scheduler noop registered
-[ 3.134024] io scheduler cfq registered (default)
+[ 3.134025] io scheduler cfq registered (default)
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
@@ -98,24 +98,24 @@ [ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134354] pci_bus 0000:00: fixups for bus
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
-[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
@@ -158,9 +158,9 @@ [ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.446951] udevd[607]: starting version 182
+[ 3.446950] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.532266] random: dd urandom read with 19 bits of entropy available
+[ 3.532262] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini index 35469b90f..8eaa9ebb0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -107,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -125,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -146,12 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -170,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -194,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -210,9 +240,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -223,12 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -247,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -306,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -322,9 +372,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -339,6 +394,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -356,6 +412,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -384,9 +444,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -400,9 +465,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.isa] @@ -455,9 +525,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -471,9 +546,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -491,6 +571,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -535,12 +616,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=true system=system +threadPolicy=RoundRobin tracer=system.cpu2.tracer workload= @@ -586,9 +672,14 @@ walker=system.cpu2.dstage2_mmu.stage2_tlb.walker [system.cpu2.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.dtb] @@ -602,9 +693,14 @@ walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.executeFuncUnits] @@ -1040,9 +1136,14 @@ walker=system.cpu2.istage2_mmu.stage2_tlb.walker [system.cpu2.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.itb] @@ -1056,9 +1157,14 @@ walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu2.tracer] @@ -1089,6 +1195,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -1127,6 +1234,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -1196,9 +1307,14 @@ walker=system.cpu3.dstage2_mmu.stage2_tlb.walker [system.cpu3.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.dtb] @@ -1212,9 +1328,14 @@ walker=system.cpu3.dtb.walker [system.cpu3.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.fuPool] @@ -1574,9 +1695,14 @@ walker=system.cpu3.istage2_mmu.stage2_tlb.walker [system.cpu3.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.itb] @@ -1590,9 +1716,14 @@ walker=system.cpu3.itb.walker [system.cpu3.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu3.tracer] @@ -1623,9 +1754,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1639,12 +1775,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1663,8 +1804,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1675,12 +1821,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1699,8 +1850,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -1708,10 +1864,15 @@ size=4194304 type=CoherentXBar children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 @@ -1725,11 +1886,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1781,6 +1947,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1792,7 +1959,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1835,10 +2006,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1919,14 +2095,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1935,13 +2116,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -2022,10 +2208,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -2105,17 +2296,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -2141,13 +2337,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -2155,14 +2356,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2248,14 +2454,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2264,13 +2475,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2279,13 +2495,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2293,11 +2514,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2311,11 +2537,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2329,12 +2560,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -2402,10 +2638,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2414,11 +2655,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2428,21 +2674,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2452,12 +2708,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2466,10 +2727,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2479,12 +2745,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2494,26 +2765,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2522,10 +2803,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2533,10 +2819,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2544,21 +2835,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2572,11 +2873,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2587,11 +2893,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2599,10 +2910,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2618,10 +2934,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr index b0ba116d4..0585c4372 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr @@ -3,26 +3,39 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 WARNING: Bank is already active! -Command: 0, Timestamp: 8890, Bank: 0 +Command: 0, Timestamp: 9177, Bank: 7 WARNING: Bank is already active! -Command: 0, Timestamp: 9681, Bank: 7 +Command: 0, Timestamp: 9842, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 6687, Bank: 0 +warn: ClockedObject: Already in the requested power state, request ignored warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist WARNING: Bank is already active! -Command: 0, Timestamp: 9468, Bank: 3 +Command: 0, Timestamp: 6757, Bank: 4 WARNING: Bank is already active! -Command: 0, Timestamp: 9409, Bank: 2 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 11862, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 6950, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 7715, Bank: 2 +WARNING: Bank is already active! +Command: 0, Timestamp: 9276, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 9425, Bank: 7 +WARNING: Bank is already active! +Command: 0, Timestamp: 7937, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9436, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 7228, Bank: 1 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -33,6 +46,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9037, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -40,7 +55,7 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6517, Bank: 3 +Command: 0, Timestamp: 11117, Bank: 3 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -61,10 +76,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -135,10 +148,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -155,40 +164,16 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 7601, Bank: 1 -WARNING: Bank is already active! -Command: 0, Timestamp: 7443, Bank: 1 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: Bank is not active! -Command: 1, Timestamp: 5441, Bank: 7 -WARNING: Bank is not active! -Command: 1, Timestamp: 5583, Bank: 7 -WARNING: Bank is not active! -Command: 1, Timestamp: 5642, Bank: 7 -WARNING: Bank is not active! -Command: 1, Timestamp: 5744, Bank: 7 -WARNING: Bank is not active! -Command: 1, Timestamp: 5805, Bank: 7 -WARNING: Bank is not active! -Command: 1, Timestamp: 5897, Bank: 7 -WARNING: Bank is not active! -Command: 1, Timestamp: 6007, Bank: 7 -WARNING: Bank is already active! -Command: 0, Timestamp: 6564, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11135, Bank: 7 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -221,10 +206,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -244,25 +225,31 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: Bank is already active! -Command: 0, Timestamp: 10204, Bank: 6 +Command: 0, Timestamp: 10309, Bank: 6 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 8301, Bank: 7 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -271,16 +258,16 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7445, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7567, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -289,10 +276,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7119, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11014, Bank: 7 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -305,10 +300,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -319,6 +314,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6702, Bank: 6 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -335,14 +338,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -353,24 +360,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 10284, Bank: 6 +Command: 0, Timestamp: 10919, Bank: 1 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is not active! -Command: 1, Timestamp: 3928, Bank: 1 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11762, Bank: 7 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -383,18 +388,26 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 9036, Bank: 2 +WARNING: Bank is already active! +Command: 0, Timestamp: 9399, Bank: 3 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9127, Bank: 1 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -403,6 +416,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -431,28 +448,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 7643, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -465,6 +472,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10476, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 7 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -473,14 +484,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6764, Bank: 7 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -489,16 +492,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8559, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7033, Bank: 5 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -517,20 +516,20 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 7772, Bank: 1 -WARNING: Bank is already active! -Command: 0, Timestamp: 8190, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9257, Bank: 5 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -539,14 +538,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -563,12 +562,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -595,10 +588,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -609,10 +598,12 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 6747, Bank: 6 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -631,8 +622,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -647,6 +640,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -661,14 +656,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -677,34 +672,36 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6808, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6514, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -715,6 +712,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -733,10 +736,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -761,18 +760,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -785,14 +776,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -806,39 +789,26 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: Bank is not active! -Command: 1, Timestamp: 4731, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 4795, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 4818, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 5308, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 5494, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 5524, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 5619, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 5650, Bank: 1 +Command: 1, Timestamp: 3068, Bank: 0 WARNING: Bank is not active! -Command: 1, Timestamp: 5683, Bank: 1 +Command: 1, Timestamp: 3098, Bank: 0 WARNING: Bank is not active! -Command: 1, Timestamp: 5714, Bank: 1 +Command: 1, Timestamp: 3558, Bank: 0 WARNING: Bank is not active! -Command: 1, Timestamp: 5778, Bank: 1 +Command: 1, Timestamp: 3589, Bank: 0 WARNING: Bank is not active! -Command: 1, Timestamp: 6025, Bank: 1 -WARNING: Bank is not active! -Command: 1, Timestamp: 6210, Bank: 1 +Command: 1, Timestamp: 4444, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 1 -WARNING: Bank is already active! -Command: 0, Timestamp: 6993, Bank: 2 +Command: 0, Timestamp: 8010, Bank: 6 WARNING: Bank is already active! -Command: 0, Timestamp: 12168, Bank: 0 +Command: 0, Timestamp: 6841, Bank: 4 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -847,6 +817,13 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10958, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 11294, Bank: 4 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -863,16 +840,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -881,6 +856,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is not active! +Command: 1, Timestamp: 2670, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -901,18 +878,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -921,8 +892,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9949, Bank: 7 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -931,16 +900,16 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -953,6 +922,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -965,10 +938,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -981,10 +950,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1029,12 +998,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -1049,24 +1012,12 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7906, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1089,10 +1040,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -1103,10 +1062,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1119,10 +1074,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1133,10 +1084,16 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1145,6 +1102,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1157,12 +1118,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1173,8 +1136,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6595, Bank: 3 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1183,12 +1146,12 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1197,6 +1160,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1225,14 +1192,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1249,6 +1208,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1257,14 +1220,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1277,24 +1236,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 7186, Bank: 3 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 7 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +Command: 0, Timestamp: 8776, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 6486, Bank: 7 WARNING: Bank is already active! -Command: 0, Timestamp: 6508, Bank: 1 +Command: 0, Timestamp: 10876, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 7192, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 7939, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1313,6 +1270,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9355, Bank: 1 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1321,8 +1280,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 6642, Bank: 4 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1339,34 +1300,32 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 6828, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 10183, Bank: 6 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1393,6 +1352,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1417,7 +1378,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout index aea4301d6..a4a16d087 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 13:54:27 -gem5 executing on e104799-lin, pid 12846 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:21 +gem5 executing on e108600-lin, pid 23069 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index d111f5f05..832def903 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.316243 # Number of seconds simulated -sim_ticks 51316242679000 # Number of ticks simulated -final_tick 51316242679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.316261 # Number of seconds simulated +sim_ticks 51316261201000 # Number of ticks simulated +final_tick 51316261201000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 261245 # Simulator instruction rate (inst/s) -host_op_rate 306975 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15616250138 # Simulator tick rate (ticks/s) -host_mem_usage 693224 # Number of bytes of host memory used -host_seconds 3286.08 # Real time elapsed on the host -sim_insts 858473131 # Number of instructions simulated -sim_ops 1008744567 # Number of ops (including micro ops) simulated +host_inst_rate 254859 # Simulator instruction rate (inst/s) +host_op_rate 299482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15269258413 # Simulator tick rate (ticks/s) +host_mem_usage 686176 # Number of bytes of host memory used +host_seconds 3360.76 # Real time elapsed on the host +sim_insts 856517636 # Number of instructions simulated +sim_ops 1006486660 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 84032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 93120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2529588 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19493128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 22656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 23808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 606400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5209600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 35264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 30848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1545600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 6997952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 75392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 63744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1527168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 11329792 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 446016 # Number of bytes read from this memory -system.physmem.bytes_read::total 50114108 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2529588 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 606400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1545600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1527168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6208756 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69736384 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 89408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 88064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2284980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19216392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 19648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 18624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 651264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5282880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 33920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 30784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1695808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 7120960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 74240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 63168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1609856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 11459776 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 417920 # Number of bytes read from this memory +system.physmem.bytes_read::total 50157692 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2284980 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 651264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1695808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1609856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6241908 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69878272 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69756964 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1455 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 79932 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 304593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 354 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 551 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 482 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 24150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 109343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1178 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 23862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 177028 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 823453 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1089631 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69898852 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1397 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1376 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 76110 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 300269 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 481 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 26497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 111265 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 25154 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 179059 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6530 # Number of read requests responded to by this memory +system.physmem.num_reads::total 824134 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1091848 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1092204 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 49294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 379863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 101520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 30119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 136369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 29760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 220784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 976574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 49294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 30119 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 29760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 120990 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1358953 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1094421 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 44527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 374470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 102947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 33046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 138766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 31371 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 223317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 977423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 44527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12691 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 33046 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 31371 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 121636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1361718 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1359354 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1358953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 49294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 380264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 101520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 30119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 136369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 29760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 220784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2335928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 433905 # Number of read requests accepted -system.physmem.writeReqs 477158 # Number of write requests accepted -system.physmem.readBursts 433905 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 477158 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27751808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue -system.physmem.bytesWritten 30536384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27769920 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 30538112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1362119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1361718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 44527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 374871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 102947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 33046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 138766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 31371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 223317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2339542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 438929 # Number of read requests accepted +system.physmem.writeReqs 487711 # Number of write requests accepted +system.physmem.readBursts 438929 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 487711 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28073280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue +system.physmem.bytesWritten 31211968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28091456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 31213504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27002 # Per bank write bursts -system.physmem.perBankRdBursts::1 28908 # Per bank write bursts -system.physmem.perBankRdBursts::2 27684 # Per bank write bursts -system.physmem.perBankRdBursts::3 26367 # Per bank write bursts -system.physmem.perBankRdBursts::4 27601 # Per bank write bursts -system.physmem.perBankRdBursts::5 30822 # Per bank write bursts -system.physmem.perBankRdBursts::6 24976 # Per bank write bursts -system.physmem.perBankRdBursts::7 26194 # Per bank write bursts -system.physmem.perBankRdBursts::8 25034 # Per bank write bursts -system.physmem.perBankRdBursts::9 29693 # Per bank write bursts -system.physmem.perBankRdBursts::10 29082 # Per bank write bursts -system.physmem.perBankRdBursts::11 28850 # Per bank write bursts -system.physmem.perBankRdBursts::12 25459 # Per bank write bursts -system.physmem.perBankRdBursts::13 26397 # Per bank write bursts -system.physmem.perBankRdBursts::14 23675 # Per bank write bursts -system.physmem.perBankRdBursts::15 25878 # Per bank write bursts -system.physmem.perBankWrBursts::0 28116 # Per bank write bursts -system.physmem.perBankWrBursts::1 30181 # Per bank write bursts -system.physmem.perBankWrBursts::2 29513 # Per bank write bursts -system.physmem.perBankWrBursts::3 29673 # Per bank write bursts -system.physmem.perBankWrBursts::4 30639 # Per bank write bursts -system.physmem.perBankWrBursts::5 33377 # Per bank write bursts -system.physmem.perBankWrBursts::6 28958 # Per bank write bursts -system.physmem.perBankWrBursts::7 30258 # Per bank write bursts -system.physmem.perBankWrBursts::8 28970 # Per bank write bursts -system.physmem.perBankWrBursts::9 32487 # Per bank write bursts -system.physmem.perBankWrBursts::10 30224 # Per bank write bursts -system.physmem.perBankWrBursts::11 30351 # Per bank write bursts -system.physmem.perBankWrBursts::12 28039 # Per bank write bursts -system.physmem.perBankWrBursts::13 29604 # Per bank write bursts -system.physmem.perBankWrBursts::14 27578 # Per bank write bursts -system.physmem.perBankWrBursts::15 29163 # Per bank write bursts +system.physmem.perBankRdBursts::0 25285 # Per bank write bursts +system.physmem.perBankRdBursts::1 29259 # Per bank write bursts +system.physmem.perBankRdBursts::2 26350 # Per bank write bursts +system.physmem.perBankRdBursts::3 25668 # Per bank write bursts +system.physmem.perBankRdBursts::4 27357 # Per bank write bursts +system.physmem.perBankRdBursts::5 30719 # Per bank write bursts +system.physmem.perBankRdBursts::6 26473 # Per bank write bursts +system.physmem.perBankRdBursts::7 28031 # Per bank write bursts +system.physmem.perBankRdBursts::8 25079 # Per bank write bursts +system.physmem.perBankRdBursts::9 30131 # Per bank write bursts +system.physmem.perBankRdBursts::10 27758 # Per bank write bursts +system.physmem.perBankRdBursts::11 30805 # Per bank write bursts +system.physmem.perBankRdBursts::12 27043 # Per bank write bursts +system.physmem.perBankRdBursts::13 27394 # Per bank write bursts +system.physmem.perBankRdBursts::14 24672 # Per bank write bursts +system.physmem.perBankRdBursts::15 26621 # Per bank write bursts +system.physmem.perBankWrBursts::0 26756 # Per bank write bursts +system.physmem.perBankWrBursts::1 29816 # Per bank write bursts +system.physmem.perBankWrBursts::2 28574 # Per bank write bursts +system.physmem.perBankWrBursts::3 30074 # Per bank write bursts +system.physmem.perBankWrBursts::4 31364 # Per bank write bursts +system.physmem.perBankWrBursts::5 33348 # Per bank write bursts +system.physmem.perBankWrBursts::6 29983 # Per bank write bursts +system.physmem.perBankWrBursts::7 32184 # Per bank write bursts +system.physmem.perBankWrBursts::8 30191 # Per bank write bursts +system.physmem.perBankWrBursts::9 34064 # Per bank write bursts +system.physmem.perBankWrBursts::10 29741 # Per bank write bursts +system.physmem.perBankWrBursts::11 31916 # Per bank write bursts +system.physmem.perBankWrBursts::12 29919 # Per bank write bursts +system.physmem.perBankWrBursts::13 30461 # Per bank write bursts +system.physmem.perBankWrBursts::14 29114 # Per bank write bursts +system.physmem.perBankWrBursts::15 30182 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 51315242398500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 51315260920500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 433905 # Read request sizes (log2) +system.physmem.readPktSize::6 438929 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 477158 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 336122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 487711 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 342866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -200,189 +200,184 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 10672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 21143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 25817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 26681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 27418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 27969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 29149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 29101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 29270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 28851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 29534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 26977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 25831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 575 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 31802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 30047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 30409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 27749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 27223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 26642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 269 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 269447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216.323596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 135.007957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.795343 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 129144 47.93% 47.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 70137 26.03% 73.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24147 8.96% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12093 4.49% 87.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8137 3.02% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4947 1.84% 92.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4006 1.49% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2935 1.09% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13901 5.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 269447 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 25551 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.968847 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 13.943536 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 23836 93.29% 93.29% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 1606 6.29% 99.57% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 93 0.36% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 3 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 4 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-223 1 0.00% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-287 1 0.00% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::352-383 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-415 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::416-447 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::448-479 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::704-735 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::928-959 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 25551 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 25551 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.673672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.805610 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.967409 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 31 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 43 0.17% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 23775 93.05% 93.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 652 2.55% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 518 2.03% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 117 0.46% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 66 0.26% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 48 0.19% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 173 0.68% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 30 0.12% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 11 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 7 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 8 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 9 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 10 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 6 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::46 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 279155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 212.371879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.666378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 251.561006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 134237 48.09% 48.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 73368 26.28% 74.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25102 8.99% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12608 4.52% 87.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8433 3.02% 90.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5025 1.80% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3984 1.43% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2939 1.05% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13459 4.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 279155 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 26191 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.746211 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.447790 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 9423 35.98% 35.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 15107 57.68% 93.66% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1332 5.09% 98.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 231 0.88% 99.63% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 66 0.25% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 23 0.09% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::144-159 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-399 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 26191 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 26191 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.620404 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.778521 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.884507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 23 0.09% 0.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 48 0.18% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 24431 93.28% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 637 2.43% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 499 1.91% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 119 0.45% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 74 0.28% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 52 0.20% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 187 0.71% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 21 0.08% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 13 0.05% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 20 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 6 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 18 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 7 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-247 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::248-255 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-359 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 25551 # Writes before turning the bus around for reads -system.physmem.totQLat 8250184127 # Total ticks spent queuing -system.physmem.totMemAccLat 16380596627 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2168110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19026.21 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::304-311 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::488-495 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 26191 # Writes before turning the bus around for reads +system.physmem.totQLat 8271276046 # Total ticks spent queuing +system.physmem.totMemAccLat 16495869796 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2193225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18856.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37776.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37606.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.94 # Average write queue length when enqueuing -system.physmem.readRowHits 319229 # Number of row buffer hits during reads -system.physmem.writeRowHits 322075 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.50 # Row buffer hit rate for writes -system.physmem.avgGap 56324581.72 # Average gap between requests -system.physmem.pageHitRate 70.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1046092320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 569142750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1712513400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1559833200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1175245195320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29690777078250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34183875153480 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.616999 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48913778839190 # Time in different power states -system.physmem_0.memoryStateTime::REF 1693745040000 # Time in different power states +system.physmem.avgWrQLen 7.58 # Average write queue length when enqueuing +system.physmem.readRowHits 320460 # Number of row buffer hits during reads +system.physmem.writeRowHits 326715 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.99 # Row buffer hit rate for writes +system.physmem.avgGap 55377774.45 # Average gap between requests +system.physmem.pageHitRate 69.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1063933920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 578980875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1709237400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1568801520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1175120467920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30458927805750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34952000129865 # Total energy per rank (pJ) +system.physmem_0.averagePower 665.969400 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48914934224726 # Time in different power states +system.physmem_0.memoryStateTime::REF 1693778580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 115773933810 # Time in different power states +system.physmem_0.memoryStateTime::ACT 115598736274 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 990927000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 539141625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1669683600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1531975680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1172482833105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29689600432500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34179780291750 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.615252 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48917806002648 # Time in different power states -system.physmem_1.memoryStateTime::REF 1693745040000 # Time in different power states +system.physmem_1.actEnergy 1046477880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 569311875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1712123400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1591410240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1175283684855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29689572406500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34182806317230 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.621570 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48914700007992 # Time in different power states +system.physmem_1.memoryStateTime::REF 1693778580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 111730336352 # Time in different power states +system.physmem_1.memoryStateTime::ACT 115815403258 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -399,9 +394,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -409,7 +404,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -439,49 +434,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 91119 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 91119 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 91119 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 91119 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 91119 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 392500671624 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.508107 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -199432260126 -50.81% -50.81% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 591932931750 150.81% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 392500671624 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 66569 84.97% 84.97% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11779 15.03% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 78348 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91119 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 91599 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 91599 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 91599 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 91599 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 91599 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.489246 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -194134706080 -48.92% -48.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 590938857500 148.92% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 396804151420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 67399 85.01% 85.01% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11889 14.99% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 79288 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91599 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91119 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78348 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91599 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 79288 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78348 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 169467 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 79288 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 170887 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64520896 # DTB read hits -system.cpu0.dtb.read_misses 69076 # DTB read misses -system.cpu0.dtb.write_hits 58341415 # DTB write hits -system.cpu0.dtb.write_misses 22043 # DTB write misses -system.cpu0.dtb.flush_tlb 1192 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 64302418 # DTB read hits +system.cpu0.dtb.read_misses 69160 # DTB read misses +system.cpu0.dtb.write_hits 58215557 # DTB write hits +system.cpu0.dtb.write_misses 22439 # DTB write misses +system.cpu0.dtb.flush_tlb 1189 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41085 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41969 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2806 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2769 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7502 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 64589972 # DTB read accesses -system.cpu0.dtb.write_accesses 58363458 # DTB write accesses +system.cpu0.dtb.perms_faults 7637 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64371578 # DTB read accesses +system.cpu0.dtb.write_accesses 58237996 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 122862311 # DTB hits -system.cpu0.dtb.misses 91119 # DTB misses -system.cpu0.dtb.accesses 122953430 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 122517975 # DTB hits +system.cpu0.dtb.misses 91599 # DTB misses +system.cpu0.dtb.accesses 122609574 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,709 +506,709 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 53727 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53727 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 53727 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53727 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53727 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 392500671624 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.508219 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -199476179626 -50.82% -50.82% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 591976851250 150.82% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 392500671624 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46661 94.95% 94.95% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2481 5.05% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 49142 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 53904 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53904 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 53904 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53904 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53904 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.489341 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -194172707080 -48.93% -48.93% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 590976858500 148.93% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 396804151420 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 47053 95.04% 95.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2454 4.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49507 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53727 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53727 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53904 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53904 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49142 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49142 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 102869 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 342517055 # ITB inst hits -system.cpu0.itb.inst_misses 53727 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49507 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49507 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 103411 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 341562377 # ITB inst hits +system.cpu0.itb.inst_misses 53904 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1192 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1189 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28935 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29855 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 342570782 # ITB inst accesses -system.cpu0.itb.hits 342517055 # DTB hits -system.cpu0.itb.misses 53727 # DTB misses -system.cpu0.itb.accesses 342570782 # DTB accesses -system.cpu0.numPwrStateTransitions 11952 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 5976 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 8382866475.975402 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 212039540044.688660 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 2476 41.43% 41.43% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 3476 58.17% 99.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 341616281 # ITB inst accesses +system.cpu0.itb.hits 341562377 # DTB hits +system.cpu0.itb.misses 53904 # DTB misses +system.cpu0.itb.accesses 341616281 # DTB accesses +system.cpu0.numPwrStateTransitions 12142 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6071 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8248096077.910065 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 210376306672.099670 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 2573 42.38% 42.38% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 3474 57.22% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.69% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 4 0.07% 99.77% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 9 0.15% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7947193331000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 5976 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1220232618571 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 50096010060429 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 413468946 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7947193303500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 6071 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1242069912008 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074191288992 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 412426852 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16570 # number of quiesce instructions executed -system.cpu0.committedInsts 342362794 # Number of instructions committed -system.cpu0.committedOps 402636690 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 369953687 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 353210 # Number of float alu accesses -system.cpu0.num_func_calls 20646613 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 51970284 # number of instructions that are conditional controls -system.cpu0.num_int_insts 369953687 # number of integer instructions -system.cpu0.num_fp_insts 353210 # number of float instructions -system.cpu0.num_int_register_reads 539846960 # number of times the integer registers were read -system.cpu0.num_int_register_writes 293703337 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 568892 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 300360 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 89273277 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 89056803 # number of times the CC registers were written -system.cpu0.num_mem_refs 122937235 # number of memory refs -system.cpu0.num_load_insts 64579480 # Number of load instructions -system.cpu0.num_store_insts 58357755 # Number of store instructions -system.cpu0.num_idle_cycles 403595961.081611 # Number of idle cycles -system.cpu0.num_busy_cycles 9872984.918389 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023878 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976122 # Percentage of idle cycles -system.cpu0.Branches 76352356 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16568 # number of quiesce instructions executed +system.cpu0.committedInsts 341412971 # Number of instructions committed +system.cpu0.committedOps 401608369 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 368837990 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 362244 # Number of float alu accesses +system.cpu0.num_func_calls 20461819 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 51941822 # number of instructions that are conditional controls +system.cpu0.num_int_insts 368837990 # number of integer instructions +system.cpu0.num_fp_insts 362244 # number of float instructions +system.cpu0.num_int_register_reads 539535569 # number of times the integer registers were read +system.cpu0.num_int_register_writes 292940682 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 578749 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 318148 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89683557 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89472336 # number of times the CC registers were written +system.cpu0.num_mem_refs 122593410 # number of memory refs +system.cpu0.num_load_insts 64360945 # Number of load instructions +system.cpu0.num_store_insts 58232465 # Number of store instructions +system.cpu0.num_idle_cycles 402405334.403935 # Number of idle cycles +system.cpu0.num_busy_cycles 10021517.596065 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024299 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975701 # Percentage of idle cycles +system.cpu0.Branches 76142746 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 278960942 69.24% 69.24% # Class of executed instruction -system.cpu0.op_class::IntMult 898467 0.22% 69.46% # Class of executed instruction -system.cpu0.op_class::IntDiv 41470 0.01% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 45104 0.01% 69.49% # Class of executed instruction +system.cpu0.op_class::IntAlu 278290201 69.25% 69.25% # Class of executed instruction +system.cpu0.op_class::IntMult 876142 0.22% 69.47% # Class of executed instruction +system.cpu0.op_class::IntDiv 42968 0.01% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 47686 0.01% 69.49% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::MemRead 64579480 16.03% 85.51% # Class of executed instruction -system.cpu0.op_class::MemWrite 58357755 14.49% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 64360945 16.02% 85.51% # Class of executed instruction +system.cpu0.op_class::MemWrite 58232465 14.49% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 402883218 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 9811129 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 296592840 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9811641 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.228668 # Average number of references to valid blocks. +system.cpu0.op_class::total 401850407 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 9785258 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999715 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 296102427 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9785770 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.258470 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.870770 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.381737 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.192700 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 6.554509 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968498 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008558 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010142 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.012802 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.924139 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.613790 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.156237 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.305549 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970555 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009011 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010071 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.010362 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1256795104 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1256795104 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 60226997 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 19487622 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26552483 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 46438516 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 152705618 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55178222 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17776476 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23635965 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 39304314 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135894977 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 162747 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47920 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 80030 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112762 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 403459 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128939 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43352 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 57616 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 100015 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 329922 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1452193 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 455982 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 583951 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 952022 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3444148 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1544925 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 494526 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 631378 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1099805 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3770634 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 115534158 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 37307450 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 50246064 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 85842845 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 288930517 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 115696905 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 37355370 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 50326094 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 85955607 # number of overall hits -system.cpu0.dcache.overall_hits::total 289333976 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2119141 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 646622 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 956573 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3413419 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7135755 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 824381 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 254255 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 649910 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3547380 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5275926 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 507242 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 136623 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 211405 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 339128 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1194398 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 658327 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 110099 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 158553 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 301342 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1228321 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 93463 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38738 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47683 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 182809 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 362693 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3601849 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1010976 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1765036 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 7262141 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13640002 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4109091 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1147599 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1976441 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 7601269 # number of overall misses -system.cpu0.dcache.overall_misses::total 14834400 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9793359500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15230666500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 50513918000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 75537944000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 7272358500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18053796000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96990581909 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 122316736409 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 1773607500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 2664287500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 5725219049 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 10163114049 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 551392000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 676206000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2266593000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3494191000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 213500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 213500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 18839325500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 35948750000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 153229718958 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 208017794458 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 18839325500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 35948750000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 153229718958 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 208017794458 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 62346138 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 20134244 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 27509056 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 49851935 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 159841373 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 56002603 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 18030731 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 24285875 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 42851694 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 141170903 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 669989 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 184543 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 291435 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 451890 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1597857 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 787266 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 153451 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 216169 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 401357 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1558243 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1545656 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 494720 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 631634 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1134831 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3806841 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1544925 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 494526 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 631378 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1099814 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3770643 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 119136007 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 38318426 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 52011100 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 93104986 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 302570519 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 119805996 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 38502969 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 52302535 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 93556876 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 304168376 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033990 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032116 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.034773 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.068471 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.044643 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014720 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014101 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.026761 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.082783 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037373 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757090 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.740332 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.725393 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.750466 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747500 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.836219 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.717486 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.733468 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.750808 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788273 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060468 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078303 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.075492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.161089 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095274 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030233 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026384 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.033936 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.077999 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.045080 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034298 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029805 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.037789 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.081248 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048770 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15145.416488 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15922.116242 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14798.628003 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10585.837658 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28602.617451 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27778.917081 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27341.469453 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23183.937077 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16109.206260 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16803.765933 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18999.074304 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 8273.988680 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14233.878879 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14181.280540 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12398.694813 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9634.018302 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 23722.222222 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23722.222222 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18634.790044 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20367.148319 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21099.799489 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15250.569205 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16416.296546 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18188.627943 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20158.439197 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14022.663165 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9944782 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 9746 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 902340 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 268 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.021103 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 36.365672 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 7599024 # number of writebacks -system.cpu0.dcache.writebacks::total 7599024 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 1975 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 105532 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1864101 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 1971608 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 21 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 285967 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2944550 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3230538 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 15 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2055 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2070 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9000 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10827 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 112609 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132436 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1996 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 391514 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 4810706 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 5204216 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1996 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 391514 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 4810706 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 5204216 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 644647 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 851041 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1549318 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3045006 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 254234 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 363943 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 602830 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1221007 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 136623 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 211302 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 334293 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 682218 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 110099 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 158538 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 299287 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 567924 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29738 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 36856 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 70200 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136794 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 1008980 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 1373522 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 2451435 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4833937 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1145603 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 1584824 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 2785728 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5516155 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4882 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4749 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4953 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14584 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4421 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4248 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4892 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13561 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9303 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8997 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 9845 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 28145 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9121433500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12645799500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23323825500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45091058500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 7016829000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9574333500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17420995002 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34012157502 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2255733000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2960339500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4961141000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10177213500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 1663508500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 2505341000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 5348384049 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 9517233549 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 386430500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 476830000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 929349500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1792610000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 204500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 204500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 17801771000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 24725474000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 46093204551 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 88620449551 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 20057504000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 27685813500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 51054345551 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 98797663051 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 895533000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 849199000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 903591500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2648323500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 895533000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 849199000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 903591500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2648323500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032017 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030937 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031078 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019050 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014100 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014986 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014068 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008649 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.740332 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.725040 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.739766 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.426958 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.717486 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.733398 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.745688 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.364464 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060111 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.058350 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061859 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035934 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026408 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026330 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015976 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029754 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030301 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029776 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018135 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14149.501200 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14859.213011 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15054.253226 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14808.200214 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27599.884359 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26307.233550 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 28898.686200 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27855.825153 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16510.638765 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14009.992807 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 14840.696634 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14917.831983 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15109.206260 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15802.779144 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17870.418859 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16757.935127 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12994.501984 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12937.649229 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13238.596866 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13104.449026 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 22722.222222 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22722.222222 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17643.333862 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18001.512899 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18802.539962 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18332.975699 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.250240 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17469.330033 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18327.110741 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17910.603138 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183435.682098 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 178816.382396 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 182433.171815 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181591.024410 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96262.818446 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 94386.906747 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 91781.767395 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94095.700835 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 15904025 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.975046 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 561201521 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15904537 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.285625 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9929825500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.819191 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.888552 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 30.340063 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.927238 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.921522 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.005642 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.059258 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.013530 # Average percentage of cache occupancy +system.cpu0.dcache.tags.tag_accesses 1254458148 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1254458148 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 60043274 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 19451230 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 26515970 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 46522470 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 152532944 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55058218 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17868348 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23514922 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 39147049 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135588537 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 161685 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47989 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 79490 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113267 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 402431 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128215 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43197 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 56794 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu3.data 101554 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 329760 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1440792 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 445911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 586217 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 965735 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3438655 # 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number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 50167176 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 85884340 # number of overall hits +system.cpu0.dcache.overall_hits::total 288853672 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2089317 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 638437 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 880712 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 3494222 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7102688 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 831050 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 249767 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 653536 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 3486415 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5220768 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 516569 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 133434 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 215040 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 331304 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1196347 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 659058 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 109033 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu2.data 156389 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu3.data 303598 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1228078 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91970 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 40583 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 45717 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 183696 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 361966 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu3.data 11 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3579425 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 997237 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1690637 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 7284235 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13551534 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4095994 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1130671 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1905677 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 7615539 # number of overall misses +system.cpu0.dcache.overall_misses::total 14747881 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9935057500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14094035000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 51705605000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 75734697500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6989560000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18192565500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96246799337 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 121428924837 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 1815402000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 2628863500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 5749220797 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 10193486297 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 588884000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 647558500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2284034500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3520477000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 238500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 238500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 18740019500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 34915464000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 153701625134 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 207357108634 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 18740019500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 34915464000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 153701625134 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 207357108634 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 62132591 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 20089667 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 27396682 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu3.data 50016692 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 159635632 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 55889268 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 18118115 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 24168458 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu3.data 42633464 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 140809305 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 678254 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 181423 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 294530 # 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number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 93055308 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 302002775 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 119487386 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 38541435 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 52072853 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 93499879 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 303601553 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033627 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031779 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.032147 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.069861 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.044493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014870 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.013785 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.027041 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.081776 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037077 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761616 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.735486 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.730112 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.745222 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748288 # 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mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.735486 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.729763 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.734861 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.422241 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716239 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.733511 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.743847 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.363822 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064899 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.054965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060948 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035879 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025929 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026310 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026581 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015995 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029269 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030289 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029948 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018134 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.571555 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14850.426619 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15115.188636 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14927.137852 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26980.166898 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26366.357608 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29142.816894 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27860.348330 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17025.113539 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14624.520208 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15022.624871 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15291.682776 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15650.023387 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15808.981148 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17809.705635 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16842.244197 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13110.996738 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12974.635804 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13232.000114 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13138.428313 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 20681.818182 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20681.818182 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17799.589097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18043.015311 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18824.645773 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18393.135974 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17707.980335 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17577.160226 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18381.062796 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18012.843428 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181572.797677 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 179641.039702 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184783.848498 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181987.987149 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.514573 # 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Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.724807 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.897260 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.967538 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.385439 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.921338 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.005659 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.058530 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.014425 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 593375053 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 593375053 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 337059836 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 108650316 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 66739589 # 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number of writebacks +system.cpu0.icache.writebacks::total 15885620 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 365439 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 365439 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 365439 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 365439 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 365439 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 365439 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1722599 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3878852 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4787746 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10389197 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1722599 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21435986000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48533195500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 59905132390 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 129874313890 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21435986000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48533195500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59905132390 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 129874313890 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.018016 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.018016 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12500.900107 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12500.900107 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12500.900107 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1243,69 +1238,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 32054 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 32054 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4620 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23591 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 32052 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 32052 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 32052 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 28213 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24818.452486 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21684.712498 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13220.953832 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 18569 65.82% 65.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9436 33.45% 99.26% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 123 0.44% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 57 0.20% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 28213 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2332813120 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.567212 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.495462 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1009613500 43.28% 43.28% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1323199620 56.72% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2332813120 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 23591 83.62% 83.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4620 16.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 28211 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32054 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 31142 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31142 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4562 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22714 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 31138 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 31138 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 31138 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27280 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24555.205279 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21409.224401 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 12983.742991 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 17842 65.40% 65.40% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9287 34.04% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 82 0.30% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 48 0.18% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 6 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 4 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 27280 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2381232620 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.574632 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.494399 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1012901000 42.54% 42.54% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1368331620 57.46% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2381232620 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 22714 83.27% 83.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4562 16.73% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27276 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31142 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32054 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31142 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27276 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28211 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 60265 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27276 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 58418 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20818389 # DTB read hits -system.cpu1.dtb.read_misses 24417 # DTB read misses -system.cpu1.dtb.write_hits 18685767 # DTB write hits -system.cpu1.dtb.write_misses 7637 # DTB write misses -system.cpu1.dtb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 20762749 # DTB read hits +system.cpu1.dtb.read_misses 23873 # DTB read misses +system.cpu1.dtb.write_hits 18763804 # DTB write hits +system.cpu1.dtb.write_misses 7269 # DTB write misses +system.cpu1.dtb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 18070 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 17777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 955 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2619 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20842806 # DTB read accesses -system.cpu1.dtb.write_accesses 18693404 # DTB write accesses +system.cpu1.dtb.perms_faults 2493 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20786622 # DTB read accesses +system.cpu1.dtb.write_accesses 18771073 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 39504156 # DTB hits -system.cpu1.dtb.misses 32054 # DTB misses -system.cpu1.dtb.accesses 39536210 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 39526553 # DTB hits +system.cpu1.dtb.misses 31142 # DTB misses +system.cpu1.dtb.accesses 39557695 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1335,154 +1330,154 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 20183 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20183 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 931 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17873 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20183 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20183 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20183 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 18804 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27697.085726 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24882.952231 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14267.961573 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 10321 54.89% 54.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 8257 43.91% 98.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 85 0.45% 99.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 115 0.61% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 9 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 19936 # Table walker walks requested +system.cpu1.itb.walker.walksLong 19936 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 932 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17656 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 19936 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 19936 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 19936 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18588 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27393.103077 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24671.512984 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13247.215063 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 10003 53.81% 53.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 8429 45.35% 99.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 57 0.31% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 80 0.43% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 18804 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18588 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 17873 95.05% 95.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 931 4.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 18804 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17656 94.99% 94.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 932 5.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18588 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20183 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20183 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 19936 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 19936 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18804 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18804 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 38987 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 110361810 # ITB inst hits -system.cpu1.itb.inst_misses 20183 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18588 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18588 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 38524 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 110162476 # ITB inst hits +system.cpu1.itb.inst_misses 19936 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13448 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13192 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 110381993 # ITB inst accesses -system.cpu1.itb.hits 110361810 # DTB hits -system.cpu1.itb.misses 20183 # DTB misses -system.cpu1.itb.accesses 110381993 # DTB accesses -system.cpu1.numPwrStateTransitions 6152 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 3076 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3956828120.931729 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 203372693587.464539 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 983 31.96% 31.96% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 67.95% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 110182412 # ITB inst accesses +system.cpu1.itb.hits 110162476 # DTB hits +system.cpu1.itb.misses 19936 # DTB misses +system.cpu1.itb.accesses 110182412 # DTB accesses +system.cpu1.numPwrStateTransitions 6038 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 3019 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 4031562886.362703 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 205285027256.597076 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 926 30.67% 30.67% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 69.23% 99.90% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.03% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.97% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 1 0.03% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11261492307001 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 3076 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 39145039379014 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171203299986 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 1184092485 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 11261576634501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 3019 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 39144972847071 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171288353929 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 1182097366 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 110287651 # Number of instructions committed -system.cpu1.committedOps 129462738 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 119015901 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 118522 # Number of float alu accesses -system.cpu1.num_func_calls 6563146 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16773404 # number of instructions that are conditional controls -system.cpu1.num_int_insts 119015901 # number of integer instructions -system.cpu1.num_fp_insts 118522 # number of float instructions -system.cpu1.num_int_register_reads 171436551 # number of times the integer registers were read -system.cpu1.num_int_register_writes 94361756 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 191512 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 99140 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 28456563 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 28368844 # number of times the CC registers were written -system.cpu1.num_mem_refs 39501087 # number of memory refs -system.cpu1.num_load_insts 20816799 # Number of load instructions -system.cpu1.num_store_insts 18684288 # Number of store instructions -system.cpu1.num_idle_cycles 1157765533.383607 # Number of idle cycles -system.cpu1.num_busy_cycles 26326951.616393 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022234 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977766 # Percentage of idle cycles -system.cpu1.Branches 24650673 # Number of branches fetched +system.cpu1.committedInsts 110088686 # Number of instructions committed +system.cpu1.committedOps 129237809 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 118887794 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 113577 # Number of float alu accesses +system.cpu1.num_func_calls 6597658 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16662523 # number of instructions that are conditional controls +system.cpu1.num_int_insts 118887794 # number of integer instructions +system.cpu1.num_fp_insts 113577 # number of float instructions +system.cpu1.num_int_register_reads 170702989 # number of times the integer registers were read +system.cpu1.num_int_register_writes 94155610 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 183331 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 96228 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28150227 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28060459 # number of times the CC registers were written +system.cpu1.num_mem_refs 39523640 # number of memory refs +system.cpu1.num_load_insts 20761578 # Number of load instructions +system.cpu1.num_store_insts 18762062 # Number of store instructions +system.cpu1.num_idle_cycles 1155305857.273267 # Number of idle cycles +system.cpu1.num_busy_cycles 26791508.726733 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022664 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977336 # Percentage of idle cycles +system.cpu1.Branches 24572277 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 89732955 69.27% 69.27% # Class of executed instruction -system.cpu1.op_class::IntMult 279120 0.22% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 11472 0.01% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 12221 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 20816799 16.07% 85.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 18684288 14.42% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 89498355 69.21% 69.21% # Class of executed instruction +system.cpu1.op_class::IntMult 266792 0.21% 69.42% # Class of executed instruction +system.cpu1.op_class::IntDiv 10604 0.01% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 12166 0.01% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::MemRead 20761578 16.06% 85.49% # Class of executed instruction +system.cpu1.op_class::MemWrite 18762062 14.51% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 129536897 # Class of executed instruction -system.cpu2.branchPred.lookups 40914061 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28392312 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2019755 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 29835012 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 20286508 # Number of BTB hits +system.cpu1.op_class::total 129311599 # Class of executed instruction +system.cpu2.branchPred.lookups 40882537 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28404958 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2018640 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 29949697 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20329283 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 67.995642 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4999749 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 330951 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1158254 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 808792 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 349462 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 143811 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.cpu2.branchPred.BTBHitPct 67.878092 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4945381 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 329320 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1144842 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 797183 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 347659 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 143486 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1512,61 +1507,66 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 93613 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93613 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7056 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30134 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93613 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93613 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93613 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 37190 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 24826.364614 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 21866.546445 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 12685.900174 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 36979 99.43% 99.43% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 182 0.49% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 14 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 37190 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000359500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000359500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000359500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 30134 81.03% 81.03% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 7056 18.97% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 37190 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93613 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.walker.walks 93219 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93219 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7034 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30340 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93219 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93219 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93219 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 37374 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 25165.904104 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 22274.336205 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 12675.748220 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-32767 24476 65.49% 65.49% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12701 33.98% 99.47% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-98303 113 0.30% 99.78% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::98304-131071 53 0.14% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-294911 6 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 37374 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000359000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000359000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000359000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 30340 81.18% 81.18% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 7034 18.82% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 37374 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93219 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93613 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37190 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93219 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37374 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37190 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 130803 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37374 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 130593 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28720728 # DTB read hits -system.cpu2.dtb.read_misses 78135 # DTB read misses -system.cpu2.dtb.write_hits 25235469 # DTB write hits -system.cpu2.dtb.write_misses 15478 # DTB write misses -system.cpu2.dtb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28583495 # DTB read hits +system.cpu2.dtb.read_misses 77825 # DTB read misses +system.cpu2.dtb.write_hits 25112772 # DTB write hits +system.cpu2.dtb.write_misses 15394 # DTB write misses +system.cpu2.dtb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22245 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2280 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 22760 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 83 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2252 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3881 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28798863 # DTB read accesses -system.cpu2.dtb.write_accesses 25250947 # DTB write accesses +system.cpu2.dtb.perms_faults 3984 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28661320 # DTB read accesses +system.cpu2.dtb.write_accesses 25128166 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 53956197 # DTB hits -system.cpu2.dtb.misses 93613 # DTB misses -system.cpu2.dtb.accesses 54049810 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.hits 53696267 # DTB hits +system.cpu2.dtb.misses 93219 # DTB misses +system.cpu2.dtb.accesses 53789486 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1596,149 +1596,149 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 26529 # Table walker walks requested -system.cpu2.itb.walker.walksLong 26529 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1840 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22126 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 26529 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 26529 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 26529 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 23966 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 28028.290078 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25290.360104 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 14051.232329 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 12906 53.85% 53.85% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 10781 44.98% 98.84% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 94 0.39% 99.23% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 160 0.67% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu2.itb.walker.walks 27359 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27359 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1819 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22616 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27359 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27359 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27359 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24435 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 28370.002046 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 25752.666599 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 13391.544423 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 12572 51.45% 51.45% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 11615 47.53% 98.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 92 0.38% 99.36% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 132 0.54% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::163840-196607 9 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 23966 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000327500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000327500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000327500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 22126 92.32% 92.32% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1840 7.68% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 23966 # Table walker page sizes translated +system.cpu2.itb.walker.walkCompletionTime::196608-229375 5 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24435 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000327000 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000327000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000327000 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 22616 92.56% 92.56% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1819 7.44% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24435 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 26529 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 26529 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27359 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27359 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 23966 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 23966 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 50495 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70694439 # ITB inst hits -system.cpu2.itb.inst_misses 26529 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24435 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24435 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 51794 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70751081 # ITB inst hits +system.cpu2.itb.inst_misses 27359 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 16547 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 17251 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 49134 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 50621 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70720968 # ITB inst accesses -system.cpu2.itb.hits 70694439 # DTB hits -system.cpu2.itb.misses 26529 # DTB misses -system.cpu2.itb.accesses 70720968 # DTB accesses -system.cpu2.numPwrStateTransitions 6922 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 3461 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 14586648609.314360 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 130413867074.756348 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 1099 31.75% 31.75% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 2325 67.18% 98.93% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+10-1e+11 6 0.17% 99.10% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 4 0.12% 99.22% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.25% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 2 0.06% 99.31% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.36% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.39% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.42% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.03% 99.45% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11 1 0.03% 99.48% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::overflows 18 0.52% 100.00% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 1988791943000 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 3461 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 831851842163 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 50484390836837 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 1178523145 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70778440 # ITB inst accesses +system.cpu2.itb.hits 70751081 # DTB hits +system.cpu2.itb.misses 27359 # DTB misses +system.cpu2.itb.accesses 70778440 # DTB accesses +system.cpu2.numPwrStateTransitions 7068 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 3534 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 14278760224.142614 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 128952650694.550415 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 1173 33.19% 33.19% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 2324 65.76% 98.95% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+10-1e+11 6 0.17% 99.12% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 3 0.08% 99.21% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 2 0.06% 99.26% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 2 0.06% 99.32% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.38% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.41% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.43% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.03% 99.46% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11 1 0.03% 99.49% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::overflows 18 0.51% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::max_value 1988791938500 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 3534 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 855122568880 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 50461138632120 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 1176514820 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 148428479 # Number of instructions committed -system.cpu2.committedOps 174146855 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 14845041 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1527 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 5665146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.940007 # CPI: cycles per instruction -system.cpu2.ipc 0.125944 # IPC: instructions per cycle +system.cpu2.committedInsts 148015275 # Number of instructions committed +system.cpu2.committedOps 173576253 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 15019689 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1599 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 5679254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.948604 # CPI: cycles per instruction +system.cpu2.ipc 0.125808 # IPC: instructions per cycle system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 120785530 69.36% 69.36% # Class of committed instruction -system.cpu2.op_class_0::IntMult 363959 0.21% 69.57% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 15220 0.01% 69.58% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 16120 0.01% 69.59% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction -system.cpu2.op_class_0::MemRead 27827190 15.98% 85.56% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 25138836 14.44% 100.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 120466035 69.40% 69.40% # Class of committed instruction +system.cpu2.op_class_0::IntMult 363809 0.21% 69.61% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 14931 0.01% 69.62% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 14962 0.01% 69.63% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction +system.cpu2.op_class_0::MemRead 27697831 15.96% 85.59% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 25018685 14.41% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 174146855 # Class of committed instruction +system.cpu2.op_class_0::total 173576253 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 278422703 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 900100442 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 75872804 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50609506 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3388105 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 51366888 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 34595075 # Number of BTB hits +system.cpu2.tickCycles 278505998 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 898008822 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 76056401 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50755289 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3415271 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 50793125 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 34573256 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 67.348980 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9780520 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 107006 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 3035481 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1551109 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 1484372 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 245540 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.cpu3.branchPred.BTBHitPct 68.066802 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9840520 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 107050 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 3054055 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1548215 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 1505840 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 248236 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1768,99 +1768,95 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 515601 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 515601 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8515 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50947 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 323770 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 191831 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2186.536587 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 12259.515456 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-32767 187758 97.88% 97.88% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-65535 2920 1.52% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-98303 506 0.26% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-131071 334 0.17% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-163839 139 0.07% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::163840-196607 61 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-229375 40 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::229376-262143 20 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-294911 20 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::294912-327679 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-360447 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::360448-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-425983 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::425984-458751 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.walker.walks 519832 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 519832 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8563 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50762 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 324579 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 195253 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2247.443061 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 12961.897479 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-32767 191171 97.91% 97.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-65535 2882 1.48% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-98303 501 0.26% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-131071 350 0.18% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-163839 155 0.08% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::163840-196607 49 0.03% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-229375 39 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::229376-262143 21 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-294911 33 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::294912-327679 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-360447 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::360448-393215 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-425983 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::425984-458751 14 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 191831 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 241555 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22389.801494 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18267.883118 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 16107.200178 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-32767 187656 77.69% 77.69% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-65535 48957 20.27% 97.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3861 1.60% 99.55% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::98304-131071 637 0.26% 99.82% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-163839 131 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::163840-196607 99 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-229375 72 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::229376-262143 72 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-294911 24 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::294912-327679 10 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-360447 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::425984-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 241555 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -21501827588 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean -0.278457 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -22090252588 102.74% 102.74% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 330768000 -1.54% 101.20% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 106533500 -0.50% 100.70% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 66241000 -0.31% 100.39% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 26933500 -0.13% 100.27% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 15179500 -0.07% 100.20% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 14407500 -0.07% 100.13% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 23051000 -0.11% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 5101000 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 177500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 28500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 4000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -21501827588 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 50947 85.68% 85.68% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8515 14.32% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 59462 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 515601 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkWaitTime::total 195253 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 240674 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 22283.310619 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 18185.362858 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 16504.392629 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 236088 98.09% 98.09% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 4155 1.73% 99.82% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 185 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 125 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 40 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 50 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 22 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 240674 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -21483315588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.617433 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -22069775588 102.73% 102.73% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 326975000 -1.52% 101.21% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 109953500 -0.51% 100.70% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 66787000 -0.31% 100.39% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 27414500 -0.13% 100.26% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 14643500 -0.07% 100.19% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 14038500 -0.07% 100.12% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 22874000 -0.11% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 3351000 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 112000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 25000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 22000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::48-51 17000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::52-55 205500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::56-59 41500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -21483315588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 50762 85.57% 85.57% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8563 14.43% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 59325 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 519832 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 515601 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59462 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 519832 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59325 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59462 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 575063 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59325 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 579157 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 59668425 # DTB read hits -system.cpu3.dtb.read_misses 351201 # DTB read misses -system.cpu3.dtb.write_hits 46869082 # DTB write hits -system.cpu3.dtb.write_misses 164400 # DTB write misses -system.cpu3.dtb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 59705170 # DTB read hits +system.cpu3.dtb.read_misses 356680 # DTB read misses +system.cpu3.dtb.write_hits 46676545 # DTB write hits +system.cpu3.dtb.write_misses 163152 # DTB write misses +system.cpu3.dtb.flush_tlb 1183 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29715 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 5087 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 29163 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 78 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 4872 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 32866 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 60019626 # DTB read accesses -system.cpu3.dtb.write_accesses 47033482 # DTB write accesses +system.cpu3.dtb.perms_faults 30504 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 60061850 # DTB read accesses +system.cpu3.dtb.write_accesses 46839697 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 106537507 # DTB hits -system.cpu3.dtb.misses 515601 # DTB misses -system.cpu3.dtb.accesses 107053108 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.hits 106381715 # DTB hits +system.cpu3.dtb.misses 519832 # DTB misses +system.cpu3.dtb.accesses 106901547 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1890,399 +1886,393 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 59193 # Table walker walks requested -system.cpu3.itb.walker.walksLong 59193 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2031 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40773 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8103 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 51090 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1228.772754 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 7780.748037 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 50655 99.15% 99.15% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 286 0.56% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 82 0.16% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 46 0.09% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 10 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu3.itb.walker.walks 58984 # Table walker walks requested +system.cpu3.itb.walker.walksLong 58984 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2019 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40730 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8213 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 50771 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1255.214591 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 7667.557499 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 50302 99.08% 99.08% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 327 0.64% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 93 0.18% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 33 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 8 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 51090 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 50907 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 28166.146110 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 24191.673448 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 17123.817204 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-32767 28249 55.49% 55.49% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-65535 21614 42.46% 97.95% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-98303 468 0.92% 98.87% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::98304-131071 440 0.86% 99.73% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-163839 42 0.08% 99.82% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::163840-196607 46 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::229376-262143 5 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-360447 8 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 50907 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -25799318884 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.966437 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.171998 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -833253492 3.23% 3.23% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -24994847892 96.88% 100.11% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 25196000 -0.10% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 3318000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 257000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 11500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -25799318884 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 40773 95.26% 95.26% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 2031 4.74% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 42804 # Table walker page sizes translated +system.cpu3.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 50771 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 50962 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 27876.584514 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 23887.788397 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 16739.526598 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-65535 49958 98.03% 98.03% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-131071 889 1.74% 99.77% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-196607 72 0.14% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-327679 9 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 50962 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -21485924088 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 1.063775 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 1402683284 -6.53% -6.53% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -22917683872 106.66% 100.14% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 26044500 -0.12% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 2758500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 237000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 36500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -21485924088 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 40730 95.28% 95.28% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 2019 4.72% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 42749 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59193 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59193 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 58984 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 58984 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42804 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42804 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 101997 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 54025408 # ITB inst hits -system.cpu3.itb.inst_misses 59193 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42749 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42749 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 101733 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 54309249 # ITB inst hits +system.cpu3.itb.inst_misses 58984 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1184 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1183 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 22821 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 22226 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 108557 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 110359 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 54084601 # ITB inst accesses -system.cpu3.itb.hits 54025408 # DTB hits -system.cpu3.itb.misses 59193 # DTB misses -system.cpu3.itb.accesses 54084601 # DTB accesses -system.cpu3.numPwrStateTransitions 7272 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 3636 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 40583971.308581 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 1016609649.397212 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 2250 61.88% 61.88% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::1000-5e+10 1386 38.12% 100.00% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 36040957368 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 3636 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 51168679359322 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 147563319678 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 361836520 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 54368233 # ITB inst accesses +system.cpu3.itb.hits 54309249 # DTB hits +system.cpu3.itb.misses 58984 # DTB misses +system.cpu3.itb.accesses 54368233 # DTB accesses +system.cpu3.numPwrStateTransitions 7050 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 3525 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 48150318.502695 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 1097902153.303432 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 2138 60.65% 60.65% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::1000-5e+10 1387 39.35% 100.00% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::max_value 36013437604 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 3525 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 51146531328278 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 169729872722 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 361675800 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 142346168 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 336897254 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 75872804 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45926704 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 198396992 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7651750 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1405577 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 5653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 1383 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2613876 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 96442 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 3584 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 53899852 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2112674 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 22747 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 348695424 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.129497 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.376512 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 142734990 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 337553362 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 76056401 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45961991 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 197659540 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7720824 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1399327 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 5628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1517 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2684967 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 90171 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 3829 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 54181818 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2125134 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 22298 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 348440253 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.132379 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.378502 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 266239908 76.35% 76.35% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10306563 2.96% 79.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10284239 2.95% 82.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7691718 2.21% 84.46% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15615273 4.48% 88.94% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5057857 1.45% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5501918 1.58% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4845338 1.39% 93.36% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 23152610 6.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 265738138 76.27% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10408686 2.99% 79.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10350946 2.97% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7718330 2.22% 84.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15611358 4.48% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5061575 1.45% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5537323 1.59% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4787480 1.37% 93.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 23226417 6.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 348695424 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.209688 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.931076 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 116362710 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 160827903 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 61169614 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7306733 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 3026861 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11256055 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 810097 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 368055040 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2493002 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 3026861 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 120564311 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 11200780 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 131699731 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 64193761 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 18008282 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 359339338 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 52499 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 958756 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 756701 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 7766170 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2268 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 342255199 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 547447054 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 423264500 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 516863 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 287051688 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 55203506 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 8135865 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 7007620 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 40276067 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 57867192 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 49204017 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7450996 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 7967631 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 341094082 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8138044 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 340373041 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 493634 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 46733837 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 29214718 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 196934 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 348695424 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.976133 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.690131 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 348440253 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.210289 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.933304 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 116402482 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 160353660 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 61341979 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7283918 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 3056510 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11212857 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 815162 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 368532981 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2520228 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 3056510 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 120624207 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 11509026 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 131064171 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 64320905 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 17863677 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 359702121 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 43833 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 968665 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 780315 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 7689356 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2098 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 342552995 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 547002223 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 423527131 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 526597 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 286388562 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 56164428 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 8049002 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6906783 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 40039981 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 58078564 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 48988354 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7585006 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 8037000 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 341408601 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8081994 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 340240717 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 497823 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 47426361 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 29768333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 191877 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 348440253 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.976468 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.690233 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 216968703 62.22% 62.22% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 54146545 15.53% 77.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24769246 7.10% 84.85% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17826986 5.11% 89.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 13092392 3.75% 93.72% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9312814 2.67% 96.39% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6328109 1.81% 98.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3700278 1.06% 99.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2550351 0.73% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 216890475 62.25% 62.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 53877096 15.46% 77.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24807816 7.12% 84.83% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17922235 5.14% 89.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 13075143 3.75% 93.72% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9287871 2.67% 96.39% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6359964 1.83% 98.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3675651 1.05% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2544002 0.73% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 348695424 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 348440253 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1713777 25.74% 25.74% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 17699 0.27% 26.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1135 0.02% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2657686 39.92% 65.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2267999 34.06% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1734447 26.04% 26.04% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 17043 0.26% 26.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1093 0.02% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.31% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2643216 39.68% 66.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2264697 34.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 231084475 67.89% 67.89% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 790161 0.23% 68.12% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 39649 0.01% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 230 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 2 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 1 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.14% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 44022 0.01% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 60938583 17.90% 86.05% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 47475914 13.95% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 231030792 67.90% 67.90% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 845869 0.25% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 38944 0.01% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 198 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 42651 0.01% 68.17% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 61002567 17.93% 86.10% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 47279686 13.90% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 340373041 # Type of FU issued -system.cpu3.iq.rate 0.940682 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6658296 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019562 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1035940060 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 396014860 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 328005954 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 653376 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 333988 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 291600 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 346682688 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 348645 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2712348 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 340240717 # Type of FU issued +system.cpu3.iq.rate 0.940734 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6660496 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019576 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1035420885 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 396967626 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 327898797 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 659121 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 337856 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 293479 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 346548979 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 352224 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2687529 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9520955 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 12048 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 389231 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4853610 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9720232 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 11871 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 394856 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4837016 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2139160 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 4030631 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2125891 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 3923806 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 3026861 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 7711218 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 2621141 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 349315178 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1020364 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 57867192 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 49204017 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6861602 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 115452 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 2462398 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 389231 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1435072 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1591104 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 3026176 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 336329886 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 59659129 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3533928 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 3056510 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 7986555 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 2673304 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 349575098 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1017291 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 58078564 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 48988354 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6756692 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 121038 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 2506923 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 394856 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1446513 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1609649 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3056162 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 336167665 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 59696171 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3560031 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 83052 # number of nop insts executed -system.cpu3.iew.exec_refs 106526406 # number of memory reference insts executed -system.cpu3.iew.exec_branches 62299744 # Number of branches executed -system.cpu3.iew.exec_stores 46867277 # Number of stores executed -system.cpu3.iew.exec_rate 0.929508 # Inst execution rate -system.cpu3.iew.wb_sent 329094434 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 328297554 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 161959018 # num instructions producing a value -system.cpu3.iew.wb_consumers 281119845 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.907309 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.576121 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 46762853 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7941110 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2588965 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 340775286 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.887677 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.879536 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 84503 # number of nop insts executed +system.cpu3.iew.exec_refs 106371515 # number of memory reference insts executed +system.cpu3.iew.exec_branches 62288679 # Number of branches executed +system.cpu3.iew.exec_stores 46675344 # Number of stores executed +system.cpu3.iew.exec_rate 0.929472 # Inst execution rate +system.cpu3.iew.wb_sent 329005088 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 328192276 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 162018804 # num instructions producing a value +system.cpu3.iew.wb_consumers 281033502 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.907421 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576511 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 47454465 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7890117 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2611241 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 340404707 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.887368 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.879512 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 231011602 67.79% 67.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 53095779 15.58% 83.37% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18991936 5.57% 88.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8794245 2.58% 91.52% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6362030 1.87% 93.39% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3754940 1.10% 94.49% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3557662 1.04% 95.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2189630 0.64% 96.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 13017462 3.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 230935782 67.84% 67.84% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 52807469 15.51% 83.35% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18991951 5.58% 88.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8773061 2.58% 91.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6429800 1.89% 93.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3748451 1.10% 94.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3528982 1.04% 95.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2195360 0.64% 96.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 12993851 3.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 340775286 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 257394207 # Number of instructions committed -system.cpu3.commit.committedOps 302498284 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 340404707 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 257000704 # Number of instructions committed +system.cpu3.commit.committedOps 302064229 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 92696643 # Number of memory references committed -system.cpu3.commit.loads 48346236 # Number of loads committed -system.cpu3.commit.membars 2024611 # Number of memory barriers committed -system.cpu3.commit.branches 57446863 # Number of branches committed -system.cpu3.commit.fp_insts 280508 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 277937546 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7603985 # Number of function calls committed. +system.cpu3.commit.refs 92509669 # Number of memory references committed +system.cpu3.commit.loads 48358331 # Number of loads committed +system.cpu3.commit.membars 2078465 # Number of memory barriers committed +system.cpu3.commit.branches 57378073 # Number of branches committed +system.cpu3.commit.fp_insts 281556 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 277690269 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7642177 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 209109353 69.13% 69.13% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 624464 0.21% 69.33% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 29794 0.01% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 38030 0.01% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 48346236 15.98% 85.34% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 44350407 14.66% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 208831181 69.13% 69.13% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 657786 0.22% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 28932 0.01% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 36661 0.01% 69.37% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 48358331 16.01% 85.38% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 44151338 14.62% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 302498284 # Class of committed instruction -system.cpu3.commit.bw_lim_events 13017462 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 674966133 # The number of ROB reads -system.cpu3.rob.rob_writes 706454494 # The number of ROB writes -system.cpu3.timesIdled 2436524 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 13141096 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98718347024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 257394207 # Number of Instructions Simulated -system.cpu3.committedOps 302498284 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.405768 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.405768 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.711355 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.711355 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 395796018 # number of integer regfile reads -system.cpu3.int_regfile_writes 234887439 # number of integer regfile writes -system.cpu3.fp_regfile_reads 565351 # number of floating regfile reads -system.cpu3.fp_regfile_writes 361110 # number of floating regfile writes -system.cpu3.cc_regfile_reads 71210349 # number of cc regfile reads -system.cpu3.cc_regfile_writes 71874336 # number of cc regfile writes -system.cpu3.misc_regfile_reads 658260097 # number of misc regfile reads -system.cpu3.misc_regfile_writes 8003769 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40273 # Transaction distribution -system.iobus.trans_dist::ReadResp 40273 # Transaction distribution +system.cpu3.commit.op_class_0::total 302064229 # Class of committed instruction +system.cpu3.commit.bw_lim_events 12993851 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 674816220 # The number of ROB reads +system.cpu3.rob.rob_writes 707084678 # The number of ROB writes +system.cpu3.timesIdled 2433054 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 13235547 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98724531811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 257000704 # Number of Instructions Simulated +system.cpu3.committedOps 302064229 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.407295 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.407295 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.710583 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.710583 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 395540710 # number of integer regfile reads +system.cpu3.int_regfile_writes 235084371 # number of integer regfile writes +system.cpu3.fp_regfile_reads 573493 # number of floating regfile reads +system.cpu3.fp_regfile_writes 349924 # number of floating regfile writes +system.cpu3.cc_regfile_reads 70842645 # number of cc regfile reads +system.cpu3.cc_regfile_writes 71511543 # number of cc regfile writes +system.cpu3.misc_regfile_reads 656533782 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7924534 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40262 # Transaction distribution +system.iobus.trans_dist::ReadResp 40262 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution system.iobus.trans_dist::WriteResp 136539 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) @@ -2299,11 +2289,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353602 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -2318,22 +2308,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13621500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492008 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13479500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -2345,68 +2335,68 @@ system.iobus.reqLayer16.occupancy 5000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 11667500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 10717000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 21479000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 21643000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 236022564 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 229106103 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 41037000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 70810000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 47420000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115466 # number of replacements -system.iocache.tags.tagsinuse 10.425431 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115455 # number of replacements +system.iocache.tags.tagsinuse 10.425438 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13087288267509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544657 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.880774 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13087296764009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544648 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.880790 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221541 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430048 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651589 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430049 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651590 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039614 # Number of tag accesses +system.iocache.tags.data_accesses 1039614 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses -system.iocache.demand_misses::total 115524 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115473 # number of demand (read+write) misses +system.iocache.demand_misses::total 115513 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115484 # number of overall misses -system.iocache.overall_misses::total 115524 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 1088192723 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1088192723 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 5155830841 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5155830841 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 6244023564 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6244023564 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 6244023564 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6244023564 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 115473 # number of overall misses +system.iocache.overall_misses::total 115513 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 148237434 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 148237434 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 5184314669 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5184314669 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 5332552103 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5332552103 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 5332552103 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5332552103 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115473 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115513 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115473 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115513 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2420,857 +2410,861 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123377.859751 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122862.450378 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48337.122562 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 48337.122562 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 54068.300059 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54049.578997 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 54068.300059 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54049.578997 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22542 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 16827.952549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 16757.566584 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48604.165126 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48604.165126 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 46164.086319 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 46164.086319 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 2296 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2372 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 267 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.503373 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.599251 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 5693 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 5693 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 43488 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 43488 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 49181 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 49181 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 49181 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 49181 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 803542723 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 803542723 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2978631735 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2978631735 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 3782174458 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3782174458 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 3782174458 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3782174458 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.645465 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.642768 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.407710 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.407710 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.425869 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.425721 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.425869 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.425721 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141145.744423 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141145.744423 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68493.187431 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68493.187431 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1175380 # number of replacements -system.l2c.tags.tagsinuse 65273.508044 # Cycle average of tags in use -system.l2c.tags.total_refs 47870421 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1238537 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.650780 # Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::realview.ide 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 43872 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 43872 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 44782 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 44782 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 44782 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 44782 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 102737434 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 102737434 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2987814984 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2987814984 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 3090552418 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3090552418 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 3090552418 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3090552418 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.103303 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.102871 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.411310 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.411310 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.387679 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.387679 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112898.279121 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112898.279121 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68103.003829 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68103.003829 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1178177 # number of replacements +system.l2c.tags.tagsinuse 65299.544871 # Cycle average of tags in use +system.l2c.tags.total_refs 47783107 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1240954 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 38.505140 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36522.594911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.677817 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 187.809125 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3696.971873 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11236.224149 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 38.223238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 48.365437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 755.794708 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1969.239780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 46.667563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 65.236270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2038.056565 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2946.228048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 100.667016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 147.723446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1700.524086 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 3648.504014 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.557291 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002866 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056411 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.171451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000583 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011533 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030048 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 36300.809857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 130.329243 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 195.620388 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3095.266131 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 10240.571353 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 40.874592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 51.867132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1035.336911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2451.400254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 46.677403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 75.693349 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2509.241112 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3335.896210 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 90.056966 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 140.583636 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1763.583672 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 3795.736663 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.553906 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001989 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002985 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.047230 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.156259 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000624 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000791 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.015798 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037405 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000995 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.031098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.044956 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001536 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.002254 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.117461 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003615 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033886 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.034832 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.034369 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020182 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.170574 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.189576 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.241330 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.098725 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.076961 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.075228 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.069659 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.016871 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.076961 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.075228 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.069659 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.016871 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 77766.845156 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18911.221122 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19008.516862 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.052738 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18979.101746 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45750 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45750 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72201.028544 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72024.542634 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89442.929077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 80214.990210 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74958.556091 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74062.168365 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74773.572716 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79572.242152 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77048.923506 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18727.928647 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19459.291299 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20267.105791 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19827.788654 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72828.309288 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 72985.645061 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 85708.127253 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 78510.647630 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72828.309288 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 72985.645061 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 85708.127253 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 78510.647630 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170923.187218 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 166314.592546 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169927.114880 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169084.201865 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89696.549500 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 87787.929310 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 85489.994921 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 87614.993782 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 2708332 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1355057 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2739 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795051 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.774990 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.783926 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.468208 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.209756 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.199867 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.188154 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.116384 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005907 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006831 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005254 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003892 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.039400 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.036596 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.035026 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021415 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.200160 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.189701 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.238606 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.100664 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007080 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005907 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.079166 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003459 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008210 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006831 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.076889 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003908 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.009318 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005254 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.070128 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007080 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005907 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.079166 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003459 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008210 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006831 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.076889 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003908 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.009318 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005254 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.070128 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 79013.712194 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18913.608070 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18989.561217 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18998.883495 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18977.051089 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 46250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 46250 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71831.714040 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72287.057141 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89705.287954 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80433.859946 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74778.438482 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74192.030233 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74608.649517 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80486.688431 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77402.173905 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18735.566349 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19463.878776 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20265.380550 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19802.140652 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72732.217945 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73119.343807 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86156.495668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 78654.645010 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72732.217945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73119.343807 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86156.495668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 78654.645010 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169058.180058 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167139.504277 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172277.427079 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169480.164827 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88675.281812 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88326.069317 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 89096.307554 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 88701.867895 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2714288 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1358609 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3170 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76738 # Transaction distribution -system.membus.trans_dist::ReadResp 443894 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 76739 # Transaction distribution +system.membus.trans_dist::ReadResp 446283 # Transaction distribution system.membus.trans_dist::WriteReq 33648 # Transaction distribution system.membus.trans_dist::WriteResp 33648 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1089631 # Transaction distribution -system.membus.trans_dist::CleanEvict 200219 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35037 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1091848 # Transaction distribution +system.membus.trans_dist::CleanEvict 200785 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35184 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14486 # Transaction distribution -system.membus.trans_dist::ReadExReq 415725 # Transaction distribution -system.membus.trans_dist::ReadExResp 415725 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 367156 # Transaction distribution -system.membus.trans_dist::InvalidateReq 600547 # Transaction distribution -system.membus.trans_dist::InvalidateResp 436040 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14271 # Transaction distribution +system.membus.trans_dist::ReadExReq 414448 # Transaction distribution +system.membus.trans_dist::ReadExResp 414448 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 369544 # Transaction distribution +system.membus.trans_dist::InvalidateReq 602468 # Transaction distribution +system.membus.trans_dist::InvalidateResp 435243 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6760 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3729876 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3859270 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302047 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 302047 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4161317 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3736384 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3865780 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 302176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4167956 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 112629920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 112799278 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7328576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7328576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 120127854 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1179 # Total snoops (count) -system.membus.snoop_fanout::samples 2232317 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015391 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.123101 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 112845536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 113014898 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7362816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 120377714 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 603 # Total snoops (count) +system.membus.snoopTraffic 38528 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2230474 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016353 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.126827 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2197960 98.46% 98.46% # Request fanout histogram -system.membus.snoop_fanout::1 34357 1.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2194000 98.36% 98.36% # Request fanout histogram +system.membus.snoop_fanout::1 36474 1.64% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2232317 # Request fanout histogram -system.membus.reqLayer0.occupancy 46873500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2230474 # Request fanout histogram +system.membus.reqLayer0.occupancy 45941500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1601000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3219472355 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3279160105 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2319703830 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2368546008 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 28713899 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 4606769 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3313,85 +3307,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 52099554 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26383185 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3169 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2082 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 52014816 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26342736 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3149 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2216 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2216 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1490866 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23977004 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1497604 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23943591 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8032732 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15904025 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2315696 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43839 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43848 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2004412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2004412 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15904657 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6582020 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1233125 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1226250 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47799339 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29657154 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 806902 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1734280 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79997675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2035912148 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1036024666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2901928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6114504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3080953246 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1497196 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 38183781 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.016504 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.127404 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 8020601 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15885620 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2314166 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 44021 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44032 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2000482 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2000482 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15886240 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6559913 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1231249 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1225834 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47744160 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29579701 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 811490 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1741524 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79876875 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2033559380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1032953822 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2918064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6139128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3075570394 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1503666 # Total snoops (count) +system.toL2Bus.snoopTraffic 65422752 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 38127714 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016625 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.127861 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 37553594 98.35% 98.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 630187 1.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37493845 98.34% 98.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 633869 1.66% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 38183781 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 31295495912 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 38127714 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 31242309916 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 884168 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 523765 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15602902016 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15589083360 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7909503562 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7892971168 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 285711732 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 287709740 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 709709811 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 712482327 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal index e2578c2a4..60da7d5bf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal @@ -37,28 +37,28 @@ [ 0.000032] pid_max: default: 32768 minimum: 301
[ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000177] hw perfevents: no hardware support available
-[ 1.060045] CPU1: failed to come online
+[ 0.000178] hw perfevents: no hardware support available
+[ 1.060046] CPU1: failed to come online
[ 2.080096] CPU2: failed to come online
[ 3.100147] CPU3: failed to come online
[ 3.100149] Brought up 1 CPUs
[ 3.100150] SMP: Total of 1 processors activated.
[ 3.100176] devtmpfs: initialized
-[ 3.100784] atomic64_test: passed
-[ 3.100838] regulator-dummy: no parameters
+[ 3.100785] atomic64_test: passed
+[ 3.100840] regulator-dummy: no parameters
[ 3.101093] NET: Registered protocol family 16
[ 3.101177] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 3.101181] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 3.101220] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 3.101221] Serial: AMBA PL011 UART driver
-[ 3.101342] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101343] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 3.101365] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 3.101399] console [ttyAMA0] enabled
-[ 3.101503] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.101553] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.101603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.101649] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130355] 3V3: 3300 mV
+[ 3.101504] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.101554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.101604] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.101650] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130356] 3V3: 3300 mV
[ 3.130376] vgaarb: loaded
[ 3.130417] SCSI subsystem initialized
[ 3.130486] libata version 3.00 loaded.
@@ -66,101 +66,101 @@ [ 3.130591] usbcore: registered new interface driver hub
[ 3.130645] usbcore: registered new device driver usb
[ 3.130677] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130686] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130687] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 3.130706] PTP clock support registered
-[ 3.130853] Switched to clocksource arch_sys_counter
-[ 3.131766] NET: Registered protocol family 2
-[ 3.131853] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131874] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131900] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.131914] TCP: reno registered
-[ 3.131921] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131933] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131960] NET: Registered protocol family 1
-[ 3.131995] RPC: Registered named UNIX socket transport module.
-[ 3.132005] RPC: Registered udp transport module.
-[ 3.132012] RPC: Registered tcp transport module.
-[ 3.132020] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132032] PCI: CLS 0 bytes, default 64
-[ 3.132126] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.132190] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.133863] fuse init (API version 7.23)
-[ 3.133946] msgmni has been set to 469
-[ 3.135911] io scheduler noop registered
-[ 3.135957] io scheduler cfq registered (default)
-[ 3.136166] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.136178] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.136189] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.136190] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.136191] pci_bus 0000:00: scanning bus
-[ 3.136194] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.130855] Switched to clocksource arch_sys_counter
+[ 3.131768] NET: Registered protocol family 2
+[ 3.131855] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131877] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131903] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131917] TCP: reno registered
+[ 3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131935] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131962] NET: Registered protocol family 1
+[ 3.131997] RPC: Registered named UNIX socket transport module.
+[ 3.132007] RPC: Registered udp transport module.
+[ 3.132015] RPC: Registered tcp transport module.
+[ 3.132023] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132034] PCI: CLS 0 bytes, default 64
+[ 3.132128] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.132192] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.133873] fuse init (API version 7.23)
+[ 3.133951] msgmni has been set to 469
+[ 3.135925] io scheduler noop registered
+[ 3.135963] io scheduler cfq registered (default)
+[ 3.136172] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.136184] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.136190] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.136191] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.136192] pci_bus 0000:00: scanning bus
+[ 3.136195] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 3.136196] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 3.136199] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136215] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.136217] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.136219] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.136221] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.136222] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.136224] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.136226] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136243] pci_bus 0000:00: fixups for bus
-[ 3.136244] pci_bus 0000:00: bus scan returning with max=00
-[ 3.136246] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.136251] pci 0000:00:00.0: fixup irq: got 33
-[ 3.136252] pci 0000:00:00.0: assigning IRQ 33
-[ 3.136255] pci 0000:00:01.0: fixup irq: got 34
-[ 3.136256] pci 0000:00:01.0: assigning IRQ 34
-[ 3.136258] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.136260] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.136262] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.136216] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.136218] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.136220] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.136222] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.136223] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.136225] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.136227] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.136244] pci_bus 0000:00: fixups for bus
+[ 3.136245] pci_bus 0000:00: bus scan returning with max=00
+[ 3.136247] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.136252] pci 0000:00:00.0: fixup irq: got 33
+[ 3.136253] pci 0000:00:00.0: assigning IRQ 33
+[ 3.136256] pci 0000:00:01.0: fixup irq: got 34
+[ 3.136257] pci 0000:00:01.0: assigning IRQ 34
+[ 3.136259] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.136261] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.136263] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.136264] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.136265] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.136267] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.136269] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.136270] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.136757] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.137006] ata_piix 0000:00:01.0: version 2.13
-[ 3.137015] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.137032] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.137198] scsi0 : ata_piix
-[ 3.137253] scsi1 : ata_piix
-[ 3.137270] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.137271] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.137332] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.137333] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.137337] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.137339] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290857] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290858] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290864] ata1.00: configured for UDMA/33
-[ 3.290881] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.290942] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.290950] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.290964] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.290965] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.290972] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291025] sda: sda1
-[ 3.291087] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.411146] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.411161] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.411190] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.411201] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411232] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411245] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411368] usbcore: registered new interface driver usb-storage
-[ 3.411435] mousedev: PS/2 mouse device common for all mice
-[ 3.411616] usbcore: registered new interface driver usbhid
-[ 3.411625] usbhid: USB HID core driver
-[ 3.411647] TCP: cubic registered
-[ 3.411654] NET: Registered protocol family 17
- -[ 3.411878] devtmpfs: mounted
-[ 3.411886] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 3.136266] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.136268] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.136270] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.136271] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.136760] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.137008] ata_piix 0000:00:01.0: version 2.13
+[ 3.137017] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.137033] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.137199] scsi0 : ata_piix
+[ 3.137254] scsi1 : ata_piix
+[ 3.137271] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.137272] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.137333] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.137334] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.137338] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.137340] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290858] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290859] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290865] ata1.00: configured for UDMA/33
+[ 3.290882] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.290943] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.290951] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.290965] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.290967] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.290973] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.291027] sda: sda1
+[ 3.291088] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.411147] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.411162] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.411191] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.411202] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.411233] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.411246] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.411369] usbcore: registered new interface driver usb-storage
+[ 3.411437] mousedev: PS/2 mouse device common for all mice
+[ 3.411617] usbcore: registered new interface driver usbhid
+[ 3.411627] usbhid: USB HID core driver
+[ 3.411648] TCP: cubic registered
+[ 3.411655] NET: Registered protocol family 17
+ +[ 3.411879] devtmpfs: mounted
+[ 3.411887] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.450099] udevd[607]: starting version 182
+[ 3.450103] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.543144] random: dd urandom read with 19 bits of entropy available
+[ 3.543155] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.681072] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.681074] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini index d0e4571d0..46d508520 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -121,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -159,6 +173,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -198,11 +216,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu0.dcache] type=Cache @@ -211,13 +236,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -236,8 +265,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -260,9 +294,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -276,9 +315,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -596,13 +640,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -621,8 +669,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -680,9 +733,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -696,9 +754,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -730,6 +793,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -768,6 +832,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -805,11 +873,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu1.dstage2_mmu] type=ArmStage2MMU @@ -830,9 +905,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -846,9 +926,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.fuPool] @@ -1208,9 +1293,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1224,9 +1314,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -1257,9 +1352,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1273,13 +1373,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1298,8 +1402,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1310,13 +1419,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1335,20 +1448,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1360,11 +1484,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1375,6 +1504,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -1409,6 +1545,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1420,7 +1557,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1463,10 +1604,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1547,14 +1693,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1563,13 +1714,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1579,6 +1735,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1649,10 +1806,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1732,17 +1894,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1768,12 +1935,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1781,14 +1954,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1874,14 +2052,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1890,13 +2073,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1905,13 +2093,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1919,11 +2112,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1937,11 +2135,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1955,19 +2158,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -2013,14 +2222,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2029,11 +2253,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2043,21 +2272,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2067,12 +2306,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2081,10 +2325,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2094,12 +2343,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2109,26 +2363,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2137,10 +2401,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2148,10 +2417,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2159,21 +2433,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2187,11 +2471,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2202,11 +2491,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2214,10 +2508,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2233,9 +2532,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr index e3ddf9c3f..d1f615ea3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr @@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist @@ -465,79 +467,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout index f47c1d8a7..6b7f60999 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 14:20:09 -gem5 executing on e104799-lin, pid 15456 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:23 +gem5 executing on e108600-lin, pid 23086 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b5baf9b71..576c749c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.317219 # Number of seconds simulated -sim_ticks 51317219225000 # Number of ticks simulated -final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.317224 # Number of seconds simulated +sim_ticks 51317223946000 # Number of ticks simulated +final_tick 51317223946000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237803 # Simulator instruction rate (inst/s) -host_op_rate 279419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13379498708 # Simulator tick rate (ticks/s) -host_mem_usage 700916 # Number of bytes of host memory used -host_seconds 3835.51 # Real time elapsed on the host -sim_insts 912094204 # Number of instructions simulated -sim_ops 1071714405 # Number of ops (including micro ops) simulated +host_inst_rate 160482 # Simulator instruction rate (inst/s) +host_op_rate 188578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9038049637 # Simulator tick rate (ticks/s) +host_mem_usage 694112 # Number of bytes of host memory used +host_seconds 5677.91 # Real time elapsed on the host +sim_insts 911201050 # Number of instructions simulated +sim_ops 1070728401 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 178240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 158592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3667840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 28126168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 173888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 153280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3614336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 28857840 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory -system.physmem.bytes_read::total 65359176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3667840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3614336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7282176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83655232 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 175488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 146560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3612352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 27482328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 187136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 157760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3726080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 29409648 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 423552 # Number of bytes read from this memory +system.physmem.bytes_read::total 65320904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3612352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3726080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7338432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83980672 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 83675812 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 57310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 439479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56474 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 450909 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1021250 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1307113 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 84001252 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 56443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 429419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2465 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 459531 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6618 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1020652 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1312198 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1309686 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 71474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 548084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 562342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1273631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 71474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1630159 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1314771 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 70393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 535538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 573095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1272885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 143001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1636501 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1630560 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1630159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 71474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 548485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 562342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2904191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1021250 # Number of read requests accepted -system.physmem.writeReqs 1309686 # Number of write requests accepted -system.physmem.readBursts 1021250 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1309686 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 65325376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 34624 # Total number of bytes read from write queue -system.physmem.bytesWritten 83676352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 65359176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 83675812 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1636902 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1636501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 535939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 573095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2909786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1020652 # Number of read requests accepted +system.physmem.writeReqs 1314771 # Number of write requests accepted +system.physmem.readBursts 1020652 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1314771 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 65284928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36800 # Total number of bytes read from write queue +system.physmem.bytesWritten 84000896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 65320904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 84001252 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 575 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2239 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 59538 # Per bank write bursts -system.physmem.perBankRdBursts::1 65186 # Per bank write bursts -system.physmem.perBankRdBursts::2 59192 # Per bank write bursts -system.physmem.perBankRdBursts::3 61503 # Per bank write bursts -system.physmem.perBankRdBursts::4 61968 # Per bank write bursts -system.physmem.perBankRdBursts::5 71297 # Per bank write bursts -system.physmem.perBankRdBursts::6 63621 # Per bank write bursts -system.physmem.perBankRdBursts::7 62505 # Per bank write bursts -system.physmem.perBankRdBursts::8 57971 # Per bank write bursts -system.physmem.perBankRdBursts::9 85989 # Per bank write bursts -system.physmem.perBankRdBursts::10 63150 # Per bank write bursts -system.physmem.perBankRdBursts::11 64998 # Per bank write bursts -system.physmem.perBankRdBursts::12 58754 # Per bank write bursts -system.physmem.perBankRdBursts::13 64690 # Per bank write bursts -system.physmem.perBankRdBursts::14 59967 # Per bank write bursts -system.physmem.perBankRdBursts::15 60380 # Per bank write bursts -system.physmem.perBankWrBursts::0 78521 # Per bank write bursts -system.physmem.perBankWrBursts::1 82873 # Per bank write bursts -system.physmem.perBankWrBursts::2 79926 # Per bank write bursts -system.physmem.perBankWrBursts::3 82832 # Per bank write bursts -system.physmem.perBankWrBursts::4 82609 # Per bank write bursts -system.physmem.perBankWrBursts::5 88110 # Per bank write bursts -system.physmem.perBankWrBursts::6 81518 # Per bank write bursts -system.physmem.perBankWrBursts::7 82656 # Per bank write bursts -system.physmem.perBankWrBursts::8 78895 # Per bank write bursts -system.physmem.perBankWrBursts::9 84228 # Per bank write bursts -system.physmem.perBankWrBursts::10 80757 # Per bank write bursts -system.physmem.perBankWrBursts::11 83094 # Per bank write bursts -system.physmem.perBankWrBursts::12 78112 # Per bank write bursts -system.physmem.perBankWrBursts::13 83897 # Per bank write bursts -system.physmem.perBankWrBursts::14 79365 # Per bank write bursts -system.physmem.perBankWrBursts::15 80050 # Per bank write bursts +system.physmem.perBankRdBursts::0 60738 # Per bank write bursts +system.physmem.perBankRdBursts::1 63324 # Per bank write bursts +system.physmem.perBankRdBursts::2 61558 # Per bank write bursts +system.physmem.perBankRdBursts::3 59296 # Per bank write bursts +system.physmem.perBankRdBursts::4 63003 # Per bank write bursts +system.physmem.perBankRdBursts::5 70930 # Per bank write bursts +system.physmem.perBankRdBursts::6 62473 # Per bank write bursts +system.physmem.perBankRdBursts::7 61273 # Per bank write bursts +system.physmem.perBankRdBursts::8 57204 # Per bank write bursts +system.physmem.perBankRdBursts::9 83606 # Per bank write bursts +system.physmem.perBankRdBursts::10 64602 # Per bank write bursts +system.physmem.perBankRdBursts::11 64452 # Per bank write bursts +system.physmem.perBankRdBursts::12 60809 # Per bank write bursts +system.physmem.perBankRdBursts::13 66792 # Per bank write bursts +system.physmem.perBankRdBursts::14 61061 # Per bank write bursts +system.physmem.perBankRdBursts::15 58956 # Per bank write bursts +system.physmem.perBankWrBursts::0 80045 # Per bank write bursts +system.physmem.perBankWrBursts::1 81301 # Per bank write bursts +system.physmem.perBankWrBursts::2 81272 # Per bank write bursts +system.physmem.perBankWrBursts::3 81440 # Per bank write bursts +system.physmem.perBankWrBursts::4 83523 # Per bank write bursts +system.physmem.perBankWrBursts::5 87218 # Per bank write bursts +system.physmem.perBankWrBursts::6 82653 # Per bank write bursts +system.physmem.perBankWrBursts::7 82595 # Per bank write bursts +system.physmem.perBankWrBursts::8 79330 # Per bank write bursts +system.physmem.perBankWrBursts::9 83624 # Per bank write bursts +system.physmem.perBankWrBursts::10 82850 # Per bank write bursts +system.physmem.perBankWrBursts::11 84015 # Per bank write bursts +system.physmem.perBankWrBursts::12 79570 # Per bank write bursts +system.physmem.perBankWrBursts::13 84630 # Per bank write bursts +system.physmem.perBankWrBursts::14 79832 # Per bank write bursts +system.physmem.perBankWrBursts::15 78616 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 115 # Number of times write queue was full causing retry -system.physmem.totGap 51317218019000 # Total gap between requests +system.physmem.numWrRetry 119 # Number of times write queue was full causing retry +system.physmem.totGap 51317222751500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1021235 # Read request sizes (log2) +system.physmem.readPktSize::6 1020637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1307113 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 561294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 302542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 104557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1312198 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 562832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 301764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 103549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -163,109 +163,109 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 739 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 21632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 41729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 50195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 67312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 74771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 78166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 83727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 87147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 87764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 90437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 81373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 72156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 67158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 578062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 257.760143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.645909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 296.380743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251223 43.46% 43.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 144003 24.91% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55356 9.58% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27668 4.79% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20975 3.63% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11890 2.06% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10828 1.87% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7399 1.28% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 48720 8.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 578062 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61477 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.602941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.801588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 61469 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 30315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 42487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 74945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 78298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 83924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 86856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 87663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 81232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 81562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 72278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 67228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 298 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 586236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.650755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.083309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.038467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256952 43.83% 43.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146727 25.03% 68.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55530 9.47% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27689 4.72% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21119 3.60% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11926 2.03% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10672 1.82% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7426 1.27% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 48195 8.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 586236 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.539767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.609404 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61664 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61477 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.267189 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.511196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.879627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 57149 92.96% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 2185 3.55% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1043 1.70% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 635 1.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 196 0.32% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 105 0.17% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 30 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61671 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.282515 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.526147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.873212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 57372 93.03% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 2142 3.47% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1045 1.69% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 638 1.03% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 205 0.33% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 106 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 28 0.05% 99.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-255 57 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 29 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 30 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 4 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::352-383 11 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::384-415 7 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads @@ -281,58 +281,58 @@ system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Wr system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::1504-1535 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61477 # Writes before turning the bus around for reads -system.physmem.totQLat 27580144715 # Total ticks spent queuing -system.physmem.totMemAccLat 46718438465 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5103545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27020.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61671 # Writes before turning the bus around for reads +system.physmem.totQLat 27430760765 # Total ticks spent queuing +system.physmem.totMemAccLat 46557204515 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5100385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26890.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45770.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45640.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.64 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.54 # Average write queue length when enqueuing -system.physmem.readRowHits 791160 # Number of row buffer hits during reads -system.physmem.writeRowHits 958928 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.34 # Row buffer hit rate for writes -system.physmem.avgGap 22015713.01 # Average gap between requests -system.physmem.pageHitRate 75.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2219328720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1210943250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3937471200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4270611600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1232390071935 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29709283194000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34305102423585 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.491159 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49423935419086 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.21 # Average write queue length when enqueuing +system.physmem.readRowHits 787981 # Number of row buffer hits during reads +system.physmem.writeRowHits 958372 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 21973416.70 # Average gap between requests +system.physmem.pageHitRate 74.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2249478000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1227393750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3920233200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4277104560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1233069997860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29708691447750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34305226966560 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.493484 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49422945373021 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713594740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 179688951414 # Time in different power states +system.physmem_0.memoryStateTime::ACT 180683706479 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2150820000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1173562500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4024012200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4201619040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1230344610120 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29711077467000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34304762893740 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.484542 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49426892036602 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states +system.physmem_1.actEnergy 2182466160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1190829750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4036320600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4227986160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1230809355630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29710674459000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34304912728740 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.487361 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49426230251457 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713594740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 176725372148 # Time in different power states +system.physmem_1.memoryStateTime::ACT 177398580543 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory @@ -355,30 +355,30 @@ system.realview.nvmem.bw_total::cpu0.inst 15 # T system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 133997601 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89911686 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5854244 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 89985465 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61739918 # Number of BTB hits +system.cpu0.branchPred.lookups 134105303 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90165699 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5786352 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 89882943 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61723151 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 68.610990 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17379215 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 192773 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4943112 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2622279 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 2320833 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 406549 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 68.670594 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17198111 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190210 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5005537 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2645934 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 2359603 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 409587 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,95 +408,95 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 931838 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 931838 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17645 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95375 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 582006 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 349832 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2584.187553 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14750.130751 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 347090 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1907 0.55% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 488 0.14% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 130 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 48 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 349832 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 445532 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23200.793658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 19017.924437 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16422.337995 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 338631 76.01% 76.01% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 97435 21.87% 97.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 7291 1.64% 99.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1212 0.27% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 239 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 222 0.05% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 191 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 178 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 71 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 21 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 14 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 445532 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 361726794756 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.119484 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.718354 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 360638415756 99.70% 99.70% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 594419500 0.16% 99.86% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 206814500 0.06% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 128366500 0.04% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 51460000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 27618000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 28344500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 44148500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6546000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 549000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 65000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 32000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 15500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 361726794756 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95376 84.39% 84.39% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17645 15.61% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 113021 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 931838 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 899770 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 899770 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17075 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93436 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 556454 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 343316 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2623.475166 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14944.534863 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-32767 334883 97.54% 97.54% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-65535 5615 1.64% 99.18% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-98303 1161 0.34% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-131071 826 0.24% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-163839 305 0.09% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::163840-196607 149 0.04% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-229375 96 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::229376-262143 57 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-294911 86 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::294912-327679 45 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-360447 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::360448-393215 18 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-425983 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::425984-458751 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 343316 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 426919 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23051.464095 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18844.709714 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16480.973938 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 417565 97.81% 97.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8400 1.97% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 455 0.11% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 392 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 68 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 426919 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 352898234664 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.139794 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.715758 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 351858805164 99.71% 99.71% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 566388500 0.16% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 206550000 0.06% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 120953500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 47115000 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 25743000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26226000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 38984000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6924500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 487500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 24000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 352898234664 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 93436 84.55% 84.55% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17075 15.45% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 110511 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 899770 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 931838 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113021 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 899770 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110511 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113021 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1044859 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110511 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1010281 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105631864 # DTB read hits -system.cpu0.dtb.read_misses 640489 # DTB read misses -system.cpu0.dtb.write_hits 81680668 # DTB write hits -system.cpu0.dtb.write_misses 291349 # DTB write misses +system.cpu0.dtb.read_hits 105998610 # DTB read hits +system.cpu0.dtb.read_misses 619021 # DTB read misses +system.cpu0.dtb.write_hits 82262350 # DTB write hits +system.cpu0.dtb.write_misses 280749 # DTB write misses system.cpu0.dtb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55386 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 55918 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 189 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9571 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56099 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106272353 # DTB read accesses -system.cpu0.dtb.write_accesses 81972017 # DTB write accesses +system.cpu0.dtb.perms_faults 57075 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106617631 # DTB read accesses +system.cpu0.dtb.write_accesses 82543099 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 187312532 # DTB hits -system.cpu0.dtb.misses 931838 # DTB misses -system.cpu0.dtb.accesses 188244370 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 188260960 # DTB hits +system.cpu0.dtb.misses 899770 # DTB misses +system.cpu0.dtb.accesses 189160730 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,860 +526,859 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 102509 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102509 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2958 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69563 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14385 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88124 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1419.845899 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9093.034945 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 87142 98.89% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 616 0.70% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 206 0.23% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 105 0.12% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 24 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 102467 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102467 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2998 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69670 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14196 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88271 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1375.933206 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8810.022108 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87313 98.91% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 590 0.67% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 225 0.25% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 97 0.11% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 16 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88124 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 86906 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28693.715048 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24359.274514 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18506.887432 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 84671 97.43% 97.43% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1946 2.24% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 187 0.22% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 65 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 88271 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28386.103564 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24197.471815 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17986.515042 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84889 97.73% 97.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1706 1.96% 99.69% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 161 0.19% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 62 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 31 0.04% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 86906 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 610832410424 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.899859 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.300566 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 61230050100 10.02% 10.02% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 549548390324 89.97% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 48170500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4945000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 599000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 205000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 50500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 610832410424 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69563 95.92% 95.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2958 4.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72521 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 86864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 606302699128 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.904496 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.294288 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 57963600068 9.56% 9.56% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 548286629060 90.43% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 47140500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4566000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 270000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 89500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 606302699128 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69670 95.87% 95.87% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2998 4.13% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72668 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102467 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102467 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72521 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72521 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 175030 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 94735666 # ITB inst hits -system.cpu0.itb.inst_misses 102509 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72668 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72668 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 175135 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94697092 # ITB inst hits +system.cpu0.itb.inst_misses 102467 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40835 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41669 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 193621 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 188921 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94838175 # ITB inst accesses -system.cpu0.itb.hits 94735666 # DTB hits -system.cpu0.itb.misses 102509 # DTB misses -system.cpu0.itb.accesses 94838175 # DTB accesses -system.cpu0.numPwrStateTransitions 16108 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 8054 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3370274965.000869 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 64926982226.426781 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3593 44.61% 44.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.18% 99.79% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988782302928 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 8054 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 24173024656883 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 27144194568117 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 677363519 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94799559 # ITB inst accesses +system.cpu0.itb.hits 94697092 # DTB hits +system.cpu0.itb.misses 102467 # DTB misses +system.cpu0.itb.accesses 94799559 # DTB accesses +system.cpu0.numPwrStateTransitions 15974 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 7987 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2945663211.345562 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 55329339473.705994 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3525 44.13% 44.13% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.64% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1988782294428 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 7987 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 27790211876983 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 23527012069017 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 671968082 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 248081332 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 593905796 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 133997601 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81741412 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 389608891 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13373506 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2523552 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 22024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2940 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 4870394 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 168493 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2299 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94525599 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3651769 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 39552 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 651966408 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.065387 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.317537 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 245522731 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 595240198 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 134105303 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81567196 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 387351290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13225502 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2523731 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 22012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 3023 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 4782962 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 167694 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94491838 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3604496 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 39400 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 646988319 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.075576 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.327336 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 506080688 77.62% 77.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18214646 2.79% 80.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18100947 2.78% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13291875 2.04% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28751599 4.41% 89.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8986592 1.38% 91.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9770458 1.50% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8414345 1.29% 93.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 40355258 6.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 500985180 77.43% 77.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18129867 2.80% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18167874 2.81% 83.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13357518 2.06% 85.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28640593 4.43% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8987633 1.39% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9763680 1.51% 92.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8383348 1.30% 93.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40572626 6.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 651966408 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.197822 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.876790 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 201025214 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 326077447 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105614620 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13934386 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5312657 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19632987 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1393622 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 647334053 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4303710 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5312657 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 208746840 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 23221789 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 263564774 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111697152 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 39420825 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 631864038 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 81982 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1845422 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1714455 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 19477575 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3876 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 604366839 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 973584661 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 745191594 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 824988 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 507520310 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96846524 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15772416 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13809695 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 77902092 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 101804436 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85844339 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13951597 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14791131 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 598600479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15906116 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 599443694 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 871420 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 82277994 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 51785989 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 367722 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 651966408 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.919440 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.646692 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 646988319 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.199571 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.885816 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 199030326 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 322925985 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105893213 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13875278 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5261155 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19621820 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1370848 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 649217042 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4232345 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5261155 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 206721651 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22515587 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 261202094 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111943526 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 39341608 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 633848526 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 79662 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1830943 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1627304 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 19580203 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3993 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 606139321 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 975790571 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 747374109 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 852582 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 509962376 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96176945 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15656160 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13698263 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 77451785 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102163876 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86418656 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13880040 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14667641 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 600742993 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15759066 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 601574255 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 855603 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 81711782 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 51353600 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 357908 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 646988319 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.929807 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.657116 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 416000229 63.81% 63.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 100627614 15.43% 79.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43369864 6.65% 85.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31012057 4.76% 90.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22935032 3.52% 94.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16054599 2.46% 96.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 11112799 1.70% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6483448 0.99% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4370766 0.67% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 411195381 63.56% 63.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 99990691 15.45% 79.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43358439 6.70% 85.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31042131 4.80% 90.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23015507 3.56% 94.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16185943 2.50% 96.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11141665 1.72% 98.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6569936 1.02% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4488626 0.69% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 651966408 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 646988319 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3017859 25.71% 25.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 24275 0.21% 25.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 3125 0.03% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4815194 41.03% 66.98% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3875781 33.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2994179 25.40% 25.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22123 0.19% 25.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2181 0.02% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4797008 40.69% 66.30% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3972728 33.70% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 50 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 407248355 67.94% 67.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1425936 0.24% 68.18% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 67925 0.01% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 173 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 60970 0.01% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 107889592 18.00% 86.20% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82750693 13.80% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 408493998 67.90% 67.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1413538 0.23% 68.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65279 0.01% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 146 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 55915 0.01% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108222779 17.99% 86.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83322549 13.85% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 599443694 # Type of FU issued -system.cpu0.iq.rate 0.884966 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11736234 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019579 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1862428500 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 696963642 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 577071065 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1032950 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 531195 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 457217 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 610628639 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 551239 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4761086 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 601574255 # Type of FU issued +system.cpu0.iq.rate 0.895242 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11788219 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019596 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1861718464 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 698381981 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 579322691 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1062187 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 541590 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 470908 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 612794722 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 567701 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4798771 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16972106 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 721660 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8682994 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16823750 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20061 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 720899 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8636995 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 4003221 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7891299 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 4014042 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7828481 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5312657 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14923194 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6733387 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 614655210 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1737208 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 101804436 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85844339 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13513919 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 247440 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6392978 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 721660 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2504975 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2708374 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5213349 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 592463883 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105622287 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6061529 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5261155 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14418671 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6592888 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 616647515 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1731555 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 102163876 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86418656 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13404445 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 244099 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6259110 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 720899 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2467872 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2697760 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5165632 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 594649792 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105987908 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6038347 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 148615 # number of nop insts executed -system.cpu0.iew.exec_refs 187306165 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109885900 # Number of branches executed -system.cpu0.iew.exec_stores 81683878 # Number of stores executed -system.cpu0.iew.exec_rate 0.874662 # Inst execution rate -system.cpu0.iew.wb_sent 578962486 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 577528282 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 284712169 # num instructions producing a value -system.cpu0.iew.wb_consumers 495210168 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.852612 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574932 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 82335465 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15538394 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4479878 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 637982242 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.834237 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.825466 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 145456 # number of nop insts executed +system.cpu0.iew.exec_refs 188253040 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110177692 # Number of branches executed +system.cpu0.iew.exec_stores 82265132 # Number of stores executed +system.cpu0.iew.exec_rate 0.884938 # Inst execution rate +system.cpu0.iew.wb_sent 581218511 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 579793599 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 286101590 # num instructions producing a value +system.cpu0.iew.wb_consumers 497649201 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.862829 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574906 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 81765486 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15401158 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4434486 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 633109401 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.844704 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.839642 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 441101470 69.14% 69.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 98311443 15.41% 84.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33085662 5.19% 89.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15424273 2.42% 92.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10896564 1.71% 93.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6486229 1.02% 94.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6026213 0.94% 95.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3904773 0.61% 96.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22745615 3.57% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 436470478 68.94% 68.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 97716674 15.43% 84.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 32967148 5.21% 89.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15484157 2.45% 92.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10846506 1.71% 93.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6530507 1.03% 94.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6073156 0.96% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3956859 0.62% 96.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 23063916 3.64% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 637982242 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 452758888 # Number of instructions committed -system.cpu0.commit.committedOps 532228596 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 633109401 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 455072762 # Number of instructions committed +system.cpu0.commit.committedOps 534790277 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 161993674 # Number of memory references committed -system.cpu0.commit.loads 84832329 # Number of loads committed -system.cpu0.commit.membars 3784982 # Number of memory barriers committed -system.cpu0.commit.branches 101373358 # Number of branches committed -system.cpu0.commit.fp_insts 437523 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 488401874 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13443378 # Number of function calls committed. +system.cpu0.commit.refs 163121787 # Number of memory references committed +system.cpu0.commit.loads 85340126 # Number of loads committed +system.cpu0.commit.membars 3736581 # Number of memory barriers committed +system.cpu0.commit.branches 101711661 # Number of branches committed +system.cpu0.commit.fp_insts 451530 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 490677146 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13330927 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 369014830 69.33% 69.33% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1117216 0.21% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 51029 0.01% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 51847 0.01% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84832329 15.94% 85.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77161345 14.50% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 370465668 69.27% 69.27% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1106577 0.21% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48950 0.01% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 47295 0.01% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 85340126 15.96% 85.46% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77781661 14.54% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 532228596 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22745615 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1225734406 # The number of ROB reads -system.cpu0.rob.rob_writes 1243135976 # The number of ROB writes -system.cpu0.timesIdled 4186507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25397111 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 54288384692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 452758888 # Number of Instructions Simulated -system.cpu0.committedOps 532228596 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.496080 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.496080 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.668413 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.668413 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 697890382 # number of integer regfile reads -system.cpu0.int_regfile_writes 412518994 # number of integer regfile writes -system.cpu0.fp_regfile_reads 828341 # number of floating regfile reads -system.cpu0.fp_regfile_writes 487008 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127089396 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128258211 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1206144502 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15679564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 10794532 # number of replacements +system.cpu0.commit.op_class_0::total 534790277 # Class of committed instruction +system.cpu0.commit.bw_lim_events 23063916 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1222566942 # The number of ROB reads +system.cpu0.rob.rob_writes 1247016110 # The number of ROB writes +system.cpu0.timesIdled 4124153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24979763 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 47054019698 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 455072762 # Number of Instructions Simulated +system.cpu0.committedOps 534790277 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.476617 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.476617 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.677224 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.677224 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 700310786 # number of integer regfile reads +system.cpu0.int_regfile_writes 414023994 # number of integer regfile writes +system.cpu0.fp_regfile_reads 859135 # number of floating regfile reads +system.cpu0.fp_regfile_writes 476716 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127822251 # number of cc regfile reads +system.cpu0.cc_regfile_writes 129020802 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1202374377 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15553504 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 10794591 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 308661870 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10795044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.592924 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 308312311 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10795103 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.560386 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1667914500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 302.186929 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 209.796481 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.590209 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.409759 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.025597 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.957813 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566456 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1362392595 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1362392595 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80965730 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 82351460 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 163317190 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67604275 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 69208699 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 136812974 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205804 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202560 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 408364 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173367 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153044 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 326411 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1817125 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1785316 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3602441 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2093741 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2052340 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4146081 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148743372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 151713203 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 300456575 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148949176 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 151915763 # number of overall hits -system.cpu0.dcache.overall_hits::total 300864939 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6366558 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6514512 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12881070 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6631964 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6534144 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13166108 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 653449 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 684365 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1337814 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 649747 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 591897 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1241644 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 332470 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 326805 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 659275 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 7 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1361016734 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1361016734 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 81465542 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 81638403 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 163103945 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 68252369 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 68428120 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 136680489 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200713 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 207163 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 407876 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 171912 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153997 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 325909 # 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miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766138 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.789377 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.794556 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.791837 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.154666 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154728 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154697 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 13540186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 13753617 # 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number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 13357374592 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 28306228547 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4139762000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4347889500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 8487651500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 110000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 214000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 324000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 345610396651 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 346265110444 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087306 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087944 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764616 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.768097 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766397 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.787932 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.796559 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792098 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.154088 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155407 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154747 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000002 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084045 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.082493 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.083262 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087606 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.086170 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086881 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15514.670172 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15231.443890 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15371.430440 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35075.160132 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35897.587066 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35483.318413 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23177.789450 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22155.804642 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22690.604925 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12915.742774 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12846.131485 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12881.236206 # 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number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3623821 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1019 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.866938 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.484789 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 8249196 # number of writebacks -system.cpu0.dcache.writebacks::total 8249196 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3454316 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3599973 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7054289 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5516594 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5434587 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 10951181 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3628 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3364 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 6992 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 204992 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 201546 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406538 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 8974538 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 9037924 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 18012462 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 8974538 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 9037924 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 18012462 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2912242 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2914539 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5826781 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1115370 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1099557 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2214927 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 644396 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 668916 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1313312 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 646119 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 588533 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 1234652 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 127478 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 125259 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 252737 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082850 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.083877 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.083364 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086389 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.087584 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086988 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15178.447390 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15637.250888 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15413.855495 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35505.108622 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35080.250286 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35294.095432 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23403.916746 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22152.819139 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22796.387324 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23979.955256 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24164.454701 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 50137821 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 53336 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3624490 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 999 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.833069 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 53.389389 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 8255712 # number of writebacks +system.cpu0.dcache.writebacks::total 8255712 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3390240 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3655769 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40500038516 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80908871788 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10386373000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12065937500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22452310500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14266559663 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12400788300 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26667347963 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1747255500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1706730500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3453986000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 76000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 231000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 307000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99985085935 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97939746816 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 197924832751 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 110371458935 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110005684316 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 220377143251 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3393465500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2870779500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264245000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3393465500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2870779500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264245000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032797 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033069 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015025 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014517 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014768 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749949 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754197 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752107 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.784969 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790040 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787378 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3458991000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 102000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 209000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 311000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 98865528602 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 99017407232 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 197882935834 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109010127102 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111221594232 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 220231721334 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3418077000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2846181000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264258000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3418077000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2846181000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264258000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033421 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033112 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014779 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753975 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.750041 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751962 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.783661 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.791897 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787638 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059090 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059426 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027835 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028304 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032576 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031710 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032139 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15558.354354 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15453.188309 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15505.750602 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36229.083866 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36833.050507 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36528.911241 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16117.997318 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18038.045883 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17095.945594 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22080.390242 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21070.676241 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21599.080521 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13706.329720 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13625.611732 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13666.325073 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12666.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 33000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23615.384615 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21392.991153 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21279.087847 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21336.476026 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20753.821587 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20867.826096 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20810.573099 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189929.227067 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181545.532157 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.022565 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92111.112619 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94012.951926 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.047182 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 16477862 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.835978 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 172394682 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16478374 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.461875 # Average number of references to valid blocks. +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028292 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028374 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028333 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032059 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032284 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032172 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15292.051279 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15781.275844 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15539.665883 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36627.781061 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36097.509754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36363.480884 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15778.968268 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18214.497646 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17021.874869 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22307.250693 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21065.696074 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21704.490253 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13469.191546 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13852.663875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13661.965211 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 41800 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23923.076923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21381.767256 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21282.495717 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21331.977898 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20697.825412 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20896.282918 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20797.577151 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189325.191093 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182143.926789 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.408551 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91010.384216 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95445.372233 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.240126 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 16455853 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.958473 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 172258590 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16456365 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.467597 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12245675500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 287.122432 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 224.713546 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560786 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.438894 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999680 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.034812 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.923660 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535224 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.464695 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 206602499 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 206602499 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 85625549 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 86769133 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 172394682 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 85625549 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 86769133 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 172394682 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 85625549 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 86769133 # number of overall hits -system.cpu0.icache.overall_hits::total 172394682 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8887589 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8841593 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17729182 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8887589 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8841593 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17729182 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8887589 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8841593 # number of overall misses -system.cpu0.icache.overall_misses::total 17729182 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116686112381 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116433434872 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 233119547253 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 116686112381 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 116433434872 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 233119547253 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 116686112381 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 116433434872 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 233119547253 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 94513138 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 95610726 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 190123864 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 94513138 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 95610726 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 190123864 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 94513138 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 95610726 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 190123864 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094035 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.092475 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.093251 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094035 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.092475 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.093251 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094035 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.092475 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.093251 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13129.107611 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13168.829969 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13148.917263 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13129.107611 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13168.829969 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13148.917263 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13129.107611 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13168.829969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13148.917263 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 88437 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 206421083 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 206421083 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 85737880 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 86520710 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 172258590 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 85737880 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 86520710 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 172258590 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 85737880 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 86520710 # number of overall hits +system.cpu0.icache.overall_hits::total 172258590 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8741497 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8964407 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17705904 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8741497 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8964407 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17705904 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8741497 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8964407 # number of overall misses +system.cpu0.icache.overall_misses::total 17705904 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 114800370390 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 118124161372 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 232924531762 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 114800370390 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 118124161372 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 232924531762 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 114800370390 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 118124161372 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 232924531762 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 94479377 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 95485117 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 189964494 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 94479377 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 95485117 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 189964494 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 94479377 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 95485117 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 189964494 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092523 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.093883 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.093206 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092523 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.093883 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.093206 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092523 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.093883 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.093206 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13132.804414 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13177.019001 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13155.190029 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13132.804414 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13177.019001 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13155.190029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13132.804414 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13177.019001 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13155.190029 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 86344 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 7555 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 7449 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.705758 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.591355 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 16477862 # number of writebacks -system.cpu0.icache.writebacks::total 16477862 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 628355 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 622192 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1250547 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 628355 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 622192 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1250547 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 628355 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 622192 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1250547 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8259234 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8219401 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16478635 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8259234 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 8219401 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16478635 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8259234 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 8219401 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16478635 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 16455853 # number of writebacks +system.cpu0.icache.writebacks::total 16455853 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 615386 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 633929 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1249315 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 615386 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 633929 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1249315 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 615386 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 633929 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1249315 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8126111 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8330478 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16456589 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8126111 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8330478 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16456589 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8126111 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8330478 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16456589 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12438 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8200 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 20638 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12438 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8200 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 20638 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103445364915 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103197184413 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 206642549328 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103445364915 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103197184413 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 206642549328 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103445364915 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103197184413 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 206642549328 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 101760931927 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 104688612913 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 206449544840 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 101760931927 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 104688612913 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 206449544840 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 101760931927 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 104688612913 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 206449544840 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 974276500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 641521000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1615797500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 974276500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 641521000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1615797500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086673 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.086673 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.086673 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12540.028305 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086630 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086630 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12545.099403 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 135004521 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90686520 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5841333 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91602372 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 61971036 # Number of BTB hits +system.cpu1.branchPred.lookups 134713045 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90294354 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5910949 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91937142 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 61863845 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.652218 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17264827 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 189835 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 5144550 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2721808 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 2422742 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 415682 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 67.289284 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17423003 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 191945 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 5099062 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2694305 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 2404757 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 414905 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1409,100 +1408,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 920636 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 920636 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17624 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92524 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 572462 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 348174 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2542.994307 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15098.255497 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 345444 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1949 0.56% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.12% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 137 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 118 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 24 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 58 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::720896-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 348174 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 432733 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23053.791830 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18897.650182 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16323.118118 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 333564 77.08% 77.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 89713 20.73% 97.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7384 1.71% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1176 0.27% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 238 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 198 0.05% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 173 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 170 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 52 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 27 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 432733 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 314249886000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.018496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.687233 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 313186458000 99.66% 99.66% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 582171000 0.19% 99.85% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 205657500 0.07% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 123171000 0.04% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 50673000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 26248000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 27458500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 40663500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 6954500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 344500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 34000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 16000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::56-59 2500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 314249886000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 92524 84.00% 84.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17624 16.00% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 110148 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 920636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 940458 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 940458 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17835 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93375 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 588116 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 352342 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2605.512542 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15403.554578 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 349554 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1910 0.54% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 467 0.13% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 147 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 145 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 66 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 352342 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 440653 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22932.098499 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18696.328712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16830.741238 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 430922 97.79% 97.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 8564 1.94% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 599 0.14% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 434 0.10% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 89 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 36 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 440653 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 323076797592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.107209 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.744323 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 321987662592 99.66% 99.66% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 587014500 0.18% 99.84% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 213123500 0.07% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 130553500 0.04% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 52805000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 28221000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 26598000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 43358000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6987500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 426000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 21000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 323076797592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 93376 83.96% 83.96% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17835 16.04% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 111211 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 940458 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 920636 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 940458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111211 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110148 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1030784 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1051669 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 107706385 # DTB read hits -system.cpu1.dtb.read_misses 633869 # DTB read misses -system.cpu1.dtb.write_hits 83022369 # DTB write hits -system.cpu1.dtb.write_misses 286767 # DTB write misses -system.cpu1.dtb.flush_tlb 1089 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 107105213 # DTB read hits +system.cpu1.dtb.read_misses 647862 # DTB read misses +system.cpu1.dtb.write_hits 82338491 # DTB write hits +system.cpu1.dtb.write_misses 292596 # DTB write misses +system.cpu1.dtb.flush_tlb 1087 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55362 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 54922 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 184 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9726 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 57000 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 108340254 # DTB read accesses -system.cpu1.dtb.write_accesses 83309136 # DTB write accesses +system.cpu1.dtb.perms_faults 55049 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 107753075 # DTB read accesses +system.cpu1.dtb.write_accesses 82631087 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 190728754 # DTB hits -system.cpu1.dtb.misses 920636 # DTB misses -system.cpu1.dtb.accesses 191649390 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 189443704 # DTB hits +system.cpu1.dtb.misses 940458 # DTB misses +system.cpu1.dtb.accesses 190384162 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1532,408 +1520,410 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 101988 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101988 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3087 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69367 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14377 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 87611 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1414.069010 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8744.624659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 86637 98.89% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 608 0.69% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 209 0.24% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 111 0.13% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 21 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 101953 # Table walker walks requested +system.cpu1.itb.walker.walksLong 101953 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3135 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69070 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14166 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 87787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1451.501931 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9077.444806 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 86783 98.86% 98.86% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 614 0.70% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 230 0.26% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 110 0.13% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 22 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 87611 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 86831 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28749.490389 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24437.163786 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18363.738628 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 45615 52.53% 52.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 39084 45.01% 97.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 938 1.08% 98.62% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.06% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.11% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 11 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 86831 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 606307709128 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.900370 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.299888 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 60468146000 9.97% 9.97% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 545785217128 90.02% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 47888000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 5793500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 658000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 606307709128 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 69367 95.74% 95.74% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3087 4.26% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72454 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::total 87787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86371 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28729.370969 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24395.132531 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18742.067885 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47141 54.58% 54.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 37044 42.89% 97.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 924 1.07% 98.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 961 1.11% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 89 0.10% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 13 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86371 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 610837012424 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.919047 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.273178 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 49510897620 8.11% 8.11% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 561270328804 91.89% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 50540500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 4377500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 769000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 99000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 610837012424 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 69070 95.66% 95.66% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3135 4.34% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72205 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101988 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101988 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101953 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101953 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 174442 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95828100 # ITB inst hits -system.cpu1.itb.inst_misses 101988 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72205 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72205 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174158 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 95706620 # ITB inst hits +system.cpu1.itb.inst_misses 101953 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1089 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1087 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40745 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 39902 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 188352 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 192638 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95930088 # ITB inst accesses -system.cpu1.itb.hits 95828100 # DTB hits -system.cpu1.itb.misses 101988 # DTB misses -system.cpu1.itb.accesses 95930088 # DTB accesses -system.cpu1.numPwrStateTransitions 16766 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8383 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 2803271183.603841 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 54004965145.463799 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3515 41.93% 41.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.84% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 1988782222956 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8383 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 27817396892849 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 23499822332151 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 668684774 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 95808573 # ITB inst accesses +system.cpu1.itb.hits 95706620 # DTB hits +system.cpu1.itb.misses 101953 # DTB misses +system.cpu1.itb.accesses 95808573 # DTB accesses +system.cpu1.numPwrStateTransitions 16900 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8450 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3209165135.406272 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 63386513065.949989 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3583 42.40% 42.40% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.38% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.04% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 1988782300428 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8450 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 24199778551817 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 27117445394183 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 673200080 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 248375133 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 600185967 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 135004521 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 81957671 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 381222161 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13317970 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2536848 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 21164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2785 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 4727264 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 160612 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2602 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95618947 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3633834 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39185 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 643707284 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.089618 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.340143 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 250326293 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 598056519 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 134713045 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81981153 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 383149579 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13468488 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2515216 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 21179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 3210 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 4838435 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 163101 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2842 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95493345 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3679546 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39276 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647753829 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.079477 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.330780 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 496523035 77.13% 77.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18305041 2.84% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18509005 2.88% 82.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13552167 2.11% 84.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28450532 4.42% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9097899 1.41% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9820940 1.53% 92.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8391092 1.30% 93.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 41057573 6.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 500909169 77.33% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18369194 2.84% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18392289 2.84% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13444419 2.08% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28522776 4.40% 89.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9079206 1.40% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9809102 1.51% 92.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8415106 1.30% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 40812568 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 643707284 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.201896 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.897562 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 201561818 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 315815468 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 107257676 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13770315 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5299898 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19801436 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1379430 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 654914208 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4252969 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5299898 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 209252042 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22880216 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 253975050 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 113199216 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 39098550 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 639470628 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 86957 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2174171 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1609351 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19507965 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3945 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 611072160 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 980685418 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 753664877 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 843607 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514110066 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96962094 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15327241 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13321250 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76568402 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 103346770 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 87233341 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13784187 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14730689 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 606543686 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15379714 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 607376538 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 875474 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 82437591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 51624950 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 357944 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 643707284 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.943560 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.668311 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647753829 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.200108 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.888379 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 203038997 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 318780583 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 106758002 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13823689 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5350357 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19769330 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1403755 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 652115787 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4334955 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5350357 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 210763548 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 23644830 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 256196843 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 112721527 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39074336 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 636556128 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 84527 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2214646 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1724456 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19278197 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3720 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 608321142 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 977030287 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 750414618 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 813643 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 510669806 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97651331 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15437965 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13428690 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76999253 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 102745060 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 86542127 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13847171 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14669306 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 603448531 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15520984 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 604287606 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 888730 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 83031386 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52028805 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 367516 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647753829 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.932897 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.658052 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 406849245 63.20% 63.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 99415625 15.44% 78.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43745607 6.80% 85.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31472621 4.89% 90.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23315391 3.62% 93.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16399031 2.55% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 11324350 1.76% 98.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6634295 1.03% 99.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4551119 0.71% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 411149730 63.47% 63.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99844018 15.41% 78.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43674585 6.74% 85.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31388880 4.85% 90.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23216755 3.58% 94.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16246972 2.51% 96.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11234988 1.73% 98.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6567238 1.01% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4430663 0.68% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 643707284 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647753829 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3079713 25.38% 25.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 23466 0.19% 25.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2047 0.02% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4953216 40.82% 66.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 4075474 33.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3092955 25.56% 25.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 25896 0.21% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 3078 0.03% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4978648 41.15% 66.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3998858 33.05% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 411722588 67.79% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1463458 0.24% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 65529 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 206 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 66963 0.01% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 109966089 18.11% 86.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 84091577 13.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 54 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 409873437 67.83% 67.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1473632 0.24% 68.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 67911 0.01% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 190 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 71982 0.01% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 109389956 18.10% 86.20% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 83410380 13.80% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 607376538 # Type of FU issued -system.cpu1.iq.rate 0.908315 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 12133916 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019978 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1870398622 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 704521244 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 584421121 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1071128 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 544645 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 476254 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 618939378 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 571011 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4788717 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 604287606 # Type of FU issued +system.cpu1.iq.rate 0.897634 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 12099435 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020023 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1868279780 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 702174546 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 581222842 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1037426 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 531508 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 461103 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 615834413 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 552574 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4729905 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16961682 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 19758 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 716289 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8689454 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 17106229 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20767 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 716806 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8739633 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3983377 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8390309 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3947805 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8490514 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5299898 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14473954 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 6659801 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 622069689 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1729386 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 103346770 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 87233341 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13033934 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 237234 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6338314 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 716289 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2501247 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2722291 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5223538 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 600362187 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 107695161 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6106837 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5350357 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 15089845 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6765703 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 619117650 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1756443 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 102745060 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 86542127 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13138616 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 241917 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6436383 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 716806 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2534366 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2735696 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5270062 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 597242145 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 107094882 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6118047 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 146289 # number of nop insts executed -system.cpu1.iew.exec_refs 190717674 # number of memory reference insts executed -system.cpu1.iew.exec_branches 110987821 # Number of branches executed -system.cpu1.iew.exec_stores 83022513 # Number of stores executed -system.cpu1.iew.exec_rate 0.897825 # Inst execution rate -system.cpu1.iew.wb_sent 586317808 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 584897375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 289057464 # num instructions producing a value -system.cpu1.iew.wb_consumers 502211172 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.874698 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575570 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 82490328 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15021770 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4481976 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 629716363 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.856712 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.853018 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 148135 # number of nop insts executed +system.cpu1.iew.exec_refs 189434078 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110489810 # Number of branches executed +system.cpu1.iew.exec_stores 82339196 # Number of stores executed +system.cpu1.iew.exec_rate 0.887169 # Inst execution rate +system.cpu1.iew.wb_sent 583107932 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 581683945 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 287154690 # num instructions producing a value +system.cpu1.iew.wb_consumers 498859903 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.864058 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575622 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 83090114 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15153468 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4526792 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 633652727 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.845792 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.838559 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 432763054 68.72% 68.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 96847267 15.38% 84.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33152549 5.26% 89.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15677479 2.49% 91.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11079326 1.76% 93.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6740057 1.07% 94.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6209892 0.99% 95.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3949846 0.63% 96.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 23296893 3.70% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 436801872 68.93% 68.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 97306167 15.36% 84.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33196725 5.24% 89.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15570610 2.46% 91.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11096620 1.75% 93.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6694600 1.06% 94.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6152090 0.97% 95.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3917687 0.62% 96.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22916356 3.62% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 629716363 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 459335316 # Number of instructions committed -system.cpu1.commit.committedOps 539485809 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 633652727 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 456128288 # Number of instructions committed +system.cpu1.commit.committedOps 535938124 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 164928975 # Number of memory references committed -system.cpu1.commit.loads 86385088 # Number of loads committed -system.cpu1.commit.membars 3716704 # Number of memory barriers committed -system.cpu1.commit.branches 102438773 # Number of branches committed -system.cpu1.commit.fp_insts 458507 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 495134645 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13388221 # Number of function calls committed. +system.cpu1.commit.refs 163441324 # Number of memory references committed +system.cpu1.commit.loads 85638830 # Number of loads committed +system.cpu1.commit.membars 3762780 # Number of memory barriers committed +system.cpu1.commit.branches 101898340 # Number of branches committed +system.cpu1.commit.fp_insts 443284 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 491997101 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13483818 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373316618 69.20% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1132929 0.21% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49236 0.01% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 58009 0.01% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 86385088 16.01% 85.44% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 78543887 14.56% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 371242424 69.27% 69.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1140857 0.21% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50916 0.01% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 62561 0.01% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85638830 15.98% 85.48% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77802494 14.52% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 539485809 # Class of committed instruction -system.cpu1.commit.bw_lim_events 23296893 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1224452307 # The number of ROB reads -system.cpu1.rob.rob_writes 1257969342 # The number of ROB writes -system.cpu1.timesIdled 4181395 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 24977490 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46999639814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 459335316 # Number of Instructions Simulated -system.cpu1.committedOps 539485809 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.455766 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.455766 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.686924 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.686924 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 706650375 # number of integer regfile reads -system.cpu1.int_regfile_writes 418043743 # number of integer regfile writes -system.cpu1.fp_regfile_reads 853513 # number of floating regfile reads -system.cpu1.fp_regfile_writes 519324 # number of floating regfile writes -system.cpu1.cc_regfile_reads 128705619 # number of cc regfile reads -system.cpu1.cc_regfile_writes 129852515 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1200738028 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15156718 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40297 # Transaction distribution -system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.cpu1.commit.op_class_0::total 535938124 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22916356 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1225792229 # The number of ROB reads +system.cpu1.rob.rob_writes 1252182686 # The number of ROB writes +system.cpu1.timesIdled 4237640 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 25446251 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 54234885938 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 456128288 # Number of Instructions Simulated +system.cpu1.committedOps 535938124 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.475901 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.475901 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.677552 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.677552 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 703163553 # number of integer regfile reads +system.cpu1.int_regfile_writes 415853151 # number of integer regfile writes +system.cpu1.fp_regfile_reads 819685 # number of floating regfile reads +system.cpu1.fp_regfile_writes 527216 # number of floating regfile writes +system.cpu1.cc_regfile_reads 127646217 # number of cc regfile reads +system.cpu1.cc_regfile_writes 128772606 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1202681898 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15276931 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40295 # Transaction distribution +system.iobus.trans_dist::ReadResp 40295 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1950,11 +1940,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1969,102 +1959,102 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47815500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47814500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 346000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 345500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25701500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25714000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40146500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40142500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568673363 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568747115 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.425589 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115455 # number of replacements +system.iocache.tags.tagsinuse 10.425592 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089213782000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544365 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.881224 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13089208185000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544364 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881227 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221523 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.430077 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.651599 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039641 # Number of tag accesses -system.iocache.tags.data_accesses 1039641 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039623 # Number of tag accesses +system.iocache.tags.data_accesses 1039623 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115476 # number of demand (read+write) misses -system.iocache.demand_misses::total 115516 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115474 # number of demand (read+write) misses +system.iocache.demand_misses::total 115514 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115476 # number of overall misses -system.iocache.overall_misses::total 115516 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5146000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1631213114 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1636359114 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115474 # number of overall misses +system.iocache.overall_misses::total 115514 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1644992106 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1650077606 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12815787249 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12815787249 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5497000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14447000363 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14452497363 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5497000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14447000363 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14452497363 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12805896509 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12805896509 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14450888615 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14456325115 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14450888615 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14456325115 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115476 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115516 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115474 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115514 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115476 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115516 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115474 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115514 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2078,53 +2068,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185112.700182 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184920.229856 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186718.740749 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186512.671640 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120151.009235 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120151.009235 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 137425 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125112.515695 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 137425 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125112.515695 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31781 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120058.281229 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120058.281229 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125144.089709 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125147.818576 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125144.089709 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125147.818576 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32488 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3407 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3420 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.328148 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.499415 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115476 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115516 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115474 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115514 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115476 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115516 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3296000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1190613114 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1193909114 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115474 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115514 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1204492106 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1207727606 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7475677012 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7475677012 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3497000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8666290126 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8669787126 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3497000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8666290126 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8669787126 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7465855613 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7465855613 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8670347719 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8673784219 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8670347719 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8673784219 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2138,613 +2128,613 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135112.700182 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134920.229856 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136718.740749 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136512.671640 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70086.224143 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70086.224143 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1414907 # number of replacements -system.l2c.tags.tagsinuse 65322.046709 # Cycle average of tags in use -system.l2c.tags.total_refs 51048957 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1478359 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 34.530826 # Average number of references to valid blocks. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69994.146226 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69994.146226 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75084.847836 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75088.597218 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75084.847836 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75088.597218 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1422298 # number of replacements +system.l2c.tags.tagsinuse 65353.005563 # Cycle average of tags in use +system.l2c.tags.total_refs 50978596 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1485492 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 34.317651 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 2400888500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35689.019526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.312182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 256.355195 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4109.760843 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10213.253541 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 166.614140 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 239.422394 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3052.672621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11431.636266 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.544571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002492 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003912 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062710 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.155842 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8251.641261 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 171.238322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 249.704860 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3886.905366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13383.155483 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.544051 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003986 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050463 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.125910 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002613 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.059309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.204211 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997208 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 314 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62880 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 309 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 509 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2809 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5038 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54676 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004745 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.963455 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 452888307 # Number of tag accesses -system.l2c.tags.data_accesses 452888307 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 548032 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 184031 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 541554 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 183989 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1457606 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8249196 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8249196 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 16473957 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 16473957 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5107 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10321 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits +system.l2c.tags.age_task_id_blocks_1023::4 313 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 544 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2815 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5073 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54349 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004791 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 452419027 # Number of tag accesses +system.l2c.tags.data_accesses 452419027 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 530836 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 183475 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 545490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 182908 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1442709 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8255712 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8255712 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 16452135 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 16452135 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 5154 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5091 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10245 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 811378 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 793383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1604761 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 8214123 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 8170809 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 16384932 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3524231 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3539730 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 7063961 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 360855 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 358692 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 719547 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 548032 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 184031 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 8214123 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4335609 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 541554 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 183989 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8170809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4333113 # number of demand (read+write) hits -system.l2c.demand_hits::total 26511260 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 548032 # 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18477 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 37035 # number of UpgradeReq misses +system.l2c.ReadExReq_hits::cpu0.data 802668 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 803981 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1606649 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 8081848 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 8280218 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 16362066 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3501004 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3562513 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 7063517 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 347477 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 365244 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 712721 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.266360 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.259869 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.263126 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005717 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.038076 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.047568 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042887 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.453026 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.390687 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.422761 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.090839 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.095347 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036211 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.090839 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.095347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036211 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 79614.673064 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19006.364274 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19001.533742 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19003.946341 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 74000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92131.695733 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92289.048897 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 92209.119710 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76171.553698 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80764.461337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82677.046081 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81839.627062 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20804.352231 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20903.544980 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20848.855624 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88468.255214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 88572.896818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87260.977881 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88468.255214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 88572.896818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87260.977881 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177423.826048 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176820.593774 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169041.073800 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.203929 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169639.415077 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.691796 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86046.293532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84999.307719 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87537.545848 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 81110.850412 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3192252 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1599225 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2999 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88892.873910 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.151497 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3206101 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1605959 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3062 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54318 # Transaction distribution -system.membus.trans_dist::ReadResp 482453 # Transaction distribution +system.membus.trans_dist::ReadResp 484167 # Transaction distribution system.membus.trans_dist::WriteReq 33697 # Transaction distribution system.membus.trans_dist::WriteResp 33697 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1307113 # Transaction distribution -system.membus.trans_dist::CleanEvict 222137 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37798 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1312198 # Transaction distribution +system.membus.trans_dist::CleanEvict 224447 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37872 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 575301 # Transaction distribution -system.membus.trans_dist::ReadExResp 575301 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428135 # Transaction distribution -system.membus.trans_dist::InvalidateReq 621651 # Transaction distribution +system.membus.trans_dist::ReadExReq 573072 # Transaction distribution +system.membus.trans_dist::ReadExResp 573072 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 429849 # Transaction distribution +system.membus.trans_dist::InvalidateReq 628542 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4001476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4131122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237676 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237676 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4368798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4014812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4144458 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4382045 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 141781676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 141953450 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 149206762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2813 # Total snoops (count) -system.membus.snoop_fanout::samples 1750905 # Request fanout histogram -system.membus.snoop_fanout::mean 0.020034 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.140117 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142074284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 142246058 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7247872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7247872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149493930 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2896 # Total snoops (count) +system.membus.snoopTraffic 184832 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1757355 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019576 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.138538 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1715827 98.00% 98.00% # Request fanout histogram -system.membus.snoop_fanout::1 35078 2.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1722953 98.04% 98.04% # Request fanout histogram +system.membus.snoop_fanout::1 34402 1.96% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1750905 # Request fanout histogram -system.membus.reqLayer0.occupancy 114103000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1757355 # Request fanout histogram +system.membus.reqLayer0.occupancy 114108500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5413500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5404000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8735804910 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8771663634 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5454823379 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5453450415 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44601796 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44589202 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2787,85 +2777,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 55407066 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 28133350 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 5182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1867 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 55371072 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 28119352 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4995 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 2058891 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25917963 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 2053309 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25890690 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9449679 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16477862 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2759760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 47359 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9461280 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16455852 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2755609 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 47371 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 47372 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2180704 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2180704 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16478635 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7382055 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1266688 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1234652 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49475900 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32614875 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 885296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2587313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 85563384 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2110504128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140051882 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2983576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8760712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3262300298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1987088 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30865453 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.026594 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.160894 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 47384 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2180359 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2180359 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16456589 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7382467 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1266004 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1234707 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49409857 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32615082 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 883766 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2568418 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 85477123 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2107688320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140469546 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2969568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8655976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3259783410 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2003011 # Total snoops (count) +system.toL2Bus.snoopTraffic 81599088 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 30844610 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026862 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.161680 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 30044617 97.34% 97.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 820836 2.66% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 30016066 97.31% 97.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 828544 2.69% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30865453 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 53089488175 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30844610 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 53049239176 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1406902 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1413407 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24765766555 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24732629203 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 15040405076 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 15040354777 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 512773114 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 512966184 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1495395971 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1489584962 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16437 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal index df2c0b95c..84cd483ca 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000014] Console: colour dummy device 80x25
-[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000017] pid_max: default: 32768 minimum: 301
-[ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000128] hw perfevents: no hardware support available
-[ 1.060052] CPU1: failed to come online
-[ 2.080098] CPU2: failed to come online
-[ 3.100145] CPU3: failed to come online
-[ 3.100147] Brought up 1 CPUs
-[ 3.100148] SMP: Total of 1 processors activated.
-[ 3.100192] devtmpfs: initialized
-[ 3.100479] atomic64_test: passed
-[ 3.100513] regulator-dummy: no parameters
-[ 3.100761] NET: Registered protocol family 16
-[ 3.100849] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.100857] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.101554] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.101558] Serial: AMBA PL011 UART driver
-[ 3.101697] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.101721] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102275] console [ttyAMA0] enabled
-[ 3.102339] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102364] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.102390] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.102415] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130380] 3V3: 3300 mV
-[ 3.130413] vgaarb: loaded
-[ 3.130448] SCSI subsystem initialized
-[ 3.130477] libata version 3.00 loaded.
-[ 3.130510] usbcore: registered new interface driver usbfs
-[ 3.130525] usbcore: registered new interface driver hub
-[ 3.130550] usbcore: registered new device driver usb
-[ 3.130570] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130579] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130596] PTP clock support registered
-[ 3.130681] Switched to clocksource arch_sys_counter
-[ 3.131401] NET: Registered protocol family 2
-[ 3.131455] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131470] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131488] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.131502] TCP: reno registered
-[ 3.131508] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131521] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131552] NET: Registered protocol family 1
-[ 3.131598] RPC: Registered named UNIX socket transport module.
-[ 3.131608] RPC: Registered udp transport module.
-[ 3.131616] RPC: Registered tcp transport module.
-[ 3.131624] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.131636] PCI: CLS 0 bytes, default 64
-[ 3.131740] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.131810] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.132878] fuse init (API version 7.23)
-[ 3.132936] msgmni has been set to 469
-[ 3.134487] io scheduler noop registered
-[ 3.134524] io scheduler cfq registered (default)
-[ 3.134851] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.134863] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.134874] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.134886] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.134895] pci_bus 0000:00: scanning bus
-[ 3.134905] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.134917] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.134930] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.134959] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.134971] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.134981] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.134991] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.135001] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.135011] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.135021] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.135048] pci_bus 0000:00: fixups for bus
-[ 3.135056] pci_bus 0000:00: bus scan returning with max=00
-[ 3.135067] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.135083] pci 0000:00:00.0: fixup irq: got 33
-[ 3.135091] pci 0000:00:00.0: assigning IRQ 33
-[ 3.135101] pci 0000:00:01.0: fixup irq: got 34
-[ 3.135108] pci 0000:00:01.0: assigning IRQ 34
-[ 3.135119] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.135131] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.135143] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.135156] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.135166] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.135177] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.135188] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.135199] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.135521] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.135699] ata_piix 0000:00:01.0: version 2.13
-[ 3.135708] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.135730] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.135914] scsi0 : ata_piix
-[ 3.135983] scsi1 : ata_piix
-[ 3.136005] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.136017] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.136090] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.136102] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.136115] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.136126] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290713] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290737] ata1.00: configured for UDMA/33
-[ 3.290778] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.290856] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.290876] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.290908] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.290916] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.290933] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291024] sda: sda1
-[ 3.291104] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.410957] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.410969] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.410987] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.410997] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411013] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411024] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411070] usbcore: registered new interface driver usb-storage
-[ 3.411111] mousedev: PS/2 mouse device common for all mice
-[ 3.411211] usbcore: registered new interface driver usbhid
-[ 3.411220] usbhid: USB HID core driver
-[ 3.411245] TCP: cubic registered
-[ 3.411253] NET: Registered protocol family 17
- -[ 3.411533] devtmpfs: mounted
-[ 3.411579] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000011] Console: colour dummy device 80x25
+[ 0.000013] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000013] pid_max: default: 32768 minimum: 301
+[ 0.000020] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000021] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000088] hw perfevents: no hardware support available
+[ 1.060050] CPU1: failed to come online
+[ 2.080097] CPU2: failed to come online
+[ 3.100143] CPU3: failed to come online
+[ 3.100145] Brought up 1 CPUs
+[ 3.100146] SMP: Total of 1 processors activated.
+[ 3.100181] devtmpfs: initialized
+[ 3.100440] atomic64_test: passed
+[ 3.100467] regulator-dummy: no parameters
+[ 3.100681] NET: Registered protocol family 16
+[ 3.100757] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.100763] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.100915] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.100918] Serial: AMBA PL011 UART driver
+[ 3.101033] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101053] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.101608] console [ttyAMA0] enabled
+[ 3.101661] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.101686] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.101712] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.101737] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130357] 3V3: 3300 mV
+[ 3.130385] vgaarb: loaded
+[ 3.130416] SCSI subsystem initialized
+[ 3.130445] libata version 3.00 loaded.
+[ 3.130474] usbcore: registered new interface driver usbfs
+[ 3.130488] usbcore: registered new interface driver hub
+[ 3.130512] usbcore: registered new device driver usb
+[ 3.130531] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130540] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130556] PTP clock support registered
+[ 3.130629] Switched to clocksource arch_sys_counter
+[ 3.131305] NET: Registered protocol family 2
+[ 3.131350] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131365] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131381] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131394] TCP: reno registered
+[ 3.131400] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131412] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131439] NET: Registered protocol family 1
+[ 3.131480] RPC: Registered named UNIX socket transport module.
+[ 3.131490] RPC: Registered udp transport module.
+[ 3.131498] RPC: Registered tcp transport module.
+[ 3.131506] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.131518] PCI: CLS 0 bytes, default 64
+[ 3.131611] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.131673] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.132676] fuse init (API version 7.23)
+[ 3.132730] msgmni has been set to 469
+[ 3.134207] io scheduler noop registered
+[ 3.134242] io scheduler cfq registered (default)
+[ 3.134452] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.134464] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.134475] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.134487] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.134496] pci_bus 0000:00: scanning bus
+[ 3.134505] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.134517] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.134530] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134557] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.134568] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.134578] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134588] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.134598] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.134608] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.134618] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134644] pci_bus 0000:00: fixups for bus
+[ 3.134652] pci_bus 0000:00: bus scan returning with max=00
+[ 3.134662] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.134678] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134686] pci 0000:00:00.0: assigning IRQ 33
+[ 3.134695] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134703] pci 0000:00:01.0: assigning IRQ 34
+[ 3.134713] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.134725] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.134737] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134750] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.134760] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.134771] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134782] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.134792] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.135096] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.135251] ata_piix 0000:00:01.0: version 2.13
+[ 3.135261] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.135277] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.135444] scsi0 : ata_piix
+[ 3.135507] scsi1 : ata_piix
+[ 3.135527] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.135539] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.135605] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.135616] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.135630] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.135640] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290649] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290659] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290682] ata1.00: configured for UDMA/33
+[ 3.290715] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.290789] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.290808] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.290839] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.290847] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.290864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.290949] sda: sda1
+[ 3.291024] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.410900] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.410913] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.410930] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.410939] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.410955] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.410967] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.411012] usbcore: registered new interface driver usb-storage
+[ 3.411049] mousedev: PS/2 mouse device common for all mice
+[ 3.411145] usbcore: registered new interface driver usbhid
+[ 3.411154] usbhid: USB HID core driver
+[ 3.411176] TCP: cubic registered
+[ 3.411183] NET: Registered protocol family 17
+ +[ 3.411435] devtmpfs: mounted
+[ 3.411454] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.448034] udevd[607]: starting version 182
+[ 3.447841] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.532645] random: dd urandom read with 19 bits of entropy available
+[ 3.542532] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.650911] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.660857] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini index 8093ae03e..f55dd08a3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -121,6 +135,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -139,13 +157,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -164,8 +186,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -188,9 +215,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -204,9 +236,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -217,13 +254,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -242,8 +283,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -301,9 +347,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -317,9 +368,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -334,6 +390,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -351,6 +408,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -379,9 +440,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -395,9 +461,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.isa] @@ -450,9 +521,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -466,9 +542,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -499,9 +580,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -515,13 +601,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -540,8 +630,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -552,13 +647,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -577,20 +676,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -602,11 +712,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -617,6 +732,13 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl IDD0=0.075000 @@ -651,6 +773,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -662,7 +785,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -705,10 +832,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -789,14 +921,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -805,13 +942,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -821,6 +963,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -891,10 +1034,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -974,17 +1122,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1010,12 +1163,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1023,14 +1182,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1116,14 +1280,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1132,13 +1301,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1147,13 +1321,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1161,11 +1340,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1179,11 +1363,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1197,19 +1386,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1255,14 +1450,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1271,11 +1481,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1285,21 +1500,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1309,12 +1534,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1323,10 +1553,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1336,12 +1571,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1351,26 +1591,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1379,10 +1629,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1390,10 +1645,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1401,21 +1661,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1429,11 +1699,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1444,11 +1719,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1456,10 +1736,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1475,9 +1760,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr index faa00bf6c..2fb53d936 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr @@ -3,8 +3,11 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 +warn: ClockedObject: Already in the requested power state, request ignored warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to read RealView I/O at offset 0x8 that doesn't exist @@ -1505,3 +1508,159 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout index ffdfb4a34..43fe4b5cc 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 11:31:31 -gem5 executing on e104799-lin, pid 30776 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:39:41 +gem5 executing on e108600-lin, pid 23105 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index e35d19105..3836d4f0c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821000 # Number of seconds simulated -sim_ticks 51820999867500 # Number of ticks simulated -final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.820975 # Number of seconds simulated +sim_ticks 51820974875500 # Number of ticks simulated +final_tick 51820974875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622691 # Simulator instruction rate (inst/s) -host_op_rate 731741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36089691928 # Simulator tick rate (ticks/s) -host_mem_usage 680680 # Number of bytes of host memory used -host_seconds 1435.89 # Real time elapsed on the host -sim_insts 894119248 # Number of instructions simulated -sim_ops 1050702892 # Number of ops (including micro ops) simulated +host_inst_rate 496355 # Simulator instruction rate (inst/s) +host_op_rate 583273 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28752228320 # Simulator tick rate (ticks/s) +host_mem_usage 675168 # Number of bytes of host memory used +host_seconds 1802.33 # Real time elapsed on the host +sim_insts 894595581 # Number of instructions simulated +sim_ops 1051249500 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 122816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 126336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2599472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 26029680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 150208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 131904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2604676 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 25292888 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 407488 # Number of bytes read from this memory -system.physmem.bytes_read::total 57465468 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2599472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2604676 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5204148 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78618432 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 122624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2604528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25895856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 149760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2570820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 25432280 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 409472 # Number of bytes read from this memory +system.physmem.bytes_read::total 57443708 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2604528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2570820 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5175348 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78747648 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 78639012 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 64898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 406717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56824 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 395211 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6367 # Number of read requests responded to by this memory -system.physmem.num_reads::total 938318 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1228413 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78768228 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64977 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 404626 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 397389 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6398 # Number of read requests responded to by this memory +system.physmem.num_reads::total 937978 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1230432 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1230986 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 50163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 502300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 488082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1108922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 50163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1517115 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1233005 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 50260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 499718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 490772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1108503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 50260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1519610 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1517512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1517115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 50163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 502300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 488479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2626435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 938318 # Number of read requests accepted -system.physmem.writeReqs 1230986 # Number of write requests accepted -system.physmem.readBursts 938318 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1230986 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 60016640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35712 # Total number of bytes read from write queue -system.physmem.bytesWritten 78638272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 57465468 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78639012 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 558 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1520007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1519610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 50260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 499718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 491169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2628510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 937978 # Number of read requests accepted +system.physmem.writeReqs 1233005 # Number of write requests accepted +system.physmem.readBursts 937978 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1233005 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59999232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue +system.physmem.bytesWritten 78767552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 57443708 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78768228 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57802 # Per bank write bursts -system.physmem.perBankRdBursts::1 61444 # Per bank write bursts -system.physmem.perBankRdBursts::2 58618 # Per bank write bursts -system.physmem.perBankRdBursts::3 56911 # Per bank write bursts -system.physmem.perBankRdBursts::4 53280 # Per bank write bursts -system.physmem.perBankRdBursts::5 57178 # Per bank write bursts -system.physmem.perBankRdBursts::6 52016 # Per bank write bursts -system.physmem.perBankRdBursts::7 52831 # Per bank write bursts -system.physmem.perBankRdBursts::8 55081 # Per bank write bursts -system.physmem.perBankRdBursts::9 100686 # Per bank write bursts -system.physmem.perBankRdBursts::10 57898 # Per bank write bursts -system.physmem.perBankRdBursts::11 58894 # Per bank write bursts -system.physmem.perBankRdBursts::12 52465 # Per bank write bursts -system.physmem.perBankRdBursts::13 56002 # Per bank write bursts -system.physmem.perBankRdBursts::14 52925 # Per bank write bursts -system.physmem.perBankRdBursts::15 53729 # Per bank write bursts -system.physmem.perBankWrBursts::0 76591 # Per bank write bursts -system.physmem.perBankWrBursts::1 80097 # Per bank write bursts -system.physmem.perBankWrBursts::2 79619 # Per bank write bursts -system.physmem.perBankWrBursts::3 80251 # Per bank write bursts -system.physmem.perBankWrBursts::4 74804 # Per bank write bursts -system.physmem.perBankWrBursts::5 78970 # Per bank write bursts -system.physmem.perBankWrBursts::6 72699 # Per bank write bursts -system.physmem.perBankWrBursts::7 74032 # Per bank write bursts -system.physmem.perBankWrBursts::8 75192 # Per bank write bursts -system.physmem.perBankWrBursts::9 79224 # Per bank write bursts -system.physmem.perBankWrBursts::10 76715 # Per bank write bursts -system.physmem.perBankWrBursts::11 78463 # Per bank write bursts -system.physmem.perBankWrBursts::12 72476 # Per bank write bursts -system.physmem.perBankWrBursts::13 78380 # Per bank write bursts -system.physmem.perBankWrBursts::14 75126 # Per bank write bursts -system.physmem.perBankWrBursts::15 76084 # Per bank write bursts +system.physmem.perBankRdBursts::0 55925 # Per bank write bursts +system.physmem.perBankRdBursts::1 62794 # Per bank write bursts +system.physmem.perBankRdBursts::2 56907 # Per bank write bursts +system.physmem.perBankRdBursts::3 56516 # Per bank write bursts +system.physmem.perBankRdBursts::4 54249 # Per bank write bursts +system.physmem.perBankRdBursts::5 59650 # Per bank write bursts +system.physmem.perBankRdBursts::6 52080 # Per bank write bursts +system.physmem.perBankRdBursts::7 52710 # Per bank write bursts +system.physmem.perBankRdBursts::8 54230 # Per bank write bursts +system.physmem.perBankRdBursts::9 101225 # Per bank write bursts +system.physmem.perBankRdBursts::10 56377 # Per bank write bursts +system.physmem.perBankRdBursts::11 58912 # Per bank write bursts +system.physmem.perBankRdBursts::12 52835 # Per bank write bursts +system.physmem.perBankRdBursts::13 56393 # Per bank write bursts +system.physmem.perBankRdBursts::14 52915 # Per bank write bursts +system.physmem.perBankRdBursts::15 53770 # Per bank write bursts +system.physmem.perBankWrBursts::0 75516 # Per bank write bursts +system.physmem.perBankWrBursts::1 81375 # Per bank write bursts +system.physmem.perBankWrBursts::2 78514 # Per bank write bursts +system.physmem.perBankWrBursts::3 79379 # Per bank write bursts +system.physmem.perBankWrBursts::4 75747 # Per bank write bursts +system.physmem.perBankWrBursts::5 80437 # Per bank write bursts +system.physmem.perBankWrBursts::6 73343 # Per bank write bursts +system.physmem.perBankWrBursts::7 74340 # Per bank write bursts +system.physmem.perBankWrBursts::8 74711 # Per bank write bursts +system.physmem.perBankWrBursts::9 79754 # Per bank write bursts +system.physmem.perBankWrBursts::10 76052 # Per bank write bursts +system.physmem.perBankWrBursts::11 78875 # Per bank write bursts +system.physmem.perBankWrBursts::12 73771 # Per bank write bursts +system.physmem.perBankWrBursts::13 78567 # Per bank write bursts +system.physmem.perBankWrBursts::14 74862 # Per bank write bursts +system.physmem.perBankWrBursts::15 75500 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 41 # Number of times write queue was full causing retry -system.physmem.totGap 51820996946500 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 51820971954500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 895202 # Read request sizes (log2) +system.physmem.readPktSize::6 894862 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1228413 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 903707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1230432 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 903465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -166,148 +166,149 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 33891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39270 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 66568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 69544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 72891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 70544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 68952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 71209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 74490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 70684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 68944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 563401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.102850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.051526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.279361 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 250361 44.44% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146586 26.02% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50209 8.91% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27045 4.80% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18004 3.20% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12090 2.15% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8995 1.60% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7664 1.36% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 42447 7.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 563401 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65697 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.273848 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.818256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65693 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::18 69647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 73027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 70654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 69180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 71444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 74057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 70724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 69059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 69030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 564009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.035904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.070971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.068931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 250512 44.42% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146974 26.06% 70.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49960 8.86% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27236 4.83% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18139 3.22% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12170 2.16% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8948 1.59% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7660 1.36% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42410 7.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 564009 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.242267 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.817618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65819 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65697 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.702878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.053855 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.999985 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 137 0.21% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 78 0.12% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 60 0.09% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 99 0.15% 0.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51857 78.93% 79.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9705 14.77% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 1082 1.65% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 596 0.91% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 852 1.30% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 335 0.51% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 83 0.13% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 33 0.05% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 55 0.08% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 34 0.05% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 40 0.06% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 30 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 421 0.64% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 37 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 32 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.05% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 65824 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.697481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.054439 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.954009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 139 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 76 0.12% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 52 0.08% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 125 0.19% 0.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51932 78.90% 79.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9755 14.82% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 1068 1.62% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 579 0.88% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 868 1.32% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 349 0.53% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 83 0.13% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 31 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 49 0.07% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 50 0.08% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 24 0.04% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 26 0.04% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 422 0.64% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 35 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 36 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 31 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 8 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 16 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65697 # Writes before turning the bus around for reads -system.physmem.totQLat 12237400086 # Total ticks spent queuing -system.physmem.totMemAccLat 29820400086 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4688800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13049.61 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 65824 # Writes before turning the bus around for reads +system.physmem.totQLat 12248455604 # Total ticks spent queuing +system.physmem.totMemAccLat 29826355604 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4687440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13065.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31799.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31815.19 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s @@ -317,42 +318,42 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.91 # Average write queue length when enqueuing -system.physmem.readRowHits 705929 # Number of row buffer hits during reads -system.physmem.writeRowHits 897152 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.01 # Row buffer hit rate for writes -system.physmem.avgGap 23888305.63 # Average gap between requests +system.physmem.avgWrQLen 9.53 # Average write queue length when enqueuing +system.physmem.readRowHits 705562 # Number of row buffer hits during reads +system.physmem.writeRowHits 898659 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 23869819.32 # Average gap between requests system.physmem.pageHitRate 73.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2146397400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1171149375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3510585000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3998568240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1301998363920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29950494857250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34648015573185 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.609580 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49824747021214 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730417000000 # Time in different power states +system.physmem_0.actEnergy 2151787680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1174090500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3516442800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4008858480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1301405336775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951001041250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34647951683805 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.608648 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49825590774964 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730416220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 265835434786 # Time in different power states +system.physmem_0.memoryStateTime::ACT 264967468786 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2112914160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1152879750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3803904000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3963556800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1301510416275 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29950922881500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34648162204485 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.612409 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49825423536265 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730417000000 # Time in different power states +system.physmem_1.actEnergy 2112120360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1152446625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3795924600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3966356160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1300719308715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29951602820250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34648043103030 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.610412 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49826557272121 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730416220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 265157286235 # Time in different power states +system.physmem_1.memoryStateTime::ACT 264000971629 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -369,9 +370,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -379,7 +380,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,66 +410,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 133030 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 133030 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 21129 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95696 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 133019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 133019 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 133019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 116836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25679.131432 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22619.213536 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13703.555245 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 115888 99.19% 99.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 821 0.70% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 61 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 31 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 134174 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 134174 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20899 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96911 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 134161 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 134161 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 134161 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 117823 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25678.780883 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22579.177668 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13711.855097 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 116916 99.23% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.66% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 26 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 116836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 9230012852 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.024648 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -227501296 -2.46% -2.46% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 9457514148 102.46% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 9230012852 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95697 81.91% 81.91% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 21129 18.09% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 116826 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 133030 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 117823 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 4912294556 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.048082 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -236192296 -4.81% -4.81% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 5148486852 104.81% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 4912294556 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 96912 82.26% 82.26% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 20899 17.74% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 117811 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 134174 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 133030 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116826 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 134174 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 117811 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116826 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 249856 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 117811 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 251985 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83528271 # DTB read hits -system.cpu0.dtb.read_misses 101098 # DTB read misses -system.cpu0.dtb.write_hits 76299925 # DTB write hits -system.cpu0.dtb.write_misses 31932 # DTB write misses +system.cpu0.dtb.read_hits 83610055 # DTB read hits +system.cpu0.dtb.read_misses 101997 # DTB read misses +system.cpu0.dtb.write_hits 76232981 # DTB write hits +system.cpu0.dtb.write_misses 32177 # DTB write misses system.cpu0.dtb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 73224 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 74001 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4744 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9926 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83629369 # DTB read accesses -system.cpu0.dtb.write_accesses 76331857 # DTB write accesses +system.cpu0.dtb.perms_faults 10268 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83712052 # DTB read accesses +system.cpu0.dtb.write_accesses 76265158 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 159828196 # DTB hits -system.cpu0.dtb.misses 133030 # DTB misses -system.cpu0.dtb.accesses 159961226 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 159843036 # DTB hits +system.cpu0.dtb.misses 134174 # DTB misses +system.cpu0.dtb.accesses 159977210 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -498,68 +499,74 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 78025 # Table walker walks requested -system.cpu0.itb.walker.walksLong 78025 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4409 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67964 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 78025 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 78025 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 78025 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72373 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28767.572161 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25800.961773 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 15890.832899 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 71328 98.56% 98.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 906 1.25% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 58 0.08% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 43 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72373 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 79618 # Table walker walks requested +system.cpu0.itb.walker.walksLong 79618 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4423 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69406 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 79618 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 79618 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 79618 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 73829 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28640.046594 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25708.417232 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 15347.109309 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 36310 49.18% 49.18% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 36530 49.48% 98.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 322 0.44% 99.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 541 0.73% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 50 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 12 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 20 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 14 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 73829 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -294749296 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -294749296 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -294749296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67964 93.91% 93.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4409 6.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72373 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 69406 94.01% 94.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4423 5.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 73829 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78025 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78025 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79618 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79618 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72373 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72373 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 150398 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 446488504 # ITB inst hits -system.cpu0.itb.inst_misses 78025 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73829 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73829 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 153447 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 446783848 # ITB inst hits +system.cpu0.itb.inst_misses 79618 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 53747 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 55085 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 446566529 # ITB inst accesses -system.cpu0.itb.hits 446488504 # DTB hits -system.cpu0.itb.misses 78025 # DTB misses -system.cpu0.itb.accesses 446566529 # DTB accesses -system.cpu0.numPwrStateTransitions 16564 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 8282 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 6000025981.117725 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 124621883322.639465 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3529 42.61% 42.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4688 56.60% 99.22% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 446863466 # ITB inst accesses +system.cpu0.itb.hits 446783848 # DTB hits +system.cpu0.itb.misses 79618 # DTB misses +system.cpu0.itb.accesses 446863466 # DTB accesses +system.cpu0.numPwrStateTransitions 16584 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8292 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 5987638231.190425 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 124545672847.091751 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3540 42.69% 42.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4687 56.52% 99.22% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.23% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 5 0.06% 99.29% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.54% 99.83% # Distribution of time spent in the clock gated state @@ -568,510 +575,510 @@ system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.86 system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 5700356796932 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 8282 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 2128784691883 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 49692215175617 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 51821574278 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 5700356716960 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8292 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 2171478662469 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 49649496213031 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 51821531497 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16348 # number of quiesce instructions executed -system.cpu0.committedInsts 446216062 # Number of instructions committed -system.cpu0.committedOps 524400051 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 481388306 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 440832 # Number of float alu accesses -system.cpu0.num_func_calls 26357525 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68205669 # number of instructions that are conditional controls -system.cpu0.num_int_insts 481388306 # number of integer instructions -system.cpu0.num_fp_insts 440832 # number of float instructions -system.cpu0.num_int_register_reads 703333504 # number of times the integer registers were read -system.cpu0.num_int_register_writes 381971540 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 708271 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 380080 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117540708 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117236412 # number of times the CC registers were written -system.cpu0.num_mem_refs 159819450 # number of memory refs -system.cpu0.num_load_insts 83525533 # Number of load instructions -system.cpu0.num_store_insts 76293917 # Number of store instructions -system.cpu0.num_idle_cycles 50236144373.803871 # Number of idle cycles -system.cpu0.num_busy_cycles 1585429904.196130 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030594 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969406 # Percentage of idle cycles -system.cpu0.Branches 99643757 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16350 # number of quiesce instructions executed +system.cpu0.committedInsts 446506838 # Number of instructions committed +system.cpu0.committedOps 524620955 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 481485743 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 439185 # Number of float alu accesses +system.cpu0.num_func_calls 26339620 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68267650 # number of instructions that are conditional controls +system.cpu0.num_int_insts 481485743 # number of integer instructions +system.cpu0.num_fp_insts 439185 # number of float instructions +system.cpu0.num_int_register_reads 703915697 # number of times the integer registers were read +system.cpu0.num_int_register_writes 382127275 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 705229 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 378788 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117675600 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117367653 # number of times the CC registers were written +system.cpu0.num_mem_refs 159834987 # number of memory refs +system.cpu0.num_load_insts 83607531 # Number of load instructions +system.cpu0.num_store_insts 76227456 # Number of store instructions +system.cpu0.num_idle_cycles 50234015072.883141 # Number of idle cycles +system.cpu0.num_busy_cycles 1587516424.116865 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030634 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969366 # Percentage of idle cycles +system.cpu0.Branches 99742938 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 363667031 69.31% 69.31% # Class of executed instruction -system.cpu0.op_class::IntMult 1107197 0.21% 69.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 49205 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55532 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 83525533 15.92% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 76293917 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 363863642 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 1121256 0.21% 69.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 48514 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55488 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::MemRead 83607531 15.93% 85.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 76227456 14.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 524698416 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 10234473 # number of replacements +system.cpu0.op_class::total 524923888 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 10233133 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 310064662 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10234985 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.294589 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 310246690 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10233645 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.316343 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 3504381500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 238.684462 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 273.281191 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466181 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.533752 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 237.355546 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 274.610106 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.463585 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.536348 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1291899613 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1291899613 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 78014225 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 78760782 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156775007 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72354151 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 72480719 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 144834870 # 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Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 78084246 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78779688 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156863934 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72276585 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 72648252 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 144924837 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 197426 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 197729 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395155 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 164722 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 170823 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 335545 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1869757 # 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average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30186.438601 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30359.177246 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20572.628321 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20431.069541 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20502.518476 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14686.967458 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14726.422318 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14707.004945 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 48666.666667 # average StoreCondReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028244 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94592101500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 93728262000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 188320363500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3122320000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3110634500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232954500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3122320000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3110634500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6232954500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032439 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032923 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032683 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015148 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014815 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014981 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.770234 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765295 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767784 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.789986 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781729 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785875 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057648 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060980 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059302 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83824627500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83511508500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 167336136000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94497005500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 93869843000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 188366848500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3111292000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3121623000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232915000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3111292000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3121623000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6232915000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032912 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032661 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015201 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014759 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014980 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.770427 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764355 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767428 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.790800 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781180 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.786011 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055880 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062259 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059036 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028124 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028106 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032188 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032109 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032148 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14911.206893 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14755.555373 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14832.413274 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29514.028873 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29185.366532 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29351.407979 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15932.966629 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16174.907231 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.569856 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19572.628321 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19431.069541 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19502.518476 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13333.819204 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13426.410148 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.088783 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 47666.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028109 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028075 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028092 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032226 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032032 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032129 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14891.233147 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14768.533951 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14829.122223 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29292.099692 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29445.127004 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29367.664885 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16037.209456 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16075.808226 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16056.197459 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19577.024872 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19449.279640 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19513.817411 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13369.471753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13390.566467 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13380.477640 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 56000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 82000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 56250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19313.203663 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18996.232476 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19154.150100 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18866.266393 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18632.726895 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18749.305042 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186307.058894 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183550.746445 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.215807 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97945.918815 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87529.813158 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92455.121930 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 13785272 # number of replacements +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19251.693732 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19067.777750 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19159.466454 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18825.533472 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18684.053461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18754.762173 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186573.039098 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183301.409278 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184920.043909 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 98250.292102 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87320.568408 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92454.536015 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 13781825 # number of replacements system.cpu0.icache.tags.tagsinuse 511.891071 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 880886027 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13785784 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.898145 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 881366045 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13782337 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.948955 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 31614405500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 232.219683 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 279.671389 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.453554 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.546233 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 231.253269 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 280.637803 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.451667 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.548121 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 908457605 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 908457605 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 439628868 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 441257159 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 880886027 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 439628868 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 441257159 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 880886027 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 439628868 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 441257159 # number of overall hits -system.cpu0.icache.overall_hits::total 880886027 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6859636 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6926153 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13785789 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6859636 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6926153 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13785789 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6859636 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6926153 # number of overall misses -system.cpu0.icache.overall_misses::total 13785789 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92139159000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 93034749000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 185173908000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 92139159000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 93034749000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 185173908000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 92139159000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 93034749000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 185173908000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 446488504 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 448183312 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 894671816 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 446488504 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 448183312 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 894671816 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 446488504 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 448183312 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 894671816 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015364 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015454 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015409 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015364 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015454 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015409 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015364 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015454 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015409 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13432.077008 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13432.384326 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13432.231409 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13432.077008 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13432.384326 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13432.231409 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13432.077008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13432.384326 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13432.231409 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 908930729 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 908930729 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 439927744 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 441438301 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 881366045 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 439927744 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 441438301 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 881366045 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 439927744 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 441438301 # number of overall hits +system.cpu0.icache.overall_hits::total 881366045 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6856104 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6926238 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13782342 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6856104 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6926238 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13782342 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6856104 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6926238 # number of overall misses +system.cpu0.icache.overall_misses::total 13782342 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92096826500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 93000613500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 185097440000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 92096826500 # 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number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 13785272 # number of writebacks -system.cpu0.icache.writebacks::total 13785272 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6859636 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6926153 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 13785789 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6859636 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 6926153 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 86108596000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 171388119000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 85279523000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 86108596000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 171388119000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 85279523000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 86108596000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 171388119000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 85240722500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 86074375500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 171315098000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 85240722500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 86074375500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 171315098000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 85240722500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 86074375500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 171315098000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3263480000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3263480000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015409 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015409 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015409 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12432.231409 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015397 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015397 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015397 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12430.042586 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1101,75 +1108,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 133445 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 133445 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20908 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 96452 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 133432 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.299778 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 83.395537 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 133430 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 131388 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 131388 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20694 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94767 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 12 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 131376 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.304470 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 84.045560 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 131374 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 133432 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 117373 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25894.485955 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22861.122715 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13849.356083 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 74140 63.17% 63.17% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 42199 35.95% 99.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 555 0.47% 99.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 343 0.29% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 6 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 29 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 23 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 117373 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 6007861436 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.129422 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -777548296 -12.94% -12.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 6785409732 112.94% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 6007861436 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 96452 82.18% 82.18% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 20908 17.82% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 117360 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 133445 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 131376 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 115473 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25989.651260 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22881.227305 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14446.882730 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 114392 99.06% 99.06% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 917 0.79% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 63 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 52 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 115473 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 5991401436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.130704 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -783101296 -13.07% -13.07% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 6774502732 113.07% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 5991401436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94767 82.08% 82.08% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20694 17.92% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 115461 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 131388 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 133445 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 117360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 131388 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115461 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 117360 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 250805 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115461 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 246849 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84301684 # DTB read hits -system.cpu1.dtb.read_misses 101780 # DTB read misses -system.cpu1.dtb.write_hits 76371214 # DTB write hits -system.cpu1.dtb.write_misses 31665 # DTB write misses +system.cpu1.dtb.read_hits 84308595 # DTB read hits +system.cpu1.dtb.read_misses 100203 # DTB read misses +system.cpu1.dtb.write_hits 76530288 # DTB write hits +system.cpu1.dtb.write_misses 31185 # DTB write misses system.cpu1.dtb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 73965 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 73106 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4660 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10027 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 84403464 # DTB read accesses -system.cpu1.dtb.write_accesses 76402879 # DTB write accesses +system.cpu1.dtb.perms_faults 9685 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84408798 # DTB read accesses +system.cpu1.dtb.write_accesses 76561473 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 160672898 # DTB hits -system.cpu1.dtb.misses 133445 # DTB misses -system.cpu1.dtb.accesses 160806343 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 160838883 # DTB hits +system.cpu1.dtb.misses 131388 # DTB misses +system.cpu1.dtb.accesses 160970271 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1199,150 +1201,144 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 78111 # Table walker walks requested -system.cpu1.itb.walker.walksLong 78111 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68231 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 78111 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 78111 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 78111 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 72561 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28942.620692 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25930.573552 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 16143.079615 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 35934 49.52% 49.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 35483 48.90% 98.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 386 0.53% 98.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 612 0.84% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 10 0.01% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 47 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 72561 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 76510 # Table walker walks requested +system.cpu1.itb.walker.walksLong 76510 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4384 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66713 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 76510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 76510 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 76510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71097 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29111.284583 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 26008.835767 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16533.926039 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 69890 98.30% 98.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1057 1.49% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 63 0.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71097 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -850152296 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -850152296 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -850152296 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 68231 94.03% 94.03% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4330 5.97% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72561 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 66713 93.83% 93.83% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4384 6.17% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71097 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78111 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 76510 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 76510 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72561 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72561 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 150672 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 448183312 # ITB inst hits -system.cpu1.itb.inst_misses 78111 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71097 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71097 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 147607 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 448364539 # ITB inst hits +system.cpu1.itb.inst_misses 76510 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 53921 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 52840 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448261423 # ITB inst accesses -system.cpu1.itb.hits 448183312 # DTB hits -system.cpu1.itb.misses 78111 # DTB misses -system.cpu1.itb.accesses 448261423 # DTB accesses -system.cpu1.numPwrStateTransitions 16084 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8042 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 6194937221.007833 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 118254200557.171326 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3517 43.73% 43.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4458 55.43% 99.17% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.06% 99.23% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 448441049 # ITB inst accesses +system.cpu1.itb.hits 448364539 # DTB hits +system.cpu1.itb.misses 76510 # DTB misses +system.cpu1.itb.accesses 448441049 # DTB accesses +system.cpu1.numPwrStateTransitions 16068 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8034 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 6192978089.022779 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 118311828609.490631 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3509 43.68% 43.68% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4459 55.50% 99.18% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.23% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 45 0.56% 99.79% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.81% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 13 0.16% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 3977581677820 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8042 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2001314736155 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 49819685131345 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 51820425457 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 3977581604528 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8034 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2066588908291 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 49754385967209 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 51820418254 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 447903186 # Number of instructions committed -system.cpu1.committedOps 526302841 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 483164392 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 453837 # Number of float alu accesses -system.cpu1.num_func_calls 26485275 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 68482317 # number of instructions that are conditional controls -system.cpu1.num_int_insts 483164392 # number of integer instructions -system.cpu1.num_fp_insts 453837 # number of float instructions -system.cpu1.num_int_register_reads 704985819 # number of times the integer registers were read -system.cpu1.num_int_register_writes 383399771 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 733419 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 379508 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 118000089 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 117710485 # number of times the CC registers were written -system.cpu1.num_mem_refs 160666503 # number of memory refs -system.cpu1.num_load_insts 84298667 # Number of load instructions -system.cpu1.num_store_insts 76367836 # Number of store instructions -system.cpu1.num_idle_cycles 50233099437.419525 # Number of idle cycles -system.cpu1.num_busy_cycles 1587326019.580469 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030631 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969369 # Percentage of idle cycles -system.cpu1.Branches 100046269 # Number of branches fetched +system.cpu1.committedInsts 448088743 # Number of instructions committed +system.cpu1.committedOps 526628545 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 483582453 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 455004 # Number of float alu accesses +system.cpu1.num_func_calls 26546962 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68480445 # number of instructions that are conditional controls +system.cpu1.num_int_insts 483582453 # number of integer instructions +system.cpu1.num_fp_insts 455004 # number of float instructions +system.cpu1.num_int_register_reads 705060671 # number of times the integer registers were read +system.cpu1.num_int_register_writes 383633333 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 735821 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 380160 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 117946404 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117660346 # number of times the CC registers were written +system.cpu1.num_mem_refs 160831979 # number of memory refs +system.cpu1.num_load_insts 84305574 # Number of load instructions +system.cpu1.num_store_insts 76526405 # Number of store instructions +system.cpu1.num_idle_cycles 50231588268.978668 # Number of idle cycles +system.cpu1.num_busy_cycles 1588829985.021333 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030660 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969340 # Percentage of idle cycles +system.cpu1.Branches 100054364 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364713411 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 1116791 0.21% 69.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 48530 0.01% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 54891 0.01% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::MemRead 84298667 16.01% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 76367836 14.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 364882138 69.25% 69.25% # Class of executed instruction +system.cpu1.op_class::IntMult 1103160 0.21% 69.46% # Class of executed instruction +system.cpu1.op_class::IntDiv 49288 0.01% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 54935 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::MemRead 84305574 16.00% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 76526405 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 526600168 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40318 # Transaction distribution -system.iobus.trans_dist::ReadResp 40318 # Transaction distribution +system.cpu1.op_class::total 526921542 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40309 # Transaction distribution +system.iobus.trans_dist::ReadResp 40309 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1359,11 +1355,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230994 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230994 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353778 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1378,16 +1374,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334408 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334408 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42147500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42146500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1405,75 +1401,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25749000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25738000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38609000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568885533 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568948940 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147754000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115478 # number of replacements -system.iocache.tags.tagsinuse 10.457315 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115469 # number of replacements +system.iocache.tags.tagsinuse 10.457310 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115494 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115485 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153888090000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13153887286000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.511180 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946135 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946130 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.219449 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.434133 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653582 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039830 # Number of tag accesses -system.iocache.tags.data_accesses 1039830 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039749 # Number of tag accesses +system.iocache.tags.data_accesses 1039749 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8833 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8870 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115497 # number of demand (read+write) misses -system.iocache.demand_misses::total 115537 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses +system.iocache.demand_misses::total 115528 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115497 # number of overall misses -system.iocache.overall_misses::total 115537 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1609929768 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1615016268 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115488 # number of overall misses +system.iocache.overall_misses::total 115528 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1592669163 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1597755163 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12771447265 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12771447265 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14381377033 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14386814533 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14381377033 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14386814533 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12771081777 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12771081777 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14363750940 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14369187940 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14363750940 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14369187940 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8833 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8870 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115497 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115537 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115497 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115537 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1487,53 +1483,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182263.078003 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182076.242165 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 180492.878853 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 180313.188466 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119735.311492 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119735.311492 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124521.274856 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124521.274856 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31700 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119731.884956 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119731.884956 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124374.402016 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124378.401253 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124374.402016 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124378.401253 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 30368 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3352 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.457041 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.067781 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8833 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8870 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8861 # 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mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.413518 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.090294 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.088178 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.037667 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007652 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.090294 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.088178 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.037667 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77153.623538 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18916.583027 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18919.496014 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18918.039642 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 44500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44750 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72050.491966 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71881.386450 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 71967.562553 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72781.640257 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74479.073353 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74378.277580 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74428.910610 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18671.781922 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18663.857839 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18667.893869 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72001.797054 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71983.378667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71992.661792 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72797.017293 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74403.995372 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74590.725350 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74496.407757 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18670.722173 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18670.205788 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.468860 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 72892.859506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 72892.859506 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173784.623188 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174050.071960 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171027.320470 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.538572 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170778.479154 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.017948 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91362.585482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91655.635204 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81557.769149 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.649234 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 2972233 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1487104 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81354.933005 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.287378 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2973114 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1487263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3311 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 450834 # Transaction distribution +system.membus.trans_dist::ReadResp 449832 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1228413 # Transaction distribution -system.membus.trans_dist::CleanEvict 193324 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36554 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1230432 # Transaction distribution +system.membus.trans_dist::CleanEvict 191908 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36440 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 524356 # Transaction distribution -system.membus.trans_dist::ReadExResp 524356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 374003 # Transaction distribution -system.membus.trans_dist::InvalidateReq 615538 # Transaction distribution +system.membus.trans_dist::ReadExReq 524978 # Transaction distribution +system.membus.trans_dist::ReadExResp 524978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 373001 # Transaction distribution +system.membus.trans_dist::InvalidateReq 616319 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721390 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3851094 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4088476 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3851630 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4089025 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128872672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 129042522 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7231808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7231808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 136274330 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3165 # Total snoops (count) -system.membus.snoop_fanout::samples 1660996 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019349 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137749 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128978144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129147994 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7233792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 136381786 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3125 # Total snoops (count) +system.membus.snoopTraffic 199488 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1661282 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019128 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.136975 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1628857 98.07% 98.07% # Request fanout histogram -system.membus.snoop_fanout::1 32139 1.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1629505 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::1 31777 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1660996 # Request fanout histogram -system.membus.reqLayer0.occupancy 106934500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1661282 # Request fanout histogram +system.membus.reqLayer0.occupancy 106916500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5678000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5690500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8069625955 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8079257005 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4926078787 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4924178426 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44722660 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44658046 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2173,85 +2170,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 48668708 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 24647917 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2076 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 48659442 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 24643437 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1748 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2028 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1292402 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21924695 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1290012 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21916025 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9016681 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13785272 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2525177 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45989 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45993 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2157137 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2157137 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13785789 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6848293 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1261037 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1232293 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41443100 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30932231 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796412 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1256395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 74428138 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764720404 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081696966 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2696152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 4001736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2853115258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1718109 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 26731746 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021922 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146427 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 9018905 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13781825 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2522217 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45883 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45886 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2158380 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2158380 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13782342 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6845459 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1260926 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1232503 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41432759 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30927957 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1252515 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 74409715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764279188 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081608326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2697464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3989080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2852574058 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1717339 # Total snoops (count) +system.toL2Bus.snoopTraffic 74998872 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 26724704 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021941 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146492 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 26145745 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 586001 2.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 26138332 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 586372 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 26731746 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 46403347500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 26724704 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 46394070000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1695386 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1633889 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20721808500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20716638000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14193795462 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14191518968 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 459393000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 459301000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 756178000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 753880000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal index b028e910d..d74b75b2a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000045] Console: colour dummy device 80x25
-[ 0.000049] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000051] pid_max: default: 32768 minimum: 301
-[ 0.000075] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000077] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000352] hw perfevents: no hardware support available
-[ 1.060142] CPU1: failed to come online
-[ 2.080279] CPU2: failed to come online
-[ 3.100417] CPU3: failed to come online
-[ 3.100422] Brought up 1 CPUs
-[ 3.100424] SMP: Total of 1 processors activated.
-[ 3.100540] devtmpfs: initialized
-[ 3.101655] atomic64_test: passed
-[ 3.101743] regulator-dummy: no parameters
-[ 3.102586] NET: Registered protocol family 16
-[ 3.102876] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.102889] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.105209] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.105217] Serial: AMBA PL011 UART driver
-[ 3.105613] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.105686] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.106271] console [ttyAMA0] enabled
-[ 3.106418] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.106468] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.106518] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.106564] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130865] 3V3: 3300 mV
-[ 3.130952] vgaarb: loaded
-[ 3.131049] SCSI subsystem initialized
-[ 3.131123] libata version 3.00 loaded.
-[ 3.131214] usbcore: registered new interface driver usbfs
-[ 3.131242] usbcore: registered new interface driver hub
-[ 3.131299] usbcore: registered new device driver usb
-[ 3.131346] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131356] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131380] PTP clock support registered
-[ 3.131622] Switched to clocksource arch_sys_counter
-[ 3.133833] NET: Registered protocol family 2
-[ 3.133999] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.134032] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.134072] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.134126] TCP: reno registered
-[ 3.134134] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134154] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134230] NET: Registered protocol family 1
-[ 3.134310] RPC: Registered named UNIX socket transport module.
-[ 3.134320] RPC: Registered udp transport module.
-[ 3.134329] RPC: Registered tcp transport module.
-[ 3.134338] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.134352] PCI: CLS 0 bytes, default 64
-[ 3.134697] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.134933] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.138705] fuse init (API version 7.23)
-[ 3.138877] msgmni has been set to 469
-[ 3.143640] io scheduler noop registered
-[ 3.143737] io scheduler cfq registered (default)
-[ 3.144797] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.144812] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.144825] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.144839] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.144850] pci_bus 0000:00: scanning bus
-[ 3.144865] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.144880] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.144898] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144963] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.144977] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.144989] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.145002] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.145014] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.145027] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.145041] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.145103] pci_bus 0000:00: fixups for bus
-[ 3.145112] pci_bus 0000:00: bus scan returning with max=00
-[ 3.145127] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.145154] pci 0000:00:00.0: fixup irq: got 33
-[ 3.145164] pci 0000:00:00.0: assigning IRQ 33
-[ 3.145178] pci 0000:00:01.0: fixup irq: got 34
-[ 3.145188] pci 0000:00:01.0: assigning IRQ 34
-[ 3.145202] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.145217] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.145232] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.145246] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.145260] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.145273] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.145286] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.145300] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.146216] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.146745] ata_piix 0000:00:01.0: version 2.13
-[ 3.146757] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.146801] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.147406] scsi0 : ata_piix
-[ 3.147592] scsi1 : ata_piix
-[ 3.147648] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.147661] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.147864] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.147877] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.147899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.147912] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301659] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301670] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301706] ata1.00: configured for UDMA/33
-[ 3.301793] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301991] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.302026] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.302084] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.302095] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.302124] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.302327] sda: sda1
-[ 3.302534] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421985] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.422000] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.422029] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.422040] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.422072] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.422084] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.422216] usbcore: registered new interface driver usb-storage
-[ 3.422310] mousedev: PS/2 mouse device common for all mice
-[ 3.422604] usbcore: registered new interface driver usbhid
-[ 3.422615] usbhid: USB HID core driver
-[ 3.422670] TCP: cubic registered
-[ 3.422680] NET: Registered protocol family 17
- -[ 3.423358] devtmpfs: mounted
-[ 3.423483] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000039] Console: colour dummy device 80x25
+[ 0.000042] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000044] pid_max: default: 32768 minimum: 301
+[ 0.000065] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000067] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000247] hw perfevents: no hardware support available
+[ 1.060141] CPU1: failed to come online
+[ 2.080278] CPU2: failed to come online
+[ 3.100415] CPU3: failed to come online
+[ 3.100420] Brought up 1 CPUs
+[ 3.100422] SMP: Total of 1 processors activated.
+[ 3.100519] devtmpfs: initialized
+[ 3.101579] atomic64_test: passed
+[ 3.101653] regulator-dummy: no parameters
+[ 3.102392] NET: Registered protocol family 16
+[ 3.102653] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102663] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.103271] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.103277] Serial: AMBA PL011 UART driver
+[ 3.103628] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.103692] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.104278] console [ttyAMA0] enabled
+[ 3.104379] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.104429] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.104479] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.104525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.131020] 3V3: 3300 mV
+[ 3.131093] vgaarb: loaded
+[ 3.131183] SCSI subsystem initialized
+[ 3.131252] libata version 3.00 loaded.
+[ 3.131332] usbcore: registered new interface driver usbfs
+[ 3.131358] usbcore: registered new interface driver hub
+[ 3.131413] usbcore: registered new device driver usb
+[ 3.131456] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131466] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131488] PTP clock support registered
+[ 3.131706] Switched to clocksource arch_sys_counter
+[ 3.133706] NET: Registered protocol family 2
+[ 3.133856] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.133884] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.133918] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.133940] TCP: reno registered
+[ 3.133948] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.133966] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134029] NET: Registered protocol family 1
+[ 3.134094] RPC: Registered named UNIX socket transport module.
+[ 3.134105] RPC: Registered udp transport module.
+[ 3.134113] RPC: Registered tcp transport module.
+[ 3.134122] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134136] PCI: CLS 0 bytes, default 64
+[ 3.134445] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134644] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138048] fuse init (API version 7.23)
+[ 3.138207] msgmni has been set to 469
+[ 3.142619] io scheduler noop registered
+[ 3.142717] io scheduler cfq registered (default)
+[ 3.143500] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.143514] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.143527] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.143541] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.143553] pci_bus 0000:00: scanning bus
+[ 3.143566] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.143581] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.143598] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143658] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.143672] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.143684] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.143697] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.143710] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.143722] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.143736] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143793] pci_bus 0000:00: fixups for bus
+[ 3.143803] pci_bus 0000:00: bus scan returning with max=00
+[ 3.143817] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.143842] pci 0000:00:00.0: fixup irq: got 33
+[ 3.143852] pci 0000:00:00.0: assigning IRQ 33
+[ 3.143866] pci 0000:00:01.0: fixup irq: got 34
+[ 3.143875] pci 0000:00:01.0: assigning IRQ 34
+[ 3.143889] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.143904] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.143919] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.143933] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.143946] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.143960] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.143973] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.143986] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.144848] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.145335] ata_piix 0000:00:01.0: version 2.13
+[ 3.145347] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.145377] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.145943] scsi0 : ata_piix
+[ 3.146120] scsi1 : ata_piix
+[ 3.146172] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.146185] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.146369] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.146383] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.146404] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.146418] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301739] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301750] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301784] ata1.00: configured for UDMA/33
+[ 3.301855] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302047] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302082] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302139] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302150] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302179] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302375] sda: sda1
+[ 3.302573] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422074] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422145] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422158] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422288] usbcore: registered new interface driver usb-storage
+[ 3.422377] mousedev: PS/2 mouse device common for all mice
+[ 3.422663] usbcore: registered new interface driver usbhid
+[ 3.422673] usbhid: USB HID core driver
+[ 3.422723] TCP: cubic registered
+[ 3.422732] NET: Registered protocol family 17
+ +[ 3.423356] devtmpfs: mounted
+[ 3.423405] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.470485] udevd[607]: starting version 182
+[ 3.470207] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.586582] random: dd urandom read with 21 bits of entropy available
+[ 3.606569] random: dd urandom read with 21 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -168,8 +168,8 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
-Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.781859] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Configuring network interfaces... [ 3.791940] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+udhcpc (v1.21.1) started
Sending discover...
Sending discover...
Sending discover...
|