diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
20 files changed, 7065 insertions, 6998 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index add5f9d75..be87396c4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,19 +30,19 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -228,6 +229,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=false system=system tracer=system.cpu.checker.tracer @@ -980,9 +982,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -993,27 +995,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 43698041c..ec581702f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,20 +10,21 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6176053500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6184767500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6220839500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6236327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6779610500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 6127336500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6135886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6171724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6187045500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6729690500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 51874115000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: 2476169247000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2490093200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2491309014500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2512521404000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2513043156000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2517323856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10 -warn: 2518814467000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2519896624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2519897721500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2520452967000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 51815926000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 2464496392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2490035144500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2491240940500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2491596722500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2505538162500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2507237495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2512436106000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2512950831500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2518637805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2519704735000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2519705958000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index a26501a59..964505e0a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:47:40 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.checker.isa: ISA system set to: 0x645a800 0x645a800 - 0: system.cpu.isa: ISA system set to: 0x645a800 0x645a800 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.checker.isa: ISA system set to: 0x639d990 0x639d990 + 0: system.cpu.isa: ISA system set to: 0x639d990 0x639d990 info: Using bootloader at address 0x80000000 info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2526146947500 because m5_exit instruction encountered +Exiting @ tick 2525888859000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 7fa449dce..76ba3533e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,137 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526192 # Number of seconds simulated -sim_ticks 2526192217500 # Number of ticks simulated -final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525889 # Number of seconds simulated +sim_ticks 2525888859000 # Number of ticks simulated +final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45758 # Simulator instruction rate (inst/s) -host_op_rate 58877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1916680323 # Simulator tick rate (ticks/s) -host_mem_usage 469072 # Number of bytes of host memory used -host_seconds 1318.00 # Real time elapsed on the host -sim_insts 60309034 # Number of instructions simulated -sim_ops 77600502 # Number of ops (including micro ops) simulated +host_inst_rate 55568 # Simulator instruction rate (inst/s) +host_op_rate 71500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2327295647 # Simulator tick rate (ticks/s) +host_mem_usage 420424 # Number of bytes of host memory used +host_seconds 1085.33 # Real time elapsed on the host +sim_insts 60309513 # Number of instructions simulated +sim_ops 77601128 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096864 # Number of read requests accepted -system.physmem.writeReqs 813148 # Number of write requests accepted -system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue -system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943480 # Per bank write bursts -system.physmem.perBankRdBursts::1 937980 # Per bank write bursts -system.physmem.perBankRdBursts::2 937559 # Per bank write bursts -system.physmem.perBankRdBursts::3 937528 # Per bank write bursts -system.physmem.perBankRdBursts::4 943087 # Per bank write bursts -system.physmem.perBankRdBursts::5 937982 # Per bank write bursts -system.physmem.perBankRdBursts::6 937070 # Per bank write bursts -system.physmem.perBankRdBursts::7 936990 # Per bank write bursts -system.physmem.perBankRdBursts::8 943982 # Per bank write bursts -system.physmem.perBankRdBursts::9 938303 # Per bank write bursts -system.physmem.perBankRdBursts::10 937119 # Per bank write bursts -system.physmem.perBankRdBursts::11 936407 # Per bank write bursts -system.physmem.perBankRdBursts::12 943924 # Per bank write bursts -system.physmem.perBankRdBursts::13 938214 # Per bank write bursts -system.physmem.perBankRdBursts::14 937241 # Per bank write bursts -system.physmem.perBankRdBursts::15 937211 # Per bank write bursts -system.physmem.perBankWrBursts::0 6601 # Per bank write bursts -system.physmem.perBankWrBursts::1 6388 # Per bank write bursts -system.physmem.perBankWrBursts::2 6528 # Per bank write bursts -system.physmem.perBankWrBursts::3 6554 # Per bank write bursts -system.physmem.perBankWrBursts::4 6464 # Per bank write bursts -system.physmem.perBankWrBursts::5 6726 # Per bank write bursts -system.physmem.perBankWrBursts::6 6713 # Per bank write bursts -system.physmem.perBankWrBursts::7 6652 # Per bank write bursts -system.physmem.perBankWrBursts::8 7031 # Per bank write bursts -system.physmem.perBankWrBursts::9 6803 # Per bank write bursts -system.physmem.perBankWrBursts::10 6461 # Per bank write bursts -system.physmem.perBankWrBursts::11 6104 # Per bank write bursts -system.physmem.perBankWrBursts::12 7064 # Per bank write bursts -system.physmem.perBankWrBursts::13 6684 # Per bank write bursts -system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6836 # Per bank write bursts +system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096846 # Number of read requests accepted +system.physmem.writeReqs 813159 # Number of write requests accepted +system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue +system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943526 # Per bank write bursts +system.physmem.perBankRdBursts::1 937990 # Per bank write bursts +system.physmem.perBankRdBursts::2 937469 # Per bank write bursts +system.physmem.perBankRdBursts::3 937431 # Per bank write bursts +system.physmem.perBankRdBursts::4 943079 # Per bank write bursts +system.physmem.perBankRdBursts::5 938170 # Per bank write bursts +system.physmem.perBankRdBursts::6 937203 # Per bank write bursts +system.physmem.perBankRdBursts::7 936910 # Per bank write bursts +system.physmem.perBankRdBursts::8 943866 # Per bank write bursts +system.physmem.perBankRdBursts::9 938107 # Per bank write bursts +system.physmem.perBankRdBursts::10 936563 # Per bank write bursts +system.physmem.perBankRdBursts::11 936045 # Per bank write bursts +system.physmem.perBankRdBursts::12 943886 # Per bank write bursts +system.physmem.perBankRdBursts::13 937531 # Per bank write bursts +system.physmem.perBankRdBursts::14 937186 # Per bank write bursts +system.physmem.perBankRdBursts::15 937024 # Per bank write bursts +system.physmem.perBankWrBursts::0 6617 # Per bank write bursts +system.physmem.perBankWrBursts::1 6376 # Per bank write bursts +system.physmem.perBankWrBursts::2 6529 # Per bank write bursts +system.physmem.perBankWrBursts::3 6558 # Per bank write bursts +system.physmem.perBankWrBursts::4 6459 # Per bank write bursts +system.physmem.perBankWrBursts::5 6705 # Per bank write bursts +system.physmem.perBankWrBursts::6 6711 # Per bank write bursts +system.physmem.perBankWrBursts::7 6649 # Per bank write bursts +system.physmem.perBankWrBursts::8 7036 # Per bank write bursts +system.physmem.perBankWrBursts::9 6794 # Per bank write bursts +system.physmem.perBankWrBursts::10 6454 # Per bank write bursts +system.physmem.perBankWrBursts::11 6111 # Per bank write bursts +system.physmem.perBankWrBursts::12 7073 # Per bank write bursts +system.physmem.perBankWrBursts::13 6679 # Per bank write bursts +system.physmem.perBankWrBursts::14 6963 # Per bank write bursts +system.physmem.perBankWrBursts::15 6824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526191083500 # Total gap between requests +system.physmem.totGap 2525887732500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154618 # Read request sizes (log2) +system.physmem.readPktSize::6 154600 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59130 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +171,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,50 +220,49 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads -system.physmem.totQLat 389908010000 # Total ticks spent queuing -system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads +system.physmem.totQLat 389024977250 # Total ticks spent queuing +system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -259,75 +270,63 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing -system.physmem.readRowHits 14044000 # Number of row buffer hits during reads -system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing +system.physmem.readRowHits 14042089 # Number of row buffer hits during reads +system.physmem.writeRowHits 91063 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.avgGap 158760.96 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states -system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states +system.physmem.memoryStateTime::REF 84344780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54877773 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149486 # Transaction distribution -system.membus.trans_dist::ReadResp 16149486 # Transaction distribution +system.membus.throughput 54884184 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149487 # Transaction distribution +system.membus.trans_dist::ReadResp 16149487 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59130 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution +system.membus.trans_dist::Writeback 59141 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution -system.membus.trans_dist::ReadExReq 131451 # Transaction distribution -system.membus.trans_dist::ReadExResp 131451 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution +system.membus.trans_dist::ReadExReq 131431 # Transaction distribution +system.membus.trans_dist::ReadExResp 131431 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631802 # Total data (bytes) +system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631350 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -335,13 +334,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48265574 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution +system.iobus.throughput 48271369 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution system.iobus.trans_dist::WriteResp 8174 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -363,12 +362,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -390,14 +389,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928118 # Total data (bytes) +system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121928114 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -443,20 +442,20 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14753661 # Number of BP lookups -system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits +system.cpu.branchPred.lookups 14910337 # Number of BP lookups +system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -480,9 +479,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987453 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11227597 # DTB write hits +system.cpu.checker.dtb.read_hits 14987595 # DTB read hits +system.cpu.checker.dtb.read_misses 7306 # DTB read misses +system.cpu.checker.dtb.write_hits 11227720 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -493,12 +492,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994761 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229788 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994901 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229911 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215050 # DTB hits -system.cpu.checker.dtb.misses 9499 # DTB misses -system.cpu.checker.dtb.accesses 26224549 # DTB accesses +system.cpu.checker.dtb.hits 26215315 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26224812 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -520,7 +519,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61483008 # ITB inst hits +system.cpu.checker.itb.inst_hits 61483491 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -537,11 +536,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61487481 # ITB inst accesses -system.cpu.checker.itb.hits 61483008 # DTB hits +system.cpu.checker.itb.inst_accesses 61487964 # ITB inst accesses +system.cpu.checker.itb.hits 61483491 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61487481 # DTB accesses -system.cpu.checker.numCycles 77886295 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61487964 # DTB accesses +system.cpu.checker.numCycles 77886925 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -567,25 +566,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51183231 # DTB read hits -system.cpu.dtb.read_misses 65223 # DTB read misses -system.cpu.dtb.write_hits 11700953 # DTB write hits -system.cpu.dtb.write_misses 15725 # DTB write misses +system.cpu.dtb.read_hits 51097792 # DTB read hits +system.cpu.dtb.read_misses 64987 # DTB read misses +system.cpu.dtb.write_hits 11709971 # DTB write hits +system.cpu.dtb.write_misses 15921 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51248454 # DTB read accesses -system.cpu.dtb.write_accesses 11716678 # DTB write accesses +system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51162779 # DTB read accesses +system.cpu.dtb.write_accesses 11725892 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62884184 # DTB hits -system.cpu.dtb.misses 80948 # DTB misses -system.cpu.dtb.accesses 62965132 # DTB accesses +system.cpu.dtb.hits 62807763 # DTB hits +system.cpu.dtb.misses 80908 # DTB misses +system.cpu.dtb.accesses 62888671 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -607,8 +606,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11525561 # ITB inst hits -system.cpu.itb.inst_misses 11159 # ITB inst misses +system.cpu.itb.inst_hits 11575507 # ITB inst hits +system.cpu.itb.inst_misses 11335 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -617,265 +616,266 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11536720 # ITB inst accesses -system.cpu.itb.hits 11525561 # DTB hits -system.cpu.itb.misses 11159 # DTB misses -system.cpu.itb.accesses 11536720 # DTB accesses -system.cpu.numCycles 477128882 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11586842 # ITB inst accesses +system.cpu.itb.hits 11575507 # DTB hits +system.cpu.itb.misses 11335 # DTB misses +system.cpu.itb.accesses 11586842 # DTB accesses +system.cpu.numCycles 476238509 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued -system.cpu.iq.rate 0.257622 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued +system.cpu.iq.rate 0.258180 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222849 # number of nop insts executed -system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed -system.cpu.iew.exec_branches 11822089 # Number of branches executed -system.cpu.iew.exec_stores 12212847 # Number of stores executed -system.cpu.iew.exec_rate 0.253272 # Inst execution rate -system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47017508 # num instructions producing a value -system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value +system.cpu.iew.exec_nop 226309 # number of nop insts executed +system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed +system.cpu.iew.exec_branches 11843747 # Number of branches executed +system.cpu.iew.exec_stores 12222179 # Number of stores executed +system.cpu.iew.exec_rate 0.253798 # Inst execution rate +system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47892202 # num instructions producing a value +system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459415 # Number of instructions committed -system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459894 # Number of instructions committed +system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386618 # Number of memory references committed -system.cpu.commit.loads 15654647 # Number of loads committed -system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 10306311 # Number of branches committed +system.cpu.commit.refs 27386881 # Number of memory references committed +system.cpu.commit.loads 15654781 # Number of loads committed +system.cpu.commit.membars 403574 # Number of memory barriers committed +system.cpu.commit.branches 10306383 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. -system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. +system.cpu.commit.function_calls 991261 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction @@ -904,319 +904,319 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction -system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction +system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243007370 # The number of ROB reads -system.cpu.rob.rob_writes 195993770 # The number of ROB writes -system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309034 # Number of Instructions Simulated -system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548643018 # number of integer regfile reads -system.cpu.int_regfile_writes 87545925 # number of integer regfile writes -system.cpu.fp_regfile_reads 8332 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution +system.cpu.rob.rob_reads 239318561 # The number of ROB reads +system.cpu.rob.rob_writes 197472000 # The number of ROB writes +system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309513 # Number of Instructions Simulated +system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548833946 # number of integer regfile reads +system.cpu.int_regfile_writes 87707846 # number of integer regfile writes +system.cpu.fp_regfile_reads 8328 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected 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mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits 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0.084813 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64387 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64369 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 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rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1337,168 +1337,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643320 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643771 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993313 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21491250 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 644283 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits -system.cpu.dcache.overall_hits::total 21015072 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses -system.cpu.dcache.overall_misses::total 3699212 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 20997707 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20997707 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20997707 # number of overall hits +system.cpu.dcache.overall_hits::total 20997707 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 762201 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 762201 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2968429 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2968429 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13530 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13530 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3730630 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3730630 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3730630 # number of overall misses +system.cpu.dcache.overall_misses::total 3730630 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10170757825 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10170757825 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 136412874713 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184826749 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184826749 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 180503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 180503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 146583632538 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 146583632538 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 146583632538 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 146583632538 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14506016 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14506016 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222321 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247609 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247609 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24728337 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24728337 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24728337 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24728337 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052544 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052544 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290387 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.290387 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052780 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052780 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150865 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150865 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150865 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks -system.cpu.dcache.writebacks::total 607456 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks +system.cpu.dcache.writebacks::total 607940 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1522,16 +1522,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 518b7284a..50ac2503c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -775,6 +776,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -1423,9 +1425,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1436,27 +1438,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index a00c0b470..52743013f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:56:34 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu0.isa: ISA system set to: 0x6856800 0x6856800 - 0: system.cpu1.isa: ISA system set to: 0x6856800 0x6856800 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x628e100 0x628e100 + 0: system.cpu1.isa: ISA system set to: 0x628e100 0x628e100 info: Using bootloader at address 0x80000000 info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2605645191500 because m5_exit instruction encountered +Exiting @ tick 2605245500000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3626d40ac..fcbba5f01 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605644 # Number of seconds simulated -sim_ticks 2605643988500 # Number of ticks simulated -final_tick 2605643988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605246 # Number of seconds simulated +sim_ticks 2605245500000 # Number of ticks simulated +final_tick 2605245500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56388 # Simulator instruction rate (inst/s) -host_op_rate 72604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2339801960 # Simulator tick rate (ticks/s) -host_mem_usage 475216 # Number of bytes of host memory used -host_seconds 1113.62 # Real time elapsed on the host -sim_insts 62794806 # Number of instructions simulated -sim_ops 80853196 # Number of ops (including micro ops) simulated +host_inst_rate 66179 # Simulator instruction rate (inst/s) +host_op_rate 85203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2745863070 # Simulator tick rate (ticks/s) +host_mem_usage 426204 # Number of bytes of host memory used +host_seconds 948.79 # Real time elapsed on the host +sim_insts 62790043 # Number of instructions simulated +sim_ops 80839298 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4377212 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 429184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5246712 # Number of bytes read from this memory -system.physmem.bytes_read::total 131559796 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 429184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4275584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4351548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 427968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5241528 # Number of bytes read from this memory +system.physmem.bytes_read::total 131526900 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 427968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4250944 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7304720 # Number of bytes written to this memory +system.physmem.bytes_written::total 7280080 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6160 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82008 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302188 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66806 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6687 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81927 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301674 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66421 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824090 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46480075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1679896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2013595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50490319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151302 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1640893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2803422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1640893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46480075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1686421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3169600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53293741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302188 # Number of read requests accepted -system.physmem.writeReqs 824090 # Number of write requests accepted -system.physmem.readBursts 15302188 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 824090 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 974626176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4713856 # Total number of bytes read from write queue -system.physmem.bytesWritten 7328128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131559796 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7304720 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 73654 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709569 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14159 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956238 # Per bank write bursts -system.physmem.perBankRdBursts::1 951013 # Per bank write bursts -system.physmem.perBankRdBursts::2 950196 # Per bank write bursts -system.physmem.perBankRdBursts::3 950464 # Per bank write bursts -system.physmem.perBankRdBursts::4 956634 # Per bank write bursts -system.physmem.perBankRdBursts::5 950822 # Per bank write bursts -system.physmem.perBankRdBursts::6 949869 # Per bank write bursts -system.physmem.perBankRdBursts::7 949811 # Per bank write bursts -system.physmem.perBankRdBursts::8 956681 # Per bank write bursts -system.physmem.perBankRdBursts::9 951277 # Per bank write bursts -system.physmem.perBankRdBursts::10 949961 # Per bank write bursts -system.physmem.perBankRdBursts::11 949024 # Per bank write bursts -system.physmem.perBankRdBursts::12 956331 # Per bank write bursts -system.physmem.perBankRdBursts::13 950586 # Per bank write bursts -system.physmem.perBankRdBursts::14 950041 # Per bank write bursts -system.physmem.perBankRdBursts::15 949586 # Per bank write bursts -system.physmem.perBankWrBursts::0 7062 # Per bank write bursts -system.physmem.perBankWrBursts::1 6963 # Per bank write bursts -system.physmem.perBankWrBursts::2 7126 # Per bank write bursts -system.physmem.perBankWrBursts::3 7116 # Per bank write bursts -system.physmem.perBankWrBursts::4 7811 # Per bank write bursts -system.physmem.perBankWrBursts::5 7409 # Per bank write bursts -system.physmem.perBankWrBursts::6 7013 # Per bank write bursts -system.physmem.perBankWrBursts::7 7004 # Per bank write bursts -system.physmem.perBankWrBursts::8 7458 # Per bank write bursts -system.physmem.perBankWrBursts::9 7561 # Per bank write bursts -system.physmem.perBankWrBursts::10 6914 # Per bank write bursts -system.physmem.perBankWrBursts::11 6583 # Per bank write bursts -system.physmem.perBankWrBursts::12 7179 # Per bank write bursts -system.physmem.perBankWrBursts::13 7101 # Per bank write bursts -system.physmem.perBankWrBursts::14 7219 # Per bank write bursts -system.physmem.perBankWrBursts::15 6983 # Per bank write bursts +system.physmem.num_writes::total 823705 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46487184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1670302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2011913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50485415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1631687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6525 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156181 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2794393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1631687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46487184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1676828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3168095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53279808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15301674 # Number of read requests accepted +system.physmem.writeReqs 823705 # Number of write requests accepted +system.physmem.readBursts 15301674 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823705 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 974584832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4722304 # Total number of bytes read from write queue +system.physmem.bytesWritten 7299840 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131526900 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7280080 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 73786 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709619 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14174 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956301 # Per bank write bursts +system.physmem.perBankRdBursts::1 950868 # Per bank write bursts +system.physmem.perBankRdBursts::2 950386 # Per bank write bursts +system.physmem.perBankRdBursts::3 950557 # Per bank write bursts +system.physmem.perBankRdBursts::4 956616 # Per bank write bursts +system.physmem.perBankRdBursts::5 950990 # Per bank write bursts +system.physmem.perBankRdBursts::6 949776 # Per bank write bursts +system.physmem.perBankRdBursts::7 949548 # Per bank write bursts +system.physmem.perBankRdBursts::8 956645 # Per bank write bursts +system.physmem.perBankRdBursts::9 951285 # Per bank write bursts +system.physmem.perBankRdBursts::10 949982 # Per bank write bursts +system.physmem.perBankRdBursts::11 948991 # Per bank write bursts +system.physmem.perBankRdBursts::12 956228 # Per bank write bursts +system.physmem.perBankRdBursts::13 950424 # Per bank write bursts +system.physmem.perBankRdBursts::14 949846 # Per bank write bursts +system.physmem.perBankRdBursts::15 949445 # Per bank write bursts +system.physmem.perBankWrBursts::0 7049 # Per bank write bursts +system.physmem.perBankWrBursts::1 6917 # Per bank write bursts +system.physmem.perBankWrBursts::2 7321 # Per bank write bursts +system.physmem.perBankWrBursts::3 7203 # Per bank write bursts +system.physmem.perBankWrBursts::4 7749 # Per bank write bursts +system.physmem.perBankWrBursts::5 7300 # Per bank write bursts +system.physmem.perBankWrBursts::6 7008 # Per bank write bursts +system.physmem.perBankWrBursts::7 6995 # Per bank write bursts +system.physmem.perBankWrBursts::8 7363 # Per bank write bursts +system.physmem.perBankWrBursts::9 7456 # Per bank write bursts +system.physmem.perBankWrBursts::10 6910 # Per bank write bursts +system.physmem.perBankWrBursts::11 6580 # Per bank write bursts +system.physmem.perBankWrBursts::12 7092 # Per bank write bursts +system.physmem.perBankWrBursts::13 7012 # Per bank write bursts +system.physmem.perBankWrBursts::14 7131 # Per bank write bursts +system.physmem.perBankWrBursts::15 6974 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605642823000 # Total gap between requests +system.physmem.totGap 2605244301000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 109 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 163263 # Read request sizes (log2) +system.physmem.readPktSize::6 162749 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66806 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1074226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1009957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 967065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1078396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 970167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1034458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2664402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2566961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3342237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 136100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 116220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 107345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66421 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1076672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1007796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 966781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1073648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 970528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1031139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2669789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2577083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3357471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 102015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -176,33 +176,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6828 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -225,73 +225,70 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1012463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 969.866853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 900.909804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.662919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24967 2.47% 2.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21104 2.08% 4.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8681 0.86% 5.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2506 0.25% 5.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2720 0.27% 5.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2029 0.20% 6.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8638 0.85% 6.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1014 0.10% 7.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 940804 92.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1012463 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6706 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2270.880853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 84552.226363 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6700 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6706 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6706 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.074560 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.020748 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.396636 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3829 57.10% 57.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 48 0.72% 57.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1779 26.53% 84.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 878 13.09% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 53 0.79% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 31 0.46% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 34 0.51% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 40 0.60% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.18% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6706 # Writes before turning the bus around for reads -system.physmem.totQLat 395588666000 # Total ticks spent queuing -system.physmem.totMemAccLat 681123678500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76142670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25976.81 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1012037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 970.206299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 901.657757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 207.022901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24841 2.45% 2.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20798 2.06% 4.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8822 0.87% 5.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2548 0.25% 5.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2540 0.25% 5.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1879 0.19% 6.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8798 0.87% 6.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1115 0.11% 7.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 940696 92.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1012037 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2278.257181 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 111148.889106 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6680 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.064632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.010880 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.396865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3849 57.59% 57.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 42 0.63% 58.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1749 26.17% 84.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 863 12.91% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 73 1.09% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 28 0.42% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.46% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 31 0.46% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.21% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads +system.physmem.totQLat 394529621500 # Total ticks spent queuing +system.physmem.totMemAccLat 680052521500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76139440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25908.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44726.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.04 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44658.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.94 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing -system.physmem.readRowHits 14234195 # Number of row buffer hits during reads -system.physmem.writeRowHits 96378 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 14233868 # Number of row buffer hits during reads +system.physmem.writeRowHits 96043 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.16 # Row buffer hit rate for writes -system.physmem.avgGap 161577.45 # Average gap between requests +system.physmem.writeRowHitRate 84.18 # Row buffer hit rate for writes +system.physmem.avgGap 161561.74 # Average gap between requests system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2260536385250 # Time in different power states -system.physmem.memoryStateTime::REF 87007960000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2261037204000 # Time in different power states +system.physmem.memoryStateTime::REF 86994700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 258093332250 # Time in different power states +system.physmem.memoryStateTime::ACT 257208674750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory @@ -311,299 +308,300 @@ system.realview.nvmem.bw_inst_read::total 172 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54224369 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352672 # Transaction distribution -system.membus.trans_dist::ReadResp 16352672 # Transaction distribution +system.membus.throughput 54210578 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352619 # Transaction distribution +system.membus.trans_dist::ReadResp 16352619 # Transaction distribution system.membus.trans_dist::WriteReq 769183 # Transaction distribution system.membus.trans_dist::WriteResp 769183 # Transaction distribution -system.membus.trans_dist::Writeback 66806 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35949 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18292 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14159 # Transaction distribution -system.membus.trans_dist::ReadExReq 138125 # Transaction distribution -system.membus.trans_dist::ReadExResp 137746 # Transaction distribution +system.membus.trans_dist::Writeback 66421 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35773 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18321 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14174 # Transaction distribution +system.membus.trans_dist::ReadExReq 137666 # Transaction distribution +system.membus.trans_dist::ReadExResp 137285 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4377155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975354 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4375612 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34654787 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34653244 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17753988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20178873 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17696452 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20121337 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141289401 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141289401 # Total data (bytes) +system.membus.tot_pkt_size::total 141231865 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141231865 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487962500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487709500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11808000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11701000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1796000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1799000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17659548997 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17608394498 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4847870095 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4825319244 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37379122644 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37398632151 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72974 # number of replacements -system.l2c.tags.tagsinuse 53023.948009 # Cycle average of tags in use -system.l2c.tags.total_refs 1873330 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 138152 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.559920 # Average number of references to valid blocks. +system.l2c.tags.replacements 72458 # number of replacements +system.l2c.tags.tagsinuse 53011.924457 # Cycle average of tags in use +system.l2c.tags.total_refs 1875821 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137631 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.629349 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37706.296895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.412172 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4169.126027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2962.597547 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.621110 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4061.748879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4107.145016 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575352 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37713.505334 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.216539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4181.052971 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2965.825646 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.076579 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4028.442908 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4106.804235 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575462 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061977 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062670 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.809081 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3154 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9081 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52631 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18850449 # Number of tag accesses -system.l2c.tags.data_accesses 18850449 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22712 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4441 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393676 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 33196 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5802 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 607870 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201576 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1434996 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583128 # 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uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036406 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017287 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.850408 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.839932 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.845796 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.786151 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776610 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.781985 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567500 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.565943 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.096586 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000216 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015074 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244637 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.096586 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61855.663374 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63802.981180 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61522.208785 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10032.540098 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10079.993939 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10053.284565 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.950777 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.994924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.102715 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56401.421988 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65247.633042 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61257.432586 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59992.112255 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56894.860917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60343.354907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65137.739949 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61297.973081 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -794,56 +792,56 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58718575 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2740966 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2740965 # Transaction distribution +system.toL2Bus.throughput 58770672 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2743232 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2743231 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583128 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35123 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53780 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259272 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259272 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800244 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13760 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56807 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1229764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15635 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8085518 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25589824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34686241 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17772 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39333696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48239320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148113805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148113805 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4885896 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4921313376 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 583097 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35011 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18701 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53712 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259154 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259154 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799809 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14034 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1233533 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820063 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15283 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75701 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8090245 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25576064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34728353 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18500 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39453888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48201112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22492 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132584 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148227457 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148227457 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4884572 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4922251450 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1803473389 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1802620121 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514355955 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1515652575 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9338456 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9436941 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34226949 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34537141 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2770248418 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2778792830 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 3257977460 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 3257203486 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 9851958 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 9681453 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 42643941 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 42845398 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47398342 # Throughput (bytes/s) +system.iobus.throughput 47405592 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution system.iobus.trans_dist::WriteReq 8083 # Transaction distribution @@ -953,17 +951,17 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38174483356 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38152801849 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6117114 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4670626 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296157 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3842728 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2949969 # Number of BTB hits +system.cpu0.branchPred.lookups 6193187 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4738042 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296192 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3876930 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2986045 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.767572 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 683314 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28361 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.020864 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 687525 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28310 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -987,25 +985,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8969403 # DTB read hits -system.cpu0.dtb.read_misses 29343 # DTB read misses -system.cpu0.dtb.write_hits 5210557 # DTB write hits -system.cpu0.dtb.write_misses 5731 # DTB write misses +system.cpu0.dtb.read_hits 8977307 # DTB read hits +system.cpu0.dtb.read_misses 29619 # DTB read misses +system.cpu0.dtb.write_hits 5215302 # DTB write hits +system.cpu0.dtb.write_misses 5680 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1050 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1732 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 993 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8998746 # DTB read accesses -system.cpu0.dtb.write_accesses 5216288 # DTB write accesses +system.cpu0.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9006926 # DTB read accesses +system.cpu0.dtb.write_accesses 5220982 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14179960 # DTB hits -system.cpu0.dtb.misses 35074 # DTB misses -system.cpu0.dtb.accesses 14215034 # DTB accesses +system.cpu0.dtb.hits 14192609 # DTB hits +system.cpu0.dtb.misses 35299 # DTB misses +system.cpu0.dtb.accesses 14227908 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1027,8 +1025,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4277605 # ITB inst hits -system.cpu0.itb.inst_misses 5145 # ITB inst misses +system.cpu0.itb.inst_hits 4299863 # ITB inst hits +system.cpu0.itb.inst_misses 5195 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1037,583 +1035,580 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1219 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1426 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1331 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4282750 # ITB inst accesses -system.cpu0.itb.hits 4277605 # DTB hits -system.cpu0.itb.misses 5145 # DTB misses -system.cpu0.itb.accesses 4282750 # DTB accesses -system.cpu0.numCycles 70248238 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4305058 # ITB inst accesses +system.cpu0.itb.hits 4299863 # DTB hits +system.cpu0.itb.misses 5195 # DTB misses +system.cpu0.itb.accesses 4305058 # DTB accesses +system.cpu0.numCycles 69478980 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11931842 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32451975 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6117114 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3633283 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7612739 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460869 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60951 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20309232 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46682 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1377400 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 299 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4276074 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 156796 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2089 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42393450 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.988978 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.370199 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11944453 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32774113 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6193187 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3673570 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7678957 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1502530 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 63317 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19508655 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6049 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47760 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1413705 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 248 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4298413 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 159366 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2185 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41753011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.013655 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.394447 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34788183 82.06% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 572054 1.35% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 825907 1.95% 85.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686377 1.62% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 779180 1.84% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 565083 1.33% 90.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 677221 1.60% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 357838 0.84% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3141607 7.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34081524 81.63% 81.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 576095 1.38% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 828597 1.98% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 688423 1.65% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 783359 1.88% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 570610 1.37% 89.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 698382 1.67% 91.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 360373 0.86% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3165648 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42393450 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.087079 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461961 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12487890 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21493629 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6874468 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552722 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 984741 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 950951 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64626 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40558878 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212020 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 984741 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13064503 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5883311 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13498743 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6804692 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2157460 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39446559 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 311 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 442642 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1180293 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 145 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39856275 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 180582545 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 163877057 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4135 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31488132 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8368142 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460013 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 416638 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5509006 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7758217 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5771757 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1123661 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1193308 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37348678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 906063 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37718806 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82800 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6312476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13233696 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257258 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42393450 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.889732 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.506737 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41753011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.089138 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471713 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12274082 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20961054 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7066192 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 425731 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1025952 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 955706 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65065 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40945366 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213036 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1025952 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12760478 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 3004976 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13648632 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 7041602 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4271371 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39802599 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1199 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1526731 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1438820 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1837389 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 522 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40279465 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 182145305 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 165318292 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4116 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31479900 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8799564 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 460456 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 417031 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4293085 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7837564 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5796369 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1159621 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1213862 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37649045 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 906994 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37770468 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93887 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6620221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14342287 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258409 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41753011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904617 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.539726 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27027469 63.75% 63.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5904750 13.93% 77.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3167008 7.47% 85.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2470651 5.83% 90.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2117188 4.99% 95.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 941206 2.22% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 520081 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 187957 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 57140 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26686839 63.92% 63.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5690671 13.63% 77.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3035101 7.27% 84.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2408430 5.77% 90.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2094356 5.02% 95.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 953036 2.28% 97.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 611124 1.46% 99.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 212675 0.51% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 60779 0.15% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42393450 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41753011 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26875 2.51% 2.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 458 0.04% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 836202 77.98% 80.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208765 19.47% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29050 2.58% 2.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 460 0.04% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 862862 76.64% 79.26% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 233562 20.74% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22694630 60.17% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47979 0.13% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14549 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22728130 60.17% 60.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48220 0.13% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.34% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9430195 25.00% 85.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5530734 14.66% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9442602 25.00% 85.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5536256 14.66% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37718806 # Type of FU issued -system.cpu0.iq.rate 0.536936 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1072300 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028429 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119012569 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44575137 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34852276 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8350 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38772197 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4358 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316382 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37770468 # Type of FU issued +system.cpu0.iq.rate 0.543624 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1125934 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.029810 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118540397 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45184408 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34905571 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8382 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38877516 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4337 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 330330 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1375838 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2694 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13105 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 538991 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1458060 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2363 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13414 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149907 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5937 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2141820 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5981 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 984741 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4273547 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 99764 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38372810 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83727 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7758217 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5771757 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 578717 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40350 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3282 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13105 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151036 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117828 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268864 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37337135 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9286340 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 381671 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1025952 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2385802 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 275075 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38676599 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 76106 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7837564 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5796369 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 579111 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 58653 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 199282 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13414 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149919 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118426 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268345 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37387044 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9294285 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 383424 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118069 # number of nop insts executed -system.cpu0.iew.exec_refs 14769450 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4962843 # Number of branches executed -system.cpu0.iew.exec_stores 5483110 # Number of stores executed -system.cpu0.iew.exec_rate 0.531503 # Inst execution rate -system.cpu0.iew.wb_sent 37142523 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34856145 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18592748 # num instructions producing a value -system.cpu0.iew.wb_consumers 35683758 # num instructions consuming a value +system.cpu0.iew.exec_nop 120560 # number of nop insts executed +system.cpu0.iew.exec_refs 14782259 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4971290 # Number of branches executed +system.cpu0.iew.exec_stores 5487974 # Number of stores executed +system.cpu0.iew.exec_rate 0.538106 # Inst execution rate +system.cpu0.iew.wb_sent 37190474 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34909443 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18996365 # num instructions producing a value +system.cpu0.iew.wb_consumers 36943291 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496185 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.521042 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.502446 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.514203 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6125993 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 648805 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232656 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41408709 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.767702 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.726975 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6443412 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 648585 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232277 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40727059 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.780301 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.748318 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29445863 71.11% 71.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5939620 14.34% 85.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1940870 4.69% 90.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1013361 2.45% 92.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 759448 1.83% 94.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 515426 1.24% 95.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 408347 0.99% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 223076 0.54% 97.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1162698 2.81% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28935599 71.05% 71.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5796697 14.23% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1842943 4.53% 89.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1067095 2.62% 92.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 737891 1.81% 94.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 511993 1.26% 95.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 448684 1.10% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 197374 0.48% 97.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1188783 2.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41408709 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24071577 # Number of instructions committed -system.cpu0.commit.committedOps 31789563 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40727059 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24067678 # Number of instructions committed +system.cpu0.commit.committedOps 31779383 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11615145 # Number of memory references committed -system.cpu0.commit.loads 6382379 # Number of loads committed -system.cpu0.commit.membars 231812 # Number of memory barriers committed -system.cpu0.commit.branches 4351457 # Number of branches committed +system.cpu0.commit.refs 11609911 # Number of memory references committed +system.cpu0.commit.loads 6379504 # Number of loads committed +system.cpu0.commit.membars 231786 # Number of memory barriers committed +system.cpu0.commit.branches 4350837 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28135168 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498959 # Number of function calls committed. +system.cpu0.commit.int_insts 28125415 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498912 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 20133954 63.34% 63.34% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39784 0.13% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6382379 20.08% 83.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5232766 16.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 20129006 63.34% 63.34% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39786 0.13% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.47% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6379504 20.07% 83.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5230407 16.46% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 31789563 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1162698 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 31779383 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1188783 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77292791 # The number of ROB reads -system.cpu0.rob.rob_writes 76817595 # The number of ROB writes -system.cpu0.timesIdled 365665 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27854788 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5140997105 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23990835 # Number of Instructions Simulated -system.cpu0.committedOps 31708821 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.928128 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.928128 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341515 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341515 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174285855 # number of integer regfile reads -system.cpu0.int_regfile_writes 34604955 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3294 # number of floating regfile reads -system.cpu0.fp_regfile_writes 912 # number of floating regfile writes -system.cpu0.misc_regfile_reads 79299010 # number of misc regfile reads -system.cpu0.misc_regfile_writes 500883 # number of misc regfile writes -system.cpu0.icache.tags.replacements 399739 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.543627 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3844274 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 400251 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.604658 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7097393250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.543627 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999109 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999109 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 76892389 # The number of ROB reads +system.cpu0.rob.rob_writes 77473478 # The number of ROB writes +system.cpu0.timesIdled 368167 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27725969 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5140969387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23986936 # Number of Instructions Simulated +system.cpu0.committedOps 31698641 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.896534 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.896534 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.345240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.345240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174527841 # number of integer regfile reads +system.cpu0.int_regfile_writes 34672219 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3319 # number of floating regfile reads +system.cpu0.fp_regfile_writes 920 # number of floating regfile writes +system.cpu0.misc_regfile_reads 78617689 # number of misc regfile reads +system.cpu0.misc_regfile_writes 500675 # number of misc regfile writes +system.cpu0.icache.tags.replacements 399525 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.581560 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3866760 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 400037 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.666006 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6951542250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.581560 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999183 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4676219 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4676219 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3844274 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3844274 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3844274 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3844274 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3844274 # number of overall hits -system.cpu0.icache.overall_hits::total 3844274 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431668 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431668 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431668 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431668 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431668 # number of overall misses -system.cpu0.icache.overall_misses::total 431668 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5966691765 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5966691765 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5966691765 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5966691765 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5966691765 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5966691765 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4275942 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4275942 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4275942 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4275942 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4275942 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4275942 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100953 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100953 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100953 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100953 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100953 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100953 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13822.409271 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13822.409271 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4149 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 4698333 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 4698333 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 3866760 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3866760 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3866760 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3866760 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3866760 # number of overall hits +system.cpu0.icache.overall_hits::total 3866760 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431519 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431519 # number of ReadReq misses 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accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4298279 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4298279 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4298279 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4298279 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4298279 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100393 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100393 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100393 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100393 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100393 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100393 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.347901 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13820.347901 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13820.347901 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13820.347901 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4778 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.122093 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.493827 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31390 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31390 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31390 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31390 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31390 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31390 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400278 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 400278 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 400278 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 400278 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 400278 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 400278 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859637603 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4859637603 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859637603 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4859637603 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859637603 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4859637603 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9490000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9490000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9490000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9490000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093612 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093612 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093612 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093612 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12140.656251 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12140.656251 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12140.656251 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31464 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31464 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31464 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31464 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31464 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31464 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400055 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 400055 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 400055 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 400055 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 400055 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 400055 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4860147872 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4860147872 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4860147872 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4860147872 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4860147872 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4860147872 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9713500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9713500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9713500 # number of overall MSHR uncacheable cycles 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overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12148.699234 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12148.699234 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 275002 # number of replacements -system.cpu0.dcache.tags.tagsinuse 479.873805 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9429051 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 275514 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.223491 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43985250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.873805 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937254 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.937254 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 275167 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.361699 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9408418 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 275679 # Sample count of references to valid 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LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144959 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144959 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11080065 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11080065 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11080065 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11080065 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062623 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062623 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328894 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328894 # miss rate for WriteReq accesses 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average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9513 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7748 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 587 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.206133 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 56.970588 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 45804428 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45804428 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5867272 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5867272 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3220606 # number of WriteReq hits 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accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11079785 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11079785 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064288 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.064288 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330352 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330352 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060114 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060114 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053531 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053531 # miss rate for StoreCondReq accesses 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14.636220 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 57.451327 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255347 # number of writebacks -system.cpu0.dcache.writebacks::total 255347 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203411 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203411 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451593 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451593 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655004 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1655004 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655004 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1655004 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189129 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189129 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130957 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130957 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8410 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7747 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7747 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320086 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320086 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320086 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320086 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2397985131 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2397985131 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338215866 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338215866 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69513767 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69513767 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34349239 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34349239 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7736200997 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7736200997 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7736200997 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7736200997 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434640527 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434640527 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206086382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206086382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640726909 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640726909 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030172 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030172 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027216 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027216 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056654 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056654 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053443 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053443 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028888 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028888 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8265.608442 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8265.608442 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4433.876210 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4433.876210 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255545 # number of writebacks +system.cpu0.dcache.writebacks::total 255545 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 213826 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 213826 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457949 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1457949 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1671775 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1671775 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1671775 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1671775 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189284 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189284 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130848 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130848 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320132 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320132 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320132 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320132 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2416725188 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2416725188 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5154000431 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5154000431 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69605516 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69605516 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34529233 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34529233 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7570725619 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7570725619 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7570725619 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7570725619 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434660545 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434660545 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206058380 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206058380 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640718925 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640718925 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030187 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030187 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056953 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056953 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053531 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053531 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028893 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028893 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8236.364454 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8236.364454 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4450.790539 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4450.790539 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1621,15 +1616,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9293378 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7631598 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 415998 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5889507 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5046361 # Number of BTB hits +system.cpu1.branchPred.lookups 9402679 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7728805 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 418099 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6037829 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5108046 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.683929 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 797302 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43622 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.600707 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 802186 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 44176 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1653,25 +1648,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42971422 # DTB read hits -system.cpu1.dtb.read_misses 37905 # DTB read misses -system.cpu1.dtb.write_hits 6976449 # DTB write hits -system.cpu1.dtb.write_misses 10883 # DTB write misses +system.cpu1.dtb.read_hits 42878527 # DTB read hits +system.cpu1.dtb.read_misses 38253 # DTB read misses +system.cpu1.dtb.write_hits 6985734 # DTB write hits +system.cpu1.dtb.write_misses 10793 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2893 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 296 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2963 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43009327 # DTB read accesses -system.cpu1.dtb.write_accesses 6987332 # DTB write accesses +system.cpu1.dtb.perms_faults 687 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42916780 # DTB read accesses +system.cpu1.dtb.write_accesses 6996527 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49947871 # DTB hits -system.cpu1.dtb.misses 48788 # DTB misses -system.cpu1.dtb.accesses 49996659 # DTB accesses +system.cpu1.dtb.hits 49864261 # DTB hits +system.cpu1.dtb.misses 49046 # DTB misses +system.cpu1.dtb.accesses 49913307 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1693,8 +1688,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7719787 # ITB inst hits -system.cpu1.itb.inst_misses 5634 # ITB inst misses +system.cpu1.itb.inst_hits 7755980 # ITB inst hits +system.cpu1.itb.inst_misses 5491 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1703,574 +1698,579 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1362 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1538 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1507 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7725421 # ITB inst accesses -system.cpu1.itb.hits 7719787 # DTB hits -system.cpu1.itb.misses 5634 # DTB misses -system.cpu1.itb.accesses 7725421 # DTB accesses -system.cpu1.numCycles 413693823 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7761471 # ITB inst accesses +system.cpu1.itb.hits 7755980 # DTB hits +system.cpu1.itb.misses 5491 # DTB misses +system.cpu1.itb.accesses 7761471 # DTB accesses +system.cpu1.numCycles 413132210 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19372544 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61318271 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9293378 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5843663 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13362487 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3346253 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 69736 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 80999073 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 19420388 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61788688 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9402679 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5910232 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13466568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3411318 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 67616 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77041165 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42062 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1494344 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7717920 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 551887 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2996 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 117635394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.638004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.959630 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 42813 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1523639 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7754163 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 555305 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2851 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113918823 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663934 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.994464 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 104280280 88.65% 88.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 814710 0.69% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 961160 0.82% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1713171 1.46% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1415249 1.20% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 586962 0.50% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1954597 1.66% 94.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 422243 0.36% 95.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5487022 4.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100459727 88.19% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820479 0.72% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 969052 0.85% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1718827 1.51% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1427854 1.25% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 590556 0.52% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1988498 1.75% 94.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 426289 0.37% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5517541 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 117635394 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022464 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.148221 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20963679 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 81759193 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11913295 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 809519 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2189708 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1137363 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100954 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71089276 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 336011 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2189708 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22156707 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33902507 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 43325786 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11473545 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4587141 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67137864 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 137 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 682095 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3075433 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1010 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 70763032 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 313108743 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 286757803 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6623 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50416422 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20346610 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 765987 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 705836 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8420477 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12843204 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8115826 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1055497 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1512633 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 61850161 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1179252 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88896986 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93979 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13548762 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36246660 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 279849 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 117635394 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.755699 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.498688 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113918823 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022759 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.149562 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20573629 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78271180 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12141436 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 681674 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2250904 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1146333 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 101070 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71648546 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 337709 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2250904 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21753755 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 11785871 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 44839476 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11758144 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 21530673 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67615561 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 613 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 15671923 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18336953 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1545811 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 1295 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 71310682 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 315205355 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 288681323 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6622 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50413608 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20897074 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 766814 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 706637 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7207016 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12951593 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8155935 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1106689 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1533453 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62295252 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1184366 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88905891 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 106644 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13983630 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 37714490 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 285025 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113918823 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780432 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.530885 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86772303 73.76% 73.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9298113 7.90% 81.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4175598 3.55% 85.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3594840 3.06% 88.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10374006 8.82% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1994938 1.70% 98.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1065613 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 281099 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78884 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83813472 73.57% 73.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8528665 7.49% 81.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3988574 3.50% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3433815 3.01% 87.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10704573 9.40% 96.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1891022 1.66% 98.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1169449 1.03% 99.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 305487 0.27% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 83766 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 117635394 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113918823 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32152 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 986 0.01% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7573471 95.70% 96.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 306947 3.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 34951 0.44% 0.44% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 989 0.01% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7593663 95.44% 95.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 326577 4.10% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14268 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37614404 42.31% 42.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43858329 49.34% 91.74% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7347048 8.26% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14267 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37698483 42.40% 42.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61348 0.07% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.49% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43772925 49.24% 91.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7357130 8.28% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88896986 # Type of FU issued -system.cpu1.iq.rate 0.214886 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7913556 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089019 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 303469985 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 76586992 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54255274 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15534 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8108 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6874 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96788024 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8250 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 355713 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88905891 # Type of FU issued +system.cpu1.iq.rate 0.215200 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7956180 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089490 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 299826864 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77472999 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54370047 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15424 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8128 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6867 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96839621 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8183 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 371805 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2862172 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4122 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17485 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1111950 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2971595 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3826 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 18443 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1153168 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965671 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675853 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31846626 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675699 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2189708 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26386476 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 363440 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63133555 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 115239 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12843204 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8115826 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 883054 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 66097 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4286 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17485 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 204520 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158639 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 363159 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87164207 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43354058 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1732779 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2250904 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 9489416 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1235015 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63585663 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 104803 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12951593 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8155935 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 886916 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 232294 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 885959 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 18443 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 206591 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158855 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 365446 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87166570 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43262018 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1739321 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104142 # number of nop insts executed -system.cpu1.iew.exec_refs 50636612 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7376811 # Number of branches executed -system.cpu1.iew.exec_stores 7282554 # Number of stores executed -system.cpu1.iew.exec_rate 0.210697 # Inst execution rate -system.cpu1.iew.wb_sent 86400335 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54262148 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30287291 # num instructions producing a value -system.cpu1.iew.wb_consumers 53873069 # num instructions consuming a value +system.cpu1.iew.exec_nop 106045 # number of nop insts executed +system.cpu1.iew.exec_refs 50553896 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7398817 # Number of branches executed +system.cpu1.iew.exec_stores 7291878 # Number of stores executed +system.cpu1.iew.exec_rate 0.210990 # Inst execution rate +system.cpu1.iew.wb_sent 86399299 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54376914 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30829889 # num instructions producing a value +system.cpu1.iew.wb_consumers 55266228 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131165 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.562197 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131621 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.557843 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13443206 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899403 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 316783 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 115445686 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.426296 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.378874 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13879712 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899341 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 318567 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111667919 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.440684 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.404622 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97421932 84.39% 84.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9594899 8.31% 92.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2172227 1.88% 94.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1301741 1.13% 95.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 988993 0.86% 96.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 587152 0.51% 97.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1008803 0.87% 97.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 534624 0.46% 98.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1835315 1.59% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 93786179 83.99% 83.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9487781 8.50% 92.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2098555 1.88% 94.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1338170 1.20% 95.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 960614 0.86% 96.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 571645 0.51% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1030883 0.92% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 527820 0.47% 98.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1866272 1.67% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 115445686 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38873610 # Number of instructions committed -system.cpu1.commit.committedOps 49214014 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111667919 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38872746 # Number of instructions committed +system.cpu1.commit.committedOps 49210296 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16984908 # Number of memory references committed -system.cpu1.commit.loads 9981032 # Number of loads committed -system.cpu1.commit.membars 195536 # Number of memory barriers committed -system.cpu1.commit.branches 6424997 # Number of branches committed +system.cpu1.commit.refs 16982765 # Number of memory references committed +system.cpu1.commit.loads 9979998 # Number of loads committed +system.cpu1.commit.membars 195533 # Number of memory barriers committed +system.cpu1.commit.branches 6424967 # Number of branches committed system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43926362 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553376 # Number of function calls committed. +system.cpu1.commit.int_insts 43922606 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553368 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 32169137 65.37% 65.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 58263 0.12% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 32167564 65.37% 65.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 58261 0.12% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9981032 20.28% 85.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7003876 14.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9979998 20.28% 85.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 7002767 14.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 49214014 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1835315 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 49210296 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1866272 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175201017 # The number of ROB reads -system.cpu1.rob.rob_writes 127586843 # The number of ROB writes -system.cpu1.timesIdled 1428644 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 296058429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796946974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38803971 # Number of Instructions Simulated -system.cpu1.committedOps 49144375 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 10.661121 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.661121 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093799 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093799 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391634066 # number of integer regfile reads -system.cpu1.int_regfile_writes 56368159 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5144 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 202762353 # number of misc regfile reads -system.cpu1.misc_regfile_writes 723009 # number of misc regfile writes -system.cpu1.icache.tags.replacements 614589 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.738252 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7056364 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 615101 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.471879 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74953244500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.738252 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974098 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974098 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 171825162 # The number of ROB reads +system.cpu1.rob.rob_writes 128514038 # The number of ROB writes +system.cpu1.timesIdled 1427088 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 299213387 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796716848 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38803107 # Number of Instructions Simulated +system.cpu1.committedOps 49140657 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 10.646885 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.646885 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093924 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093924 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391718305 # number of integer regfile reads +system.cpu1.int_regfile_writes 56505033 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5108 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes +system.cpu1.misc_regfile_reads 199117817 # number of misc regfile reads +system.cpu1.misc_regfile_writes 722972 # number of misc regfile writes +system.cpu1.icache.tags.replacements 616464 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.721065 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7090163 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 616976 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.491797 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74744507500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.721065 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974065 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974065 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8332995 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8332995 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 7056364 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7056364 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7056364 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7056364 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7056364 # number of overall hits -system.cpu1.icache.overall_hits::total 7056364 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661505 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661505 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661505 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661505 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661505 # number of overall misses -system.cpu1.icache.overall_misses::total 661505 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8964922762 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8964922762 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8964922762 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8964922762 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8964922762 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8964922762 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7717869 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7717869 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7717869 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7717869 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7717869 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7717869 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085711 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.085711 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085711 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.085711 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085711 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.085711 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13552.312926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13552.312926 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3582 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 212 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.896226 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 8371129 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8371129 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7090163 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7090163 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7090163 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7090163 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7090163 # number of overall hits +system.cpu1.icache.overall_hits::total 7090163 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 663949 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 663949 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 663949 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 663949 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 663949 # number of overall misses +system.cpu1.icache.overall_misses::total 663949 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9003300184 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9003300184 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9003300184 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9003300184 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9003300184 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9003300184 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7754112 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7754112 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7754112 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7754112 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7754112 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7754112 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085625 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.085625 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085625 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.085625 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085625 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.085625 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13560.228548 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13560.228548 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3101 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 648 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 217 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.290323 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 648 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46379 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46379 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46379 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46379 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46379 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46379 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615126 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 615126 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 615126 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 615126 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 615126 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 615126 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7320744820 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7320744820 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7320744820 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7320744820 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7320744820 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7320744820 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3847250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3847250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3847250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3847250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079702 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079702 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079702 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11901.211817 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11901.211817 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11901.211817 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46932 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46932 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46932 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46932 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46932 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46932 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 617017 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 617017 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 617017 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 617017 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 617017 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 617017 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343865656 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343865656 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343865656 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7343865656 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343865656 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7343865656 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4135000 # number of ReadReq MSHR uncacheable cycles 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11902.209592 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 363297 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.117445 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 13019165 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 363645 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.801853 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 71011321250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.117445 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949448 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949448 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 60291027 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 60291027 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8513196 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8513196 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4271027 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4271027 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99804 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 99804 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97081 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 97081 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12784223 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12784223 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12784223 # number of overall hits -system.cpu1.dcache.overall_hits::total 12784223 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 403038 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 403038 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1566274 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1566274 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14187 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14187 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10911 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10911 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1969312 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1969312 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1969312 # number of overall misses -system.cpu1.dcache.overall_misses::total 1969312 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6108097691 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6108097691 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 77891341203 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 77891341203 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131130743 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131130743 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58206088 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58206088 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 83999438894 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 83999438894 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 83999438894 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 83999438894 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8916234 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8916234 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837301 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5837301 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113991 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 113991 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107992 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107992 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14753535 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14753535 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14753535 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14753535 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045203 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045203 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268322 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.268322 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124457 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124457 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101035 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101035 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133481 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.133481 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133481 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.133481 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 49730.341692 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9243.021287 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9243.021287 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.624507 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.624507 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 42654.205577 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42654.205577 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 42654.205577 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29593 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18156 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 363234 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.053035 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13011922 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 363603 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.786069 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70837218250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.053035 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947369 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.947369 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 60324528 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 60324528 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8516413 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8516413 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4259216 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4259216 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99616 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 99616 # number of LoadLockedReq hits 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+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10944 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10944 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1986483 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1986483 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1986483 # number of overall misses +system.cpu1.dcache.overall_misses::total 1986483 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6227092173 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6227092173 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 74233295889 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 74233295889 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131030244 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131030244 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58441088 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58441088 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 80460388062 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 80460388062 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 80460388062 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 80460388062 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8925901 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8925901 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5836211 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5836211 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113826 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 113826 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108002 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 108002 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14762112 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14762112 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14762112 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14762112 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045876 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045876 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.270209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.270209 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124840 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124840 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101331 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101331 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134566 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134566 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134566 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134566 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9220.988318 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9220.988318 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5340.011696 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5340.011696 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 30714 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17665 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.003042 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 103.748571 # average number of cycles each access was blocked +system.cpu1.dcache.blocked::no_targets 190 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.344083 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 92.973684 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327781 # number of writebacks -system.cpu1.dcache.writebacks::total 327781 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171674 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171674 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1403027 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1403027 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1467 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1467 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574701 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1574701 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574701 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1574701 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231364 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231364 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163247 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163247 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10911 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10911 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394611 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394611 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394611 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394611 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2878773157 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2878773157 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7001686259 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7001686259 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89753005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89753005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36382912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36382912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9880459416 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9880459416 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9880459416 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9880459416 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25869959988 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25869959988 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025949 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025949 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027966 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027966 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111588 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111588 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101035 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101035 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026747 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026747 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7056.053852 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7056.053852 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3334.516726 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3334.516726 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327552 # number of writebacks +system.cpu1.dcache.writebacks::total 327552 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178171 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 178171 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1413840 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1413840 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1592011 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1592011 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1592011 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1592011 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231317 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231317 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163155 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163155 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12755 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12755 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10944 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10944 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394472 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394472 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394472 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394472 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2894401946 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2894401946 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6921941032 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6921941032 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89586755 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89586755 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36550912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36550912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9816342978 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9816342978 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9816342978 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9816342978 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25874415734 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25874415734 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025915 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025915 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112057 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112057 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101331 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026722 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026722 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7023.657781 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7023.657781 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3339.812865 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3339.812865 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2294,18 +2294,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1735350782356 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1734300149849 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42636 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42635 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50408 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50404 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal Binary files differindex ff60c1de9..9ab4c62df 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 9bc002187..f4610569d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -831,9 +832,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -844,27 +845,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 9a2da36f9..c786d9a25 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:42:01 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 - 0: system.cpu.isa: ISA system set to: 0x6dd8800 0x6dd8800 +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x4e2f380 0x4e2f380 info: Using bootloader at address 0x80000000 info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2526146947500 because m5_exit instruction encountered +Exiting @ tick 2525888859000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 4ddd9308a..8259c3ed2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526192 # Number of seconds simulated -sim_ticks 2526192217500 # Number of ticks simulated -final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525889 # Number of seconds simulated +sim_ticks 2525888859000 # Number of ticks simulated +final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56578 # Simulator instruction rate (inst/s) -host_op_rate 72800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2369913329 # Simulator tick rate (ticks/s) -host_mem_usage 467016 # Number of bytes of host memory used -host_seconds 1065.94 # Real time elapsed on the host -sim_insts 60309034 # Number of instructions simulated -sim_ops 77600502 # Number of ops (including micro ops) simulated +host_inst_rate 66506 # Simulator instruction rate (inst/s) +host_op_rate 85575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2785423099 # Simulator tick rate (ticks/s) +host_mem_usage 419792 # Number of bytes of host memory used +host_seconds 906.82 # Real time elapsed on the host +sim_insts 60309513 # Number of instructions simulated +sim_ops 77601128 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096864 # Number of read requests accepted -system.physmem.writeReqs 813148 # Number of write requests accepted -system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue -system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943480 # Per bank write bursts -system.physmem.perBankRdBursts::1 937980 # Per bank write bursts -system.physmem.perBankRdBursts::2 937559 # Per bank write bursts -system.physmem.perBankRdBursts::3 937528 # Per bank write bursts -system.physmem.perBankRdBursts::4 943087 # Per bank write bursts -system.physmem.perBankRdBursts::5 937982 # Per bank write bursts -system.physmem.perBankRdBursts::6 937070 # Per bank write bursts -system.physmem.perBankRdBursts::7 936990 # Per bank write bursts -system.physmem.perBankRdBursts::8 943982 # Per bank write bursts -system.physmem.perBankRdBursts::9 938303 # Per bank write bursts -system.physmem.perBankRdBursts::10 937119 # Per bank write bursts -system.physmem.perBankRdBursts::11 936407 # Per bank write bursts -system.physmem.perBankRdBursts::12 943924 # Per bank write bursts -system.physmem.perBankRdBursts::13 938214 # Per bank write bursts -system.physmem.perBankRdBursts::14 937241 # Per bank write bursts -system.physmem.perBankRdBursts::15 937211 # Per bank write bursts -system.physmem.perBankWrBursts::0 6601 # Per bank write bursts -system.physmem.perBankWrBursts::1 6388 # Per bank write bursts -system.physmem.perBankWrBursts::2 6528 # Per bank write bursts -system.physmem.perBankWrBursts::3 6554 # Per bank write bursts -system.physmem.perBankWrBursts::4 6464 # Per bank write bursts -system.physmem.perBankWrBursts::5 6726 # Per bank write bursts -system.physmem.perBankWrBursts::6 6713 # Per bank write bursts -system.physmem.perBankWrBursts::7 6652 # Per bank write bursts -system.physmem.perBankWrBursts::8 7031 # Per bank write bursts -system.physmem.perBankWrBursts::9 6803 # Per bank write bursts -system.physmem.perBankWrBursts::10 6461 # Per bank write bursts -system.physmem.perBankWrBursts::11 6104 # Per bank write bursts -system.physmem.perBankWrBursts::12 7064 # Per bank write bursts -system.physmem.perBankWrBursts::13 6684 # Per bank write bursts -system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6836 # Per bank write bursts +system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096846 # Number of read requests accepted +system.physmem.writeReqs 813159 # Number of write requests accepted +system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue +system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943526 # Per bank write bursts +system.physmem.perBankRdBursts::1 937990 # Per bank write bursts +system.physmem.perBankRdBursts::2 937469 # Per bank write bursts +system.physmem.perBankRdBursts::3 937431 # Per bank write bursts +system.physmem.perBankRdBursts::4 943079 # Per bank write bursts +system.physmem.perBankRdBursts::5 938170 # Per bank write bursts +system.physmem.perBankRdBursts::6 937203 # Per bank write bursts +system.physmem.perBankRdBursts::7 936910 # Per bank write bursts +system.physmem.perBankRdBursts::8 943866 # Per bank write bursts +system.physmem.perBankRdBursts::9 938107 # Per bank write bursts +system.physmem.perBankRdBursts::10 936563 # Per bank write bursts +system.physmem.perBankRdBursts::11 936045 # Per bank write bursts +system.physmem.perBankRdBursts::12 943886 # Per bank write bursts +system.physmem.perBankRdBursts::13 937531 # Per bank write bursts +system.physmem.perBankRdBursts::14 937186 # Per bank write bursts +system.physmem.perBankRdBursts::15 937024 # Per bank write bursts +system.physmem.perBankWrBursts::0 6617 # Per bank write bursts +system.physmem.perBankWrBursts::1 6376 # Per bank write bursts +system.physmem.perBankWrBursts::2 6529 # Per bank write bursts +system.physmem.perBankWrBursts::3 6558 # Per bank write bursts +system.physmem.perBankWrBursts::4 6459 # Per bank write bursts +system.physmem.perBankWrBursts::5 6705 # Per bank write bursts +system.physmem.perBankWrBursts::6 6711 # Per bank write bursts +system.physmem.perBankWrBursts::7 6649 # Per bank write bursts +system.physmem.perBankWrBursts::8 7036 # Per bank write bursts +system.physmem.perBankWrBursts::9 6794 # Per bank write bursts +system.physmem.perBankWrBursts::10 6454 # Per bank write bursts +system.physmem.perBankWrBursts::11 6111 # Per bank write bursts +system.physmem.perBankWrBursts::12 7073 # Per bank write bursts +system.physmem.perBankWrBursts::13 6679 # Per bank write bursts +system.physmem.perBankWrBursts::14 6963 # Per bank write bursts +system.physmem.perBankWrBursts::15 6824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526191083500 # Total gap between requests +system.physmem.totGap 2525887732500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154618 # Read request sizes (log2) +system.physmem.readPktSize::6 154600 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59130 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +159,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,50 +208,49 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads -system.physmem.totQLat 389908010000 # Total ticks spent queuing -system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads +system.physmem.totQLat 389024977250 # Total ticks spent queuing +system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -259,18 +258,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing -system.physmem.readRowHits 14044000 # Number of row buffer hits during reads -system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing +system.physmem.readRowHits 14042089 # Number of row buffer hits during reads +system.physmem.writeRowHits 91063 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.avgGap 158760.96 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states -system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states +system.physmem.memoryStateTime::REF 84344780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -284,50 +283,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54877773 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149486 # Transaction distribution -system.membus.trans_dist::ReadResp 16149486 # Transaction distribution +system.membus.throughput 54884184 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149487 # Transaction distribution +system.membus.trans_dist::ReadResp 16149487 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59130 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution +system.membus.trans_dist::Writeback 59141 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution -system.membus.trans_dist::ReadExReq 131451 # Transaction distribution -system.membus.trans_dist::ReadExResp 131451 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution +system.membus.trans_dist::ReadExReq 131431 # Transaction distribution +system.membus.trans_dist::ReadExResp 131431 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631802 # Total data (bytes) +system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631350 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -335,13 +334,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48265574 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution +system.iobus.throughput 48271369 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution system.iobus.trans_dist::WriteResp 8174 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -363,12 +362,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -390,14 +389,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928118 # Total data (bytes) +system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121928114 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -443,20 +442,20 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14753661 # Number of BP lookups -system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits +system.cpu.branchPred.lookups 14910337 # Number of BP lookups +system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -480,25 +479,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51183231 # DTB read hits -system.cpu.dtb.read_misses 65223 # DTB read misses -system.cpu.dtb.write_hits 11700953 # DTB write hits -system.cpu.dtb.write_misses 15725 # DTB write misses +system.cpu.dtb.read_hits 51097792 # DTB read hits +system.cpu.dtb.read_misses 64987 # DTB read misses +system.cpu.dtb.write_hits 11709971 # DTB write hits +system.cpu.dtb.write_misses 15921 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51248454 # DTB read accesses -system.cpu.dtb.write_accesses 11716678 # DTB write accesses +system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51162779 # DTB read accesses +system.cpu.dtb.write_accesses 11725892 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62884184 # DTB hits -system.cpu.dtb.misses 80948 # DTB misses -system.cpu.dtb.accesses 62965132 # DTB accesses +system.cpu.dtb.hits 62807763 # DTB hits +system.cpu.dtb.misses 80908 # DTB misses +system.cpu.dtb.accesses 62888671 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -520,8 +519,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11525561 # ITB inst hits -system.cpu.itb.inst_misses 11159 # ITB inst misses +system.cpu.itb.inst_hits 11575507 # ITB inst hits +system.cpu.itb.inst_misses 11335 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -530,265 +529,266 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11536720 # ITB inst accesses -system.cpu.itb.hits 11525561 # DTB hits -system.cpu.itb.misses 11159 # DTB misses -system.cpu.itb.accesses 11536720 # DTB accesses -system.cpu.numCycles 477128882 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11586842 # ITB inst accesses +system.cpu.itb.hits 11575507 # DTB hits +system.cpu.itb.misses 11335 # DTB misses +system.cpu.itb.accesses 11586842 # DTB accesses +system.cpu.numCycles 476238509 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued -system.cpu.iq.rate 0.257622 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued +system.cpu.iq.rate 0.258180 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222849 # number of nop insts executed -system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed -system.cpu.iew.exec_branches 11822089 # Number of branches executed -system.cpu.iew.exec_stores 12212847 # Number of stores executed -system.cpu.iew.exec_rate 0.253272 # Inst execution rate -system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47017508 # num instructions producing a value -system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value +system.cpu.iew.exec_nop 226309 # number of nop insts executed +system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed +system.cpu.iew.exec_branches 11843747 # Number of branches executed +system.cpu.iew.exec_stores 12222179 # Number of stores executed +system.cpu.iew.exec_rate 0.253798 # Inst execution rate +system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47892202 # num instructions producing a value +system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459415 # Number of instructions committed -system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459894 # Number of instructions committed +system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386618 # Number of memory references committed -system.cpu.commit.loads 15654647 # Number of loads committed -system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 10306311 # Number of branches committed +system.cpu.commit.refs 27386881 # Number of memory references committed +system.cpu.commit.loads 15654781 # Number of loads committed +system.cpu.commit.membars 403574 # Number of memory barriers committed +system.cpu.commit.branches 10306383 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. -system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. +system.cpu.commit.function_calls 991261 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction @@ -817,319 +817,319 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction -system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction +system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243007370 # The number of ROB reads -system.cpu.rob.rob_writes 195993770 # The number of ROB writes -system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309034 # Number of Instructions Simulated -system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548643015 # number of integer regfile reads -system.cpu.int_regfile_writes 87545924 # number of integer regfile writes -system.cpu.fp_regfile_reads 8332 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution +system.cpu.rob.rob_reads 239318561 # The number of ROB reads +system.cpu.rob.rob_writes 197472000 # The number of ROB writes +system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309513 # Number of Instructions Simulated +system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548833940 # number of integer regfile reads +system.cpu.int_regfile_writes 87707844 # number of integer regfile writes +system.cpu.fp_regfile_reads 8328 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) 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demand accesses -system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits +system.cpu.icache.overall_hits::total 10510158 # number of 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accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits 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-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583712225 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11583712225 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits 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miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64387 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092489 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency 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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency 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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1250,168 +1250,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 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blocks. +system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 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-system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) 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# miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 20997707 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20997707 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20997707 # number of overall hits +system.cpu.dcache.overall_hits::total 20997707 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 762201 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 762201 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2968429 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2968429 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13530 # number of LoadLockedReq misses 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accesses +system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks -system.cpu.dcache.writebacks::total 607456 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks +system.cpu.dcache.writebacks::total 607940 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1435,16 +1435,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 8f4cb76c4..69a162eed 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index b551f2cf3..e53092e6a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -97,6 +97,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -126,6 +127,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu0.tracer @@ -326,6 +328,7 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU children=dstage2_mmu dtb isa istage2_mmu itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -349,6 +352,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=true system=system tracer=system.cpu1.tracer @@ -543,6 +547,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=true @@ -1111,9 +1116,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1124,27 +1129,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 21d388ebd..bb9bfcfdd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 19:05:28 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400 - 0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400 - 0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400 + 0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 60f6414c0..d741bed70 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403852 # Number of seconds simulated -sim_ticks 2403852457500 # Number of ticks simulated -final_tick 2403852457500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403860 # Number of seconds simulated +sim_ticks 2403859810000 # Number of ticks simulated +final_tick 2403859810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165592 # Simulator instruction rate (inst/s) -host_op_rate 212680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6597855857 # Simulator tick rate (ticks/s) -host_mem_usage 469068 # Number of bytes of host memory used -host_seconds 364.34 # Real time elapsed on the host -sim_insts 60331653 # Number of instructions simulated -sim_ops 77487544 # Number of ops (including micro ops) simulated +host_inst_rate 189252 # Simulator instruction rate (inst/s) +host_op_rate 243065 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7540617560 # Simulator tick rate (ticks/s) +host_mem_usage 419508 # Number of bytes of host memory used +host_seconds 318.79 # Real time elapsed on the host +sim_insts 60331162 # Number of instructions simulated +sim_ops 77486236 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7048216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 510792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7044824 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 63936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 680960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1348288 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 63936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743808 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298564 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159248 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558004 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759624 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 65024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 679232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1352768 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 510792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3745216 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298452 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558108 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761032 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14193 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110111 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21067 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512407 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58497 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324641 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39812 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389501 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812451 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764609 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21137 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512414 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324613 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389527 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812473 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764463 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 212488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2930630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 283279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 560886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540201 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66247 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811996 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 78381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 562748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 78381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812573 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764463 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3470783 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 349526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1209014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54670713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446501 # Number of read requests accepted -system.physmem.writeReqs 446412 # Number of write requests accepted -system.physmem.readBursts 13446501 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446412 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860576000 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 27050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 78381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1210918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54671318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13444811 # Number of read requests accepted +system.physmem.writeReqs 446538 # Number of write requests accepted +system.physmem.readBursts 13444811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446538 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860467840 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 2816640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109567680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2811588 # Total written bytes from the system interface side +system.physmem.bytesWritten 2823232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109558976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2817972 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402376 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2365 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835689 # Per bank write bursts -system.physmem.perBankRdBursts::1 835334 # Per bank write bursts -system.physmem.perBankRdBursts::2 835514 # Per bank write bursts -system.physmem.perBankRdBursts::3 835992 # Per bank write bursts -system.physmem.perBankRdBursts::4 837083 # Per bank write bursts -system.physmem.perBankRdBursts::5 837766 # Per bank write bursts -system.physmem.perBankRdBursts::6 837910 # Per bank write bursts -system.physmem.perBankRdBursts::7 839140 # Per bank write bursts -system.physmem.perBankRdBursts::8 840643 # Per bank write bursts -system.physmem.perBankRdBursts::9 843328 # Per bank write bursts -system.physmem.perBankRdBursts::10 843395 # Per bank write bursts -system.physmem.perBankRdBursts::11 843892 # Per bank write bursts -system.physmem.perBankRdBursts::12 845429 # Per bank write bursts -system.physmem.perBankRdBursts::13 846004 # Per bank write bursts -system.physmem.perBankRdBursts::14 844795 # Per bank write bursts -system.physmem.perBankRdBursts::15 844586 # Per bank write bursts -system.physmem.perBankWrBursts::0 2674 # Per bank write bursts -system.physmem.perBankWrBursts::1 2534 # Per bank write bursts -system.physmem.perBankWrBursts::2 2538 # Per bank write bursts -system.physmem.perBankWrBursts::3 3024 # Per bank write bursts -system.physmem.perBankWrBursts::4 3410 # Per bank write bursts -system.physmem.perBankWrBursts::5 3131 # Per bank write bursts -system.physmem.perBankWrBursts::6 2493 # Per bank write bursts -system.physmem.perBankWrBursts::7 2267 # Per bank write bursts -system.physmem.perBankWrBursts::8 2164 # Per bank write bursts +system.physmem.mergedWrBursts 402393 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2368 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835670 # Per bank write bursts +system.physmem.perBankRdBursts::1 835346 # Per bank write bursts +system.physmem.perBankRdBursts::2 835517 # Per bank write bursts +system.physmem.perBankRdBursts::3 836010 # Per bank write bursts +system.physmem.perBankRdBursts::4 837094 # Per bank write bursts +system.physmem.perBankRdBursts::5 837780 # Per bank write bursts +system.physmem.perBankRdBursts::6 837922 # Per bank write bursts +system.physmem.perBankRdBursts::7 839142 # Per bank write bursts +system.physmem.perBankRdBursts::8 840618 # Per bank write bursts +system.physmem.perBankRdBursts::9 843327 # Per bank write bursts +system.physmem.perBankRdBursts::10 843373 # Per bank write bursts +system.physmem.perBankRdBursts::11 843894 # Per bank write bursts +system.physmem.perBankRdBursts::12 845193 # Per bank write bursts +system.physmem.perBankRdBursts::13 844981 # Per bank write bursts +system.physmem.perBankRdBursts::14 844356 # Per bank write bursts +system.physmem.perBankRdBursts::15 844587 # Per bank write bursts +system.physmem.perBankWrBursts::0 2683 # Per bank write bursts +system.physmem.perBankWrBursts::1 2536 # Per bank write bursts +system.physmem.perBankWrBursts::2 2524 # Per bank write bursts +system.physmem.perBankWrBursts::3 3040 # Per bank write bursts +system.physmem.perBankWrBursts::4 3434 # Per bank write bursts +system.physmem.perBankWrBursts::5 3138 # Per bank write bursts +system.physmem.perBankWrBursts::6 2510 # Per bank write bursts +system.physmem.perBankWrBursts::7 2271 # Per bank write bursts +system.physmem.perBankWrBursts::8 2160 # Per bank write bursts system.physmem.perBankWrBursts::9 2378 # Per bank write bursts -system.physmem.perBankWrBursts::10 2328 # Per bank write bursts +system.physmem.perBankWrBursts::10 2319 # Per bank write bursts system.physmem.perBankWrBursts::11 2803 # Per bank write bursts -system.physmem.perBankWrBursts::12 3718 # Per bank write bursts -system.physmem.perBankWrBursts::13 3446 # Per bank write bursts -system.physmem.perBankWrBursts::14 2595 # Per bank write bursts -system.physmem.perBankWrBursts::15 2507 # Per bank write bursts +system.physmem.perBankWrBursts::12 3771 # Per bank write bursts +system.physmem.perBankWrBursts::13 3447 # Per bank write bursts +system.physmem.perBankWrBursts::14 2601 # Per bank write bursts +system.physmem.perBankWrBursts::15 2498 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402816386500 # Total gap between requests +system.physmem.totGap 2402823771000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13410864 # Read request sizes (log2) +system.physmem.readPktSize::3 13409088 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35637 # Read request sizes (log2) +system.physmem.readPktSize::6 35723 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429313 # Write request sizes (log2) +system.physmem.writePktSize::2 429341 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17099 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 877452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 853858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 853065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 937219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 912169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2402802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2330624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3052022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 80661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 76244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 73288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17197 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 877930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 852855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 852810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 941410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 915654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2398641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2321801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3038639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 92226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 80541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 77647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,10 +178,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see @@ -193,27 +193,27 @@ system.physmem.wrQLenPdf::11 93 # Wh system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -242,63 +242,64 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.952353 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.296727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.584191 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8288 0.96% 0.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8846 1.02% 1.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6189 0.71% 2.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 800 0.09% 2.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 916 0.11% 2.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 687 0.08% 2.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7828 0.90% 3.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 865990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.883419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.040735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.863432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8417 0.97% 0.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8847 1.02% 1.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6111 0.71% 2.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 842 0.10% 2.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 894 0.10% 2.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 743 0.09% 2.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7672 0.89% 3.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832235 96.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866032 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2414 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5570.207125 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 258157.496677 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2413 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::1024-1151 832221 96.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 865990 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2416 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5564.893626 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 258050.737776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2415 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2414 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2414 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.231152 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.108696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.979905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.04% 0.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.08% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.04% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 1 0.04% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 1 0.04% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 7 0.29% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 485 20.09% 20.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.62% 21.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 872 36.12% 57.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 845 35.00% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 52 2.15% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 24 0.99% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 26 1.08% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 34 1.41% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.54% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.21% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.25% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.04% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.25% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.29% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.08% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.17% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2414 # Writes before turning the bus around for reads -system.physmem.totQLat 345783645500 # Total ticks spent queuing -system.physmem.totMemAccLat 597905520500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67232500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25715.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2416 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2416 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.258692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.106432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.116221 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 1 0.04% 0.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.08% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.04% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.08% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 5 0.21% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 486 20.12% 20.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.54% 21.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 855 35.39% 56.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 862 35.68% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 56 2.32% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 20 0.83% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.83% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 33 1.37% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 16 0.66% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.25% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.25% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.17% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.29% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.25% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.17% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.17% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2416 # Writes before turning the bus around for reads +system.physmem.totQLat 346456254750 # Total ticks spent queuing +system.physmem.totMemAccLat 598546442250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67224050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25768.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44465.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44518.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 357.95 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s @@ -306,18 +307,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.51 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.43 # Average write queue length when enqueuing -system.physmem.readRowHits 12586631 # Number of row buffer hits during reads -system.physmem.writeRowHits 37847 # Number of row buffer hits during writes +system.physmem.avgRdQLen 8.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 5.37 # Average write queue length when enqueuing +system.physmem.readRowHits 12585053 # Number of row buffer hits during reads +system.physmem.writeRowHits 37880 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.95 # Row buffer hit rate for writes -system.physmem.avgGap 172952.67 # Average gap between requests +system.physmem.writeRowHitRate 85.81 # Row buffer hit rate for writes +system.physmem.avgGap 172972.67 # Average gap between requests system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2167477603250 # Time in different power states -system.physmem.memoryStateTime::REF 80269800000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2167576169750 # Time in different power states +system.physmem.memoryStateTime::REF 80270060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 156101819250 # Time in different power states +system.physmem.memoryStateTime::ACT 156010779000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -331,322 +332,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55667977 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13781620 # Transaction distribution -system.membus.trans_dist::ReadResp 13781620 # Transaction distribution -system.membus.trans_dist::WriteReq 432153 # Transaction distribution -system.membus.trans_dist::WriteResp 432153 # Transaction distribution -system.membus.trans_dist::Writeback 17099 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2365 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2365 # Transaction distribution -system.membus.trans_dist::ReadExReq 28041 # Transaction distribution -system.membus.trans_dist::ReadExResp 28041 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26821728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26821728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28505457 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735662 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5092356 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5828446 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107286912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107286912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113115358 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133817603 # Total data (bytes) +system.membus.throughput 55668579 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13780402 # Transaction distribution +system.membus.trans_dist::ReadResp 13780402 # Transaction distribution +system.membus.trans_dist::WriteReq 432242 # Transaction distribution +system.membus.trans_dist::WriteResp 432242 # Transaction distribution +system.membus.trans_dist::Writeback 17197 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2368 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2368 # Transaction distribution +system.membus.trans_dist::ReadExReq 28083 # Transaction distribution +system.membus.trans_dist::ReadExResp 28083 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 732930 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 952061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1685211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26818176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28503387 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 736825 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5104244 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5841509 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113114213 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133819459 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416874000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 417666500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 199500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14576510500 # Layer occupancy (ticks) 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-system.l2c.tags.warmup_cycle 2375562300000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36845.662788 # Average occupied blocks per requestor +system.l2c.tags.replacements 63255 # number of replacements +system.l2c.tags.tagsinuse 50395.732810 # Cycle average of tags in use +system.l2c.tags.total_refs 1749595 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128654 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.599227 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375537274500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36859.250431 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5231.089770 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3832.891832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 496.025776 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 690.296020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.797358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1694.464698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1598.012760 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562220 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5225.740605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3831.207928 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 514.351835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 694.414886 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.820575 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1674.526375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1584.426715 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562428 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058485 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079738 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058460 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010533 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769016 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65389 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6488 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55889 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997757 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17683113 # Number of tag accesses -system.l2c.tags.data_accesses 17683113 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8690 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468117 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177120 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 129717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18993 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281260 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131724 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291137 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597632 # number of Writeback hits -system.l2c.Writeback_hits::total 597632 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007848 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010596 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025551 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024176 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768978 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65393 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2636 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55911 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997818 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17684075 # Number of tag accesses +system.l2c.tags.data_accesses 17684075 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8753 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3188 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 465928 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1178 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 130375 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18901 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 282805 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 131860 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291106 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597736 # number of Writeback hits +system.l2c.Writeback_hits::total 597736 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 62001 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18409 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33201 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113611 # number of ReadExReq hits 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0.005820 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991753 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988304 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.509196 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.343485 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365679 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117225 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023462 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023462 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64058.310992 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64394.188850 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63013.296340 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63559.280639 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64023.022432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63001.570681 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59891.492036 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61174.798891 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60740.166229 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.464497 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.671572 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59804.455617 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61130.396042 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60683.653578 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -799,52 +800,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58808825 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1019736 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1019735 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432153 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432153 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1508 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80528 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80528 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830481 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419466 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15414 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52803 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3318164 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26553408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37366366 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64027794 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141267007 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100732 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176624753 # Layer occupancy (ticks) +system.toL2Bus.throughput 58812389 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1022771 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1022770 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432242 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432242 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265826 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80908 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80908 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 834992 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2422460 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3325616 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26696960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37444261 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64248813 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141273763 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 102976 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2181217728 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870991697 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1881226404 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845922726 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1849082178 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10050964 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10054967 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31304739 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31351984 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758959 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13773981 # Transaction distribution -system.iobus.trans_dist::ReadResp 13773981 # Transaction distribution -system.iobus.trans_dist::WriteReq 2776 # Transaction distribution -system.iobus.trans_dist::WriteResp 2776 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11410 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758810 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13772718 # Transaction distribution +system.iobus.trans_dist::ReadResp 13772718 # Transaction distribution +system.iobus.trans_dist::WriteReq 2835 # Transaction distribution +system.iobus.trans_dist::WriteResp 2835 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3040 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 717678 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -860,18 +861,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731786 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26821728 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26821728 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27553514 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15374 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 732930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26818176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27551106 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 714003 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -887,18 +888,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735662 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107286912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107286912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108022574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 736825 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108009529 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209343 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7968000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 8145000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1520000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -906,7 +907,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358898000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 359342000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -938,11 +939,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13410864000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13409088000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 729010000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 730095000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33767373000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33780437750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -967,25 +968,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7995700 # DTB read hits -system.cpu0.dtb.read_misses 6195 # DTB read misses -system.cpu0.dtb.write_hits 6594454 # DTB write hits -system.cpu0.dtb.write_misses 1984 # DTB write misses +system.cpu0.dtb.read_hits 7992228 # DTB read hits +system.cpu0.dtb.read_misses 6211 # DTB read misses +system.cpu0.dtb.write_hits 6585208 # DTB write hits +system.cpu0.dtb.write_misses 1983 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5702 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8001895 # DTB read accesses -system.cpu0.dtb.write_accesses 6596438 # DTB write accesses +system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7998439 # DTB read accesses +system.cpu0.dtb.write_accesses 6587191 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14590154 # DTB hits -system.cpu0.dtb.misses 8179 # DTB misses -system.cpu0.dtb.accesses 14598333 # DTB accesses +system.cpu0.dtb.hits 14577436 # DTB hits +system.cpu0.dtb.misses 8194 # DTB misses +system.cpu0.dtb.accesses 14585630 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1007,468 +1008,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32327896 # ITB inst hits -system.cpu0.itb.inst_misses 3449 # ITB inst misses +system.cpu0.itb.inst_hits 32348466 # ITB inst hits +system.cpu0.itb.inst_misses 3468 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2626 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2648 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32331345 # ITB inst accesses -system.cpu0.itb.hits 32327896 # DTB hits -system.cpu0.itb.misses 3449 # DTB misses -system.cpu0.itb.accesses 32331345 # DTB accesses -system.cpu0.numCycles 113683212 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32351934 # ITB inst accesses +system.cpu0.itb.hits 32348466 # DTB hits +system.cpu0.itb.misses 3468 # DTB misses +system.cpu0.itb.accesses 32351934 # DTB accesses +system.cpu0.numCycles 113676157 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31852389 # Number of instructions committed -system.cpu0.committedOps 42022034 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37405417 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1199046 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4246321 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37405417 # number of integer instructions -system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193890675 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39514617 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15257672 # number of memory refs -system.cpu0.num_load_insts 8364380 # Number of load instructions -system.cpu0.num_store_insts 6893292 # Number of store instructions -system.cpu0.num_idle_cycles 110986808.765580 # Number of idle cycles -system.cpu0.num_busy_cycles 2696403.234420 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023719 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976281 # Percentage of idle cycles -system.cpu0.Branches 5614656 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14792 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 26773719 63.60% 63.63% # Class of executed instruction -system.cpu0.op_class::IntMult 49650 0.12% 63.75% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1431 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::MemRead 8364380 19.87% 83.63% # Class of executed instruction -system.cpu0.op_class::MemWrite 6893292 16.37% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31863567 # Number of instructions committed +system.cpu0.committedOps 42010857 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37388293 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses +system.cpu0.num_func_calls 1197302 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4248978 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37388293 # number of integer instructions +system.cpu0.num_fp_insts 5018 # number of float instructions +system.cpu0.num_int_register_reads 193803982 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39520708 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written +system.cpu0.num_mem_refs 15242780 # number of memory refs +system.cpu0.num_load_insts 8359522 # Number of load instructions +system.cpu0.num_store_insts 6883258 # Number of store instructions +system.cpu0.num_idle_cycles 110978931.176812 # Number of idle cycles +system.cpu0.num_busy_cycles 2697225.823188 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023727 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976273 # Percentage of idle cycles +system.cpu0.Branches 5616963 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14526 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 26777156 63.63% 63.66% # Class of executed instruction +system.cpu0.op_class::IntMult 49712 0.12% 63.78% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1435 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::MemRead 8359522 19.86% 83.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 6883258 16.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 42097264 # Class of executed instruction +system.cpu0.op_class::total 42085609 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891512 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602542 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43658005 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892024 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.942635 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8184230000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.829489 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.587272 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.185782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966464 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014819 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017941 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 891568 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602608 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43675041 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892080 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.958660 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8174940250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.966915 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.710732 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.924961 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964779 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015060 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019385 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45465874 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45465874 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31854091 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8059411 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3744503 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43658005 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31854091 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8059411 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3744503 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43658005 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31854091 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8059411 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3744503 # number of overall hits -system.cpu0.icache.overall_hits::total 43658005 # number of overall hits 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13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8069 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3116 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 905 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 48 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.916022 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 64.916667 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20517.213300 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29287.771220 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21070.514646 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20517.213300 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 29287.771220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21070.514646 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7838 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2641 # number of cycles access was blocked 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LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57799752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714080758 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543058359 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5257139117 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714080758 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543058359 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5257139117 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27392049000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579464500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55971513500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1440396400 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339396963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14779793363 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28832445400 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41918861463 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70751306863 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033859 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026666 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014074 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019443 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008026 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050186 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020255 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011505 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011505 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597736 # number of writebacks +system.cpu0.dcache.writebacks::total 597736 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143982 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 143982 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 560780 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 560780 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 407 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 407 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 704762 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 704762 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 704762 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 704762 # number of overall MSHR hits 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StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92719 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184592 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 277311 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92719 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184592 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 277311 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780623750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1700229865 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2480853615 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 933509750 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1853484745 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2786994495 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19304000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38850752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58154752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714133500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3553714610 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5267848110 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714133500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3553714610 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5267848110 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27350994000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28703901500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56054895500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1444132955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13356723550 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14800856505 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28795126955 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42060625050 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70855752005 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033885 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026674 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021438 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019472 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008063 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049685 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043387 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020339 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011528 # mshr miss rate for demand accesses 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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.815668 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11593.778574 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11432.033025 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1502,25 +1503,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096038 # DTB read hits -system.cpu1.dtb.read_misses 2089 # DTB read misses -system.cpu1.dtb.write_hits 1418402 # DTB write hits -system.cpu1.dtb.write_misses 376 # DTB write misses +system.cpu1.dtb.read_hits 2096820 # DTB read hits +system.cpu1.dtb.read_misses 2107 # DTB read misses +system.cpu1.dtb.write_hits 1423125 # DTB write hits +system.cpu1.dtb.write_misses 370 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1770 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098127 # DTB read accesses -system.cpu1.dtb.write_accesses 1418778 # DTB write accesses +system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2098927 # DTB read accesses +system.cpu1.dtb.write_accesses 1423495 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3514440 # DTB hits -system.cpu1.dtb.misses 2465 # DTB misses -system.cpu1.dtb.accesses 3516905 # DTB accesses +system.cpu1.dtb.hits 3519945 # DTB hits +system.cpu1.dtb.misses 2477 # DTB misses +system.cpu1.dtb.accesses 3522422 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1542,96 +1543,96 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8190394 # ITB inst hits -system.cpu1.itb.inst_misses 1200 # ITB inst misses +system.cpu1.itb.inst_hits 8175454 # ITB inst hits +system.cpu1.itb.inst_misses 1196 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8191594 # ITB inst accesses -system.cpu1.itb.hits 8190394 # DTB hits -system.cpu1.itb.misses 1200 # DTB misses -system.cpu1.itb.accesses 8191594 # DTB accesses -system.cpu1.numCycles 584767176 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8176650 # ITB inst accesses +system.cpu1.itb.hits 8175454 # DTB hits +system.cpu1.itb.misses 1196 # DTB misses +system.cpu1.itb.accesses 8176650 # DTB accesses +system.cpu1.numCycles 584791217 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7979697 # Number of instructions committed -system.cpu1.committedOps 10128513 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9101420 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304592 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114093 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9101420 # number of integer instructions -system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 53054873 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9892627 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3681879 # number of memory refs -system.cpu1.num_load_insts 2189240 # Number of load instructions -system.cpu1.num_store_insts 1492639 # Number of store instructions -system.cpu1.num_idle_cycles 548440957.661697 # Number of idle cycles -system.cpu1.num_busy_cycles 36326218.338303 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062121 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937879 # Percentage of idle cycles -system.cpu1.Branches 1446987 # Number of branches fetched -system.cpu1.op_class::No_OpClass 5386 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6616988 64.14% 64.19% # Class of executed instruction -system.cpu1.op_class::IntMult 11601 0.11% 64.31% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::MemRead 2189240 21.22% 85.53% # Class of executed instruction -system.cpu1.op_class::MemWrite 1492639 14.47% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7972563 # Number of instructions committed +system.cpu1.committedOps 10134873 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9111769 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2002 # Number of float alu accesses +system.cpu1.num_func_calls 305506 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114419 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9111769 # number of integer instructions +system.cpu1.num_fp_insts 2002 # number of float instructions +system.cpu1.num_int_register_reads 53111503 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9891567 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1488 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_mem_refs 3688880 # number of memory refs +system.cpu1.num_load_insts 2190803 # Number of load instructions +system.cpu1.num_store_insts 1498077 # Number of store instructions +system.cpu1.num_idle_cycles 549443201.253140 # Number of idle cycles +system.cpu1.num_busy_cycles 35348015.746859 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060446 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939554 # Percentage of idle cycles +system.cpu1.Branches 1447411 # Number of branches fetched +system.cpu1.op_class::No_OpClass 5397 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6618001 64.10% 64.15% # Class of executed instruction +system.cpu1.op_class::IntMult 11557 0.11% 64.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::MemRead 2190803 21.22% 85.49% # Class of executed instruction +system.cpu1.op_class::MemWrite 1498077 14.51% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 10316152 # Class of executed instruction +system.cpu1.op_class::total 10324133 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4788852 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3906949 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223643 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3181584 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2530711 # Number of BTB hits +system.cpu2.branchPred.lookups 4844951 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3958364 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223288 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3209464 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2561917 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.542486 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413887 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21714 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.823827 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 415777 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21493 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1655,25 +1656,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10930564 # DTB read hits -system.cpu2.dtb.read_misses 23215 # DTB read misses -system.cpu2.dtb.write_hits 3350483 # DTB write hits -system.cpu2.dtb.write_misses 6482 # DTB write misses +system.cpu2.dtb.read_hits 10946099 # DTB read hits +system.cpu2.dtb.read_misses 23259 # DTB read misses +system.cpu2.dtb.write_hits 3358425 # DTB write hits +system.cpu2.dtb.write_misses 6569 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 733 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2341 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 761 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 169 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 461 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10953779 # DTB read accesses -system.cpu2.dtb.write_accesses 3356965 # DTB write accesses +system.cpu2.dtb.perms_faults 490 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10969358 # DTB read accesses +system.cpu2.dtb.write_accesses 3364994 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14281047 # DTB hits -system.cpu2.dtb.misses 29697 # DTB misses -system.cpu2.dtb.accesses 14310744 # DTB accesses +system.cpu2.dtb.hits 14304524 # DTB hits +system.cpu2.dtb.misses 29828 # DTB misses +system.cpu2.dtb.accesses 14334352 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1695,328 +1696,329 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4054306 # ITB inst hits -system.cpu2.itb.inst_misses 4589 # ITB inst misses +system.cpu2.itb.inst_hits 4066170 # ITB inst hits +system.cpu2.itb.inst_misses 4558 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1707 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1650 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 958 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4058895 # ITB inst accesses -system.cpu2.itb.hits 4054306 # DTB hits -system.cpu2.itb.misses 4589 # DTB misses -system.cpu2.itb.accesses 4058895 # DTB accesses -system.cpu2.numCycles 88316329 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4070728 # ITB inst accesses +system.cpu2.itb.hits 4066170 # DTB hits +system.cpu2.itb.misses 4558 # DTB misses +system.cpu2.itb.accesses 4070728 # DTB accesses +system.cpu2.numCycles 88357644 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9351504 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32524106 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4788852 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2944598 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6861719 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1761177 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50498 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19190819 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 265 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 860 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33145 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 719724 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 402 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4052907 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289738 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2002 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37419321 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.044533 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431855 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9387256 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32765333 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4844951 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2977694 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6914165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1793026 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51157 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18399919 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 937 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 34522 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 732881 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4064781 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 291170 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36763653 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.071353 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.456601 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30562706 81.68% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385991 1.03% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516133 1.38% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 820285 2.19% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 630351 1.68% 87.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341631 0.91% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1045289 2.79% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 230176 0.62% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2886759 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 29854695 81.21% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 388351 1.06% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 517738 1.41% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 822514 2.24% 85.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 639820 1.74% 87.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344469 0.94% 88.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1061447 2.89% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 231777 0.63% 92.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2902842 7.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37419321 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054224 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368268 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9979534 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19757337 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6196813 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 326068 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1158658 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 609699 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 52950 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36983425 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178083 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1158658 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10528432 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6814826 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11435729 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5959486 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1521262 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34891179 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 96 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 325442 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 887620 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 163 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37432161 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 161024301 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148452649 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3370 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26548024 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10884136 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285664 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261962 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3325772 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6628163 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3904378 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 525369 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 781342 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32207136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505175 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34773283 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55288 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7195240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19128466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148705 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37419321 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.929287 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.589860 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36763653 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054833 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.370826 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9873812 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19124591 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6319657 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 254865 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1189808 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 613364 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53448 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37275302 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179889 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1189808 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10379118 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2802247 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11780210 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6098002 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 4513356 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35160533 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 386 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2869122 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 3154793 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 689173 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 383 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37744497 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 162187083 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 149521715 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3412 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26544575 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11199921 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 286052 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 262435 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 2598030 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6687505 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3927813 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 542106 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 758032 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32441943 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511673 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34839204 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 63540 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7431415 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19915523 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154345 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36763653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.947653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.617979 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24716493 66.05% 66.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3990546 10.66% 76.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2313548 6.18% 82.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974351 5.28% 88.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2779950 7.43% 95.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 967650 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 497474 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144778 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34531 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24294475 66.08% 66.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3786923 10.30% 76.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2217252 6.03% 82.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1918473 5.22% 87.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2844306 7.74% 95.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 967223 2.63% 98.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 535277 1.46% 99.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 160435 0.44% 99.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 39289 0.11% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37419321 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36763653 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19609 1.29% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1392955 91.52% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109452 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19487 1.25% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1415927 90.74% 91.99% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 124952 8.01% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8340 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19803061 56.95% 56.97% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28127 0.08% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 3 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8595 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19842102 56.95% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28105 0.08% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 10 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 57.06% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 57.06% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11414599 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3518761 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11432468 32.81% 89.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3527522 10.13% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34773283 # Type of FU issued -system.cpu2.iq.rate 0.393736 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1522017 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043770 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108565265 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39912731 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28072202 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7477 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4009 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3345 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36282976 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3984 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206198 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34839204 # Type of FU issued +system.cpu2.iq.rate 0.394298 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1560367 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044788 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108088247 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 40390587 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28132113 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7428 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3949 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3288 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36387010 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3966 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 216264 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1536367 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2104 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9509 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 563915 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1592400 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1668 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9845 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 582754 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5287425 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344896 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5289504 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 343573 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1158658 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5187034 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 87972 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32794480 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61964 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6628163 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3904378 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362952 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29501 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2651 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9509 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107755 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89629 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197384 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33857007 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11143266 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 916276 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1189808 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2192287 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 292580 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 33037931 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55534 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6687505 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3927813 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368987 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 60475 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 207427 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9845 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107337 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89487 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196824 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33922204 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11159492 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82169 # number of nop insts executed -system.cpu2.iew.exec_refs 14628489 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3765120 # Number of branches executed -system.cpu2.iew.exec_stores 3485223 # Number of stores executed -system.cpu2.iew.exec_rate 0.383361 # Inst execution rate -system.cpu2.iew.wb_sent 33455826 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28075547 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16112995 # num instructions producing a value -system.cpu2.iew.wb_consumers 29113416 # num instructions consuming a value +system.cpu2.iew.exec_nop 84315 # number of nop insts executed +system.cpu2.iew.exec_refs 14652861 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3774133 # Number of branches executed +system.cpu2.iew.exec_stores 3493369 # Number of stores executed +system.cpu2.iew.exec_rate 0.383919 # Inst execution rate +system.cpu2.iew.wb_sent 33519345 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28135401 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16326972 # num instructions producing a value +system.cpu2.iew.wb_consumers 29693548 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317898 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553456 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.318426 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549849 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7147493 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356470 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171471 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36260461 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700277 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.736744 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7376982 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357328 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170683 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35573653 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713892 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.756913 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27338017 75.39% 75.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4438533 12.24% 87.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1258858 3.47% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 640995 1.77% 92.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 514559 1.42% 94.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318215 0.88% 95.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418287 1.15% 96.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 309870 0.85% 97.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1023127 2.82% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 26733174 75.15% 75.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4358118 12.25% 87.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1232607 3.46% 90.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 662996 1.86% 92.73% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 505200 1.42% 94.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 312825 0.88% 95.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 424269 1.19% 96.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302810 0.85% 97.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1041654 2.93% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36260461 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20554943 # Number of instructions committed -system.cpu2.commit.committedOps 25392373 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35573653 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20550287 # Number of instructions committed +system.cpu2.commit.committedOps 25395761 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8432259 # Number of memory references committed -system.cpu2.commit.loads 5091796 # Number of loads committed -system.cpu2.commit.membars 94283 # Number of memory barriers committed -system.cpu2.commit.branches 3240263 # Number of branches committed -system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22648524 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295510 # Number of function calls committed. +system.cpu2.commit.refs 8440164 # Number of memory references committed +system.cpu2.commit.loads 5095105 # Number of loads committed +system.cpu2.commit.membars 94591 # Number of memory barriers committed +system.cpu2.commit.branches 3237542 # Number of branches committed +system.cpu2.commit.fp_insts 3235 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22655353 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295831 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 16933133 66.69% 66.69% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 26595 0.10% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 386 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5091796 20.05% 86.84% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3340463 13.16% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 16928638 66.66% 66.66% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 26577 0.10% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 382 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5095105 20.06% 86.83% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3345059 13.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 25392373 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1023127 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 25395761 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1041654 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67255841 # The number of ROB reads -system.cpu2.rob.rob_writes 66282532 # The number of ROB writes -system.cpu2.timesIdled 358696 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50897008 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3546076715 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20499567 # Number of Instructions Simulated -system.cpu2.committedOps 25336997 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 4.308205 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.308205 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232115 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232115 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157113831 # number of integer regfile reads -system.cpu2.int_regfile_writes 29893796 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46822 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes -system.cpu2.misc_regfile_reads 67223937 # number of misc regfile reads -system.cpu2.misc_regfile_writes 297064 # number of misc regfile writes +system.cpu2.rob.rob_reads 66778885 # The number of ROB reads +system.cpu2.rob.rob_writes 66779605 # The number of ROB writes +system.cpu2.timesIdled 362907 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51593991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3545947336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20495032 # Number of Instructions Simulated +system.cpu2.committedOps 25340506 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 4.311174 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.311174 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.231955 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.231955 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157422880 # number of integer regfile reads +system.cpu2.int_regfile_writes 29963931 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46839 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45210 # number of floating regfile writes +system.cpu2.misc_regfile_reads 66597785 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297300 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2033,10 +2035,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1535534030000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1536043103750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1536043103750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal Binary files differindex aaf6d88fc..f40477dbc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 789fa7ff8..da5ad247a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -172,6 +172,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -775,6 +776,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=true @@ -1343,9 +1345,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1356,27 +1358,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index f047a9e04..74b77ce44 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 19:10:32 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x6aaf400 0x6aaf400 - 0: system.cpu1.isa: ISA system set to: 0x6aaf400 0x6aaf400 + 0: system.cpu0.isa: ISA system set to: 0x60c5390 0x60c5390 + 0: system.cpu1.isa: ISA system set to: 0x60c5390 0x60c5390 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index bff238873..4b7f3d43e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550603 # Number of seconds simulated -sim_ticks 2550603285500 # Number of ticks simulated -final_tick 2550603285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550237 # Number of seconds simulated +sim_ticks 2550237191000 # Number of ticks simulated +final_tick 2550237191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56179 # Simulator instruction rate (inst/s) -host_op_rate 72287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2375661490 # Simulator tick rate (ticks/s) -host_mem_usage 471120 # Number of bytes of host memory used -host_seconds 1073.64 # Real time elapsed on the host -sim_insts 60315997 # Number of instructions simulated -sim_ops 77609994 # Number of ops (including micro ops) simulated +host_inst_rate 66377 # Simulator instruction rate (inst/s) +host_op_rate 85409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2806608319 # Simulator tick rate (ticks/s) +host_mem_usage 421988 # Number of bytes of host memory used +host_seconds 908.65 # Real time elapsed on the host +sim_insts 60314055 # Number of instructions simulated +sim_ops 77607027 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 487168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5091220 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 310848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4002308 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 310848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785472 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521388 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494684 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801544 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 507520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5298200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 292352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3795584 # Number of bytes read from this memory +system.physmem.bytes_read::total 131007192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 507520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 292352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786240 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494672 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802312 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7612 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 79585 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4857 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 62537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293452 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59148 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380347 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373671 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813166 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47483091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1996085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 121872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1569161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51362340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 121872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 312873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596482 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666641 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47483091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2592566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 121872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2155173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54028981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293452 # Number of read requests accepted -system.physmem.writeReqs 813166 # Number of write requests accepted -system.physmem.readBursts 15293452 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813166 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977025792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1755136 # Total number of bytes read from write queue -system.physmem.bytesWritten 6829888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131004952 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801544 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 27424 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706426 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955870 # Per bank write bursts -system.physmem.perBankRdBursts::1 953353 # Per bank write bursts -system.physmem.perBankRdBursts::2 953267 # Per bank write bursts -system.physmem.perBankRdBursts::3 953402 # Per bank write bursts -system.physmem.perBankRdBursts::4 955744 # Per bank write bursts -system.physmem.perBankRdBursts::5 953745 # Per bank write bursts -system.physmem.perBankRdBursts::6 953482 # Per bank write bursts -system.physmem.perBankRdBursts::7 953247 # Per bank write bursts -system.physmem.perBankRdBursts::8 956258 # Per bank write bursts -system.physmem.perBankRdBursts::9 953771 # Per bank write bursts -system.physmem.perBankRdBursts::10 953551 # Per bank write bursts -system.physmem.perBankRdBursts::11 953111 # Per bank write bursts -system.physmem.perBankRdBursts::12 956206 # Per bank write bursts -system.physmem.perBankRdBursts::13 953857 # Per bank write bursts -system.physmem.perBankRdBursts::14 953612 # Per bank write bursts -system.physmem.perBankRdBursts::15 953552 # Per bank write bursts -system.physmem.perBankWrBursts::0 6609 # Per bank write bursts -system.physmem.perBankWrBursts::1 6381 # Per bank write bursts -system.physmem.perBankWrBursts::2 6537 # Per bank write bursts -system.physmem.perBankWrBursts::3 6560 # Per bank write bursts -system.physmem.perBankWrBursts::4 6488 # Per bank write bursts +system.physmem.num_reads::cpu0.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 82820 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 59306 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59160 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373668 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47489907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2077532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1488326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51370591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586091 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47489907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 199009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2674104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2074417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54037916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293487 # Number of read requests accepted +system.physmem.writeReqs 813178 # Number of write requests accepted +system.physmem.readBursts 15293487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813178 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 977052352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1730816 # Total number of bytes read from write queue +system.physmem.bytesWritten 6829312 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131007192 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6802312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 27044 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706441 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4687 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955866 # Per bank write bursts +system.physmem.perBankRdBursts::1 953274 # Per bank write bursts +system.physmem.perBankRdBursts::2 953247 # Per bank write bursts +system.physmem.perBankRdBursts::3 953514 # Per bank write bursts +system.physmem.perBankRdBursts::4 955750 # Per bank write bursts +system.physmem.perBankRdBursts::5 953800 # Per bank write bursts +system.physmem.perBankRdBursts::6 953588 # Per bank write bursts +system.physmem.perBankRdBursts::7 953504 # Per bank write bursts +system.physmem.perBankRdBursts::8 956261 # Per bank write bursts +system.physmem.perBankRdBursts::9 953859 # Per bank write bursts +system.physmem.perBankRdBursts::10 953506 # Per bank write bursts +system.physmem.perBankRdBursts::11 952990 # Per bank write bursts +system.physmem.perBankRdBursts::12 956201 # Per bank write bursts +system.physmem.perBankRdBursts::13 953861 # Per bank write bursts +system.physmem.perBankRdBursts::14 953718 # Per bank write bursts +system.physmem.perBankRdBursts::15 953504 # Per bank write bursts +system.physmem.perBankWrBursts::0 6593 # Per bank write bursts +system.physmem.perBankWrBursts::1 6395 # Per bank write bursts +system.physmem.perBankWrBursts::2 6535 # Per bank write bursts +system.physmem.perBankWrBursts::3 6562 # Per bank write bursts +system.physmem.perBankWrBursts::4 6485 # Per bank write bursts system.physmem.perBankWrBursts::5 6754 # Per bank write bursts -system.physmem.perBankWrBursts::6 6745 # Per bank write bursts -system.physmem.perBankWrBursts::7 6685 # Per bank write bursts -system.physmem.perBankWrBursts::8 7023 # Per bank write bursts -system.physmem.perBankWrBursts::9 6801 # Per bank write bursts -system.physmem.perBankWrBursts::10 6470 # Per bank write bursts -system.physmem.perBankWrBursts::11 6120 # Per bank write bursts -system.physmem.perBankWrBursts::12 7060 # Per bank write bursts -system.physmem.perBankWrBursts::13 6677 # Per bank write bursts -system.physmem.perBankWrBursts::14 6963 # Per bank write bursts -system.physmem.perBankWrBursts::15 6844 # Per bank write bursts +system.physmem.perBankWrBursts::6 6752 # Per bank write bursts +system.physmem.perBankWrBursts::7 6692 # Per bank write bursts +system.physmem.perBankWrBursts::8 7013 # Per bank write bursts +system.physmem.perBankWrBursts::9 6813 # Per bank write bursts +system.physmem.perBankWrBursts::10 6467 # Per bank write bursts +system.physmem.perBankWrBursts::11 6119 # Per bank write bursts +system.physmem.perBankWrBursts::12 7057 # Per bank write bursts +system.physmem.perBankWrBursts::13 6685 # Per bank write bursts +system.physmem.perBankWrBursts::14 6965 # Per bank write bursts +system.physmem.perBankWrBursts::15 6821 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550602119500 # Total gap between requests +system.physmem.totGap 2550236004000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154598 # Read request sizes (log2) +system.physmem.readPktSize::6 154633 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59148 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1066844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1005139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1068011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1033822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2692544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2602827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3401172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 102949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 92392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59160 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1068642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1003556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1068028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 971433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1034228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3400925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 102170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -225,95 +225,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.187598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 908.669037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 201.227455 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22588 2.23% 2.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20116 1.99% 4.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8785 0.87% 5.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2331 0.23% 5.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2167 0.21% 5.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1761 0.17% 5.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9115 0.90% 6.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 858 0.08% 6.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943241 93.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2514.580135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47785.198367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6044 99.56% 99.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.57% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 6 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1011151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.031391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 908.214038 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 201.586844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22832 2.26% 2.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19987 1.98% 4.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8899 0.88% 5.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2276 0.23% 5.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2117 0.21% 5.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1805 0.18% 5.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9141 0.90% 6.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 764 0.08% 6.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943330 93.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1011151 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2512.992263 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47101.457482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6047 99.54% 99.54% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 7 0.12% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.578158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.392553 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.387042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 4 0.07% 0.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.03% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 7 0.12% 0.28% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6075 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.565103 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.376946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.337614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 6 0.10% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 5 0.08% 0.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.03% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.05% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 4 0.07% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.03% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.05% 0.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.03% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.03% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 4 0.07% 0.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 5 0.08% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 2 0.03% 0.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 3 0.05% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.02% 0.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 12 0.20% 0.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2739 45.12% 46.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.58% 46.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1542 25.40% 72.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1308 21.55% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 93 1.53% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 45 0.74% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 49 0.81% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 58 0.96% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 25 0.41% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.28% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.33% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 16 0.26% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 13 0.21% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.23% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 14 0.23% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 16 0.26% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 10 0.16% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads -system.physmem.totQLat 393355196000 # Total ticks spent queuing -system.physmem.totMemAccLat 679593221000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76330140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25766.70 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2721 44.79% 45.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 38 0.63% 46.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1583 26.06% 72.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1297 21.35% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 91 1.50% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 44 0.72% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 54 0.89% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 48 0.79% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.48% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 18 0.30% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.33% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 17 0.28% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 13 0.21% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 16 0.26% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 12 0.20% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.16% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 8 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads +system.physmem.totQLat 393209260500 # Total ticks spent queuing +system.physmem.totMemAccLat 679455066750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76332215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25756.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44516.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44506.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.51 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.34 # Average write queue length when enqueuing -system.physmem.readRowHits 14270645 # Number of row buffer hits during reads -system.physmem.writeRowHits 91138 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.37 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.37 # Average write queue length when enqueuing +system.physmem.readRowHits 14270960 # Number of row buffer hits during reads +system.physmem.writeRowHits 91040 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.38 # Row buffer hit rate for writes -system.physmem.avgGap 158357.40 # Average gap between requests +system.physmem.writeRowHitRate 85.29 # Row buffer hit rate for writes +system.physmem.avgGap 158334.21 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2202343950500 # Time in different power states -system.physmem.memoryStateTime::REF 85170020000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2202305646000 # Time in different power states +system.physmem.memoryStateTime::REF 85157800000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 263082705750 # Time in different power states +system.physmem.memoryStateTime::ACT 262767276500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -327,283 +328,289 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54969203 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346092 # Transaction distribution -system.membus.trans_dist::ReadResp 16346092 # Transaction distribution +system.membus.throughput 54978267 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346128 # Transaction distribution +system.membus.trans_dist::ReadResp 16346128 # Transaction distribution system.membus.trans_dist::WriteReq 763361 # Transaction distribution system.membus.trans_dist::WriteResp 763361 # Transaction distribution -system.membus.trans_dist::Writeback 59148 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution -system.membus.trans_dist::ReadExReq 131444 # Transaction distribution -system.membus.trans_dist::ReadExResp 131444 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59160 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4687 # Transaction distribution +system.membus.trans_dist::ReadExReq 131439 # Transaction distribution +system.membus.trans_dist::ReadExResp 131439 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885816 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272758 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550302 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550390 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16695968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094102 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19097094 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140204630 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140204630 # Total data (bytes) +system.membus.tot_pkt_size::total 140207622 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140207622 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486938500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487194000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3616000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3622500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17564463000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17516054500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4735162713 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4714051227 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37454635709 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37455331951 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64370 # number of replacements -system.l2c.tags.tagsinuse 51446.531370 # Cycle average of tags in use -system.l2c.tags.total_refs 1904863 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129760 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.679894 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2513258094500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36996.902854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 21.266230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4638.850911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3223.219228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.615555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3561.358912 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2994.317308 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564528 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000324 # Average percentage of cache occupancy +system.l2c.tags.replacements 64405 # number of replacements +system.l2c.tags.tagsinuse 51448.142618 # Cycle average of tags in use +system.l2c.tags.total_refs 1904465 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129797 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.672643 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2540066144500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37002.110374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 24.124150 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4932.290143 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3309.962047 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.942781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3265.462064 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2905.250809 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000368 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070783 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.049182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045690 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785012 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3064 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6835 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55083 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997437 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18932032 # Number of tag accesses -system.l2c.tags.data_accesses 18932032 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32158 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6860 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 505744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 187679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31450 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7231 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 465794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199404 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436320 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 607907 # number of Writeback hits -system.l2c.Writeback_hits::total 607907 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58462 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54465 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112927 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32158 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 505744 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 246141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 465794 # number of demand (read+write) hits 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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61530.156287 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59331.574060 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60610.807088 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89364.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 281000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58891.705069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61528.344756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60247.646673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59701.172833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60664.341591 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -778,46 +797,46 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58427348 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677396 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677395 # Transaction distribution +system.toL2Bus.throughput 58447524 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676676 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676675 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 607907 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2938 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2945 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246147 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246147 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1969203 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796633 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149595 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7953885 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62977408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85532246 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56372 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148820630 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148820630 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 204356 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4962673723 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 608464 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2946 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2964 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246266 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246266 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798454 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7953186 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62935104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85607366 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55020 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148850866 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148850866 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204184 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964883974 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4436346984 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4433375902 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4483051170 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4485758372 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24406904 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24044394 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86367392 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86236537 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48420315 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution +system.iobus.throughput 48427259 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution system.iobus.trans_dist::WriteReq 8177 # Transaction distribution system.iobus.trans_dist::WriteResp 8177 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -839,12 +858,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383060 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660692 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -866,14 +885,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390486 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501014 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501014 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500998 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -919,19 +938,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38146923291 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38148865049 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7527303 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6005482 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 376664 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4812068 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3910560 # Number of BTB hits +system.cpu0.branchPred.lookups 7661485 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6126508 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 381527 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4905065 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3983490 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.265685 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 724420 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38989 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.211768 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 723596 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38982 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -955,25 +974,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25762472 # DTB read hits -system.cpu0.dtb.read_misses 39475 # DTB read misses -system.cpu0.dtb.write_hits 6143291 # DTB write hits -system.cpu0.dtb.write_misses 10324 # DTB write misses +system.cpu0.dtb.read_hits 25785436 # DTB read hits +system.cpu0.dtb.read_misses 39736 # DTB read misses +system.cpu0.dtb.write_hits 6191742 # DTB write hits +system.cpu0.dtb.write_misses 10170 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5580 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1376 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5474 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1453 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 639 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25801947 # DTB read accesses -system.cpu0.dtb.write_accesses 6153615 # DTB write accesses +system.cpu0.dtb.perms_faults 628 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25825172 # DTB read accesses +system.cpu0.dtb.write_accesses 6201912 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31905763 # DTB hits -system.cpu0.dtb.misses 49799 # DTB misses -system.cpu0.dtb.accesses 31955562 # DTB accesses +system.cpu0.dtb.hits 31977178 # DTB hits +system.cpu0.dtb.misses 49906 # DTB misses +system.cpu0.dtb.accesses 32027084 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -995,694 +1014,696 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5893431 # ITB inst hits -system.cpu0.itb.inst_misses 7431 # ITB inst misses +system.cpu0.itb.inst_hits 5958651 # ITB inst hits +system.cpu0.itb.inst_misses 7224 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2617 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2573 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1506 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5900862 # ITB inst accesses -system.cpu0.itb.hits 5893431 # DTB hits -system.cpu0.itb.misses 7431 # DTB misses -system.cpu0.itb.accesses 5900862 # DTB accesses -system.cpu0.numCycles 242264674 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5965875 # ITB inst accesses +system.cpu0.itb.hits 5958651 # DTB hits +system.cpu0.itb.misses 7224 # DTB misses +system.cpu0.itb.accesses 5965875 # DTB accesses +system.cpu0.numCycles 242096947 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15531926 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45587183 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7527303 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4634980 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10285875 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2434733 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 89107 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50171859 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2068 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 54478 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1474048 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5891523 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 366856 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79291736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.723314 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.072188 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15548527 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 46430150 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7661485 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4707086 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10443980 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2504010 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 87505 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47991707 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1669 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1947 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50069 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1492171 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5956718 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 371320 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77361996 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.753757 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.110815 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69012854 87.04% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 680232 0.86% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 874808 1.10% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1172230 1.48% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1090891 1.38% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 557599 0.70% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1295199 1.63% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 379880 0.48% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4228043 5.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66925381 86.51% 86.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 685980 0.89% 87.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 883677 1.14% 88.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1195178 1.54% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1096516 1.42% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 566437 0.73% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1314357 1.70% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 386846 0.50% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4307624 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79291736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031071 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.188171 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16635366 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51194908 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9213198 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 653944 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1592125 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1010665 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90813 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54600074 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 300654 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1592125 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17527482 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20299787 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27625200 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8910460 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3334547 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52031373 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 331 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 485563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2176301 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 182 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53736698 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241285167 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 220106334 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4864 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39390817 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14345881 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 590593 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 539084 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6947132 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10055649 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6962422 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1056834 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1358453 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48348288 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1003135 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62086915 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89013 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9905639 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24691410 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 254686 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79291736 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.783019 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.501466 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77361996 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031646 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.191783 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16313273 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49370536 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9491475 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 529288 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1655237 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1021533 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91523 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 55531280 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 303986 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1655237 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17162522 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7654348 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 28580121 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9244360 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 13063308 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52889125 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1160 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 8605902 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 9933616 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1829408 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 705 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54696180 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 245103090 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 223663577 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5274 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39761499 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14934681 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 590339 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 538925 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5812671 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10214201 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7053988 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1084092 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1355038 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49147671 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1004891 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62507144 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 106564 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10354652 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26208427 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256708 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77361996 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.807983 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.536259 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56790483 71.62% 71.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7331291 9.25% 80.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3517102 4.44% 85.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2900884 3.66% 88.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6182474 7.80% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1488398 1.88% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 785922 0.99% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 230106 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65076 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55228815 71.39% 71.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6921867 8.95% 80.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3371546 4.36% 84.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2828196 3.66% 88.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6343832 8.20% 96.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1429149 1.85% 98.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 903697 1.17% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 264810 0.34% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 70084 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79291736 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77361996 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 31039 0.70% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4198728 94.33% 95.03% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221343 4.97% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 34065 0.76% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4230863 93.99% 94.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 236461 5.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14970 0.02% 0.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29137192 46.93% 46.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47374 0.08% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1226 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.03% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26440432 42.59% 89.62% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6445693 10.38% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14977 0.02% 0.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29471794 47.15% 47.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48326 0.08% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1252 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26467836 42.34% 89.60% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6502932 10.40% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62086915 # Type of FU issued -system.cpu0.iq.rate 0.256277 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4451111 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071692 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208044448 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59266351 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43285904 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10871 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5830 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4924 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66517304 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5752 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316537 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62507144 # Type of FU issued +system.cpu0.iq.rate 0.258191 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4501391 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.072014 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207022163 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60516960 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43741315 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11807 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6284 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5315 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66987291 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6267 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 331575 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2144033 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4052 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15721 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 849604 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2258680 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16640 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 890724 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17082730 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 349385 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17025951 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348422 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1592125 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15682380 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239912 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49471978 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105539 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10055649 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6962422 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 704937 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56286 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4027 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15721 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184221 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145235 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 329456 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61023718 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26110824 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1063197 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1655237 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6199849 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 752551 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50264845 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10214201 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7053988 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 705061 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 147463 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 536075 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16640 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186895 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147787 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 334682 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61435794 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26133192 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1071350 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 120555 # number of nop insts executed -system.cpu0.iew.exec_refs 32498156 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5982225 # Number of branches executed -system.cpu0.iew.exec_stores 6387332 # Number of stores executed -system.cpu0.iew.exec_rate 0.251889 # Inst execution rate -system.cpu0.iew.wb_sent 60528797 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43290828 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23369621 # num instructions producing a value -system.cpu0.iew.wb_consumers 42956226 # num instructions consuming a value +system.cpu0.iew.exec_nop 112283 # number of nop insts executed +system.cpu0.iew.exec_refs 32576038 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6024055 # Number of branches executed +system.cpu0.iew.exec_stores 6442846 # Number of stores executed +system.cpu0.iew.exec_rate 0.253765 # Inst execution rate +system.cpu0.iew.wb_sent 60932314 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43746630 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24175990 # num instructions producing a value +system.cpu0.iew.wb_consumers 44857309 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.178692 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544033 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.180699 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.538953 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9786876 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 748449 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 287258 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77699611 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.504830 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.472024 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10244306 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 748183 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 291383 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75706759 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.522606 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.501619 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63277588 81.44% 81.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7407512 9.53% 90.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1967451 2.53% 93.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1105852 1.42% 94.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 852897 1.10% 96.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 576328 0.74% 96.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 737114 0.95% 97.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 349768 0.45% 98.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1425101 1.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61320530 81.00% 81.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7333121 9.69% 90.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1910409 2.52% 93.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1174950 1.55% 94.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 814971 1.08% 95.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 569506 0.75% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 771340 1.02% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 344904 0.46% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1467028 1.94% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77699611 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30084753 # Number of instructions committed -system.cpu0.commit.committedOps 39225066 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75706759 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30422123 # Number of instructions committed +system.cpu0.commit.committedOps 39564795 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14024434 # Number of memory references committed -system.cpu0.commit.loads 7911616 # Number of loads committed -system.cpu0.commit.membars 209739 # Number of memory barriers committed -system.cpu0.commit.branches 5192960 # Number of branches committed -system.cpu0.commit.fp_insts 4874 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34907078 # Number of committed integer instructions. -system.cpu0.commit.function_calls 509367 # Number of function calls committed. +system.cpu0.commit.refs 14118785 # Number of memory references committed +system.cpu0.commit.loads 7955521 # Number of loads committed +system.cpu0.commit.membars 210845 # Number of memory barriers committed +system.cpu0.commit.branches 5215430 # Number of branches committed +system.cpu0.commit.fp_insts 5270 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35234514 # Number of committed integer instructions. +system.cpu0.commit.function_calls 505825 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 25154804 64.13% 64.13% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 44602 0.11% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.24% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 1226 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.25% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7911616 20.17% 84.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6112818 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25399613 64.20% 64.20% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 45146 0.11% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 1251 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.31% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7955521 20.11% 84.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6163264 15.58% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 39225066 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1425101 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 39564795 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1467028 # number 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317.697202 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 193.874025 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.620502 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.378660 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999163 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 123090455 # The number of ROB reads +system.cpu0.rob.rob_writes 101316686 # The number of ROB writes +system.cpu0.timesIdled 905863 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 164734951 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2248240039 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30347856 # Number of Instructions Simulated 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blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 163 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12553911 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12553911 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5335132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5167503 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10502635 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5335132 # number of demand (read+write) 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accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11999.094435 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12152.176982 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11832.828434 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11999.094435 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643424 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993257 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21526419 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 643936 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.429439 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43468250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.820066 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.173192 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497695 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502291 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 644041 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993361 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21521749 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644553 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.390193 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42479250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.642215 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.351146 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499301 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500686 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101635836 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101635836 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7044250 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6727132 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13771382 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3751595 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3509581 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261176 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116856 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126271 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243127 # number of LoadLockedReq hits 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number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1956432 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1754680 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711112 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5370959618 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6018353236 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11389312854 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84349105443 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 64286693931 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 148635799374 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105098996 # number of LoadLockedReq miss cycles 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miss cycles -system.cpu0.dcache.overall_miss_latency::total 160025112228 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7379776 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7140342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14520118 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5372501 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4851051 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223552 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132401 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119518 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128133 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247651 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12752277 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11991393 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24743670 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12752277 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11991393 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24743670 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045466 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057870 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051565 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.301704 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.276532 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289760 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059532 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046299 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052705 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000039 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000028 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.153418 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.146328 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149982 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.153418 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.146328 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149982 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16007.580986 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15211.386729 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52038.246168 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50174.521862 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14208.327160 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45859.025543 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40067.161629 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43120.528895 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45859.025543 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40067.161629 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43120.528895 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36695 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25289 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3463 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 288 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.596304 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 87.809028 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 101726761 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101726761 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7076892 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6698233 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13775125 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3751457 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3500966 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7252423 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118146 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125300 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243446 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120516 # number of 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MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 704 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 669 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1373 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1700796 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1402246 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3103042 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1700796 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1402246 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3103042 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191404 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 194821 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386225 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 136878 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 112211 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249089 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6707 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5478 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 18 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 328282 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 307032 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635314 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 328282 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 307032 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635314 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2672225710 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2597817092 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5270042802 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6526900100 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4738022235 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11264922335 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 84662502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63153752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147816254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 111499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 111499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 222998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9199125810 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7335839327 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16534965137 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9199125810 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7335839327 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16534965137 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91653477500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90683023500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13720132000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13077337591 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26797469591 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105373609500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103760361091 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209133970591 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025718 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026558 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023337 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024365 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053418 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041675 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000075 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000071 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000073 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025653 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025532 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025783 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025653 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13961.180069 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13334.379210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13645.006931 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47684.069756 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42224.222536 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45224.487372 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12623.006113 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11528.614823 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.001559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12388.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12388.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12388.777778 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28022.023169 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23892.751658 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.445407 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1693,15 +1714,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7300035 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5887077 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345091 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4651296 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3771120 # Number of BTB hits +system.cpu1.branchPred.lookups 7344792 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5924572 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 342317 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4758265 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3794052 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 81.076758 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 673548 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34495 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.736038 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 685317 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35371 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1725,25 +1746,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25450161 # DTB read hits -system.cpu1.dtb.read_misses 36388 # DTB read misses -system.cpu1.dtb.write_hits 5568332 # DTB write hits -system.cpu1.dtb.write_misses 8538 # DTB write misses +system.cpu1.dtb.read_hits 25350014 # DTB read hits +system.cpu1.dtb.read_misses 36246 # DTB read misses +system.cpu1.dtb.write_hits 5533315 # DTB write hits +system.cpu1.dtb.write_misses 8540 # DTB write misses system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2244 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 247 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5471 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1908 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25486549 # DTB read accesses -system.cpu1.dtb.write_accesses 5576870 # DTB write accesses +system.cpu1.dtb.read_accesses 25386260 # DTB read accesses +system.cpu1.dtb.write_accesses 5541855 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31018493 # DTB hits -system.cpu1.dtb.misses 44926 # DTB misses -system.cpu1.dtb.accesses 31063419 # DTB accesses +system.cpu1.dtb.hits 30883329 # DTB hits +system.cpu1.dtb.misses 44786 # DTB misses +system.cpu1.dtb.accesses 30928115 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1765,125 +1786,126 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5679651 # ITB inst hits -system.cpu1.itb.inst_misses 6870 # ITB inst misses +system.cpu1.itb.inst_hits 5683844 # ITB inst hits +system.cpu1.itb.inst_misses 6848 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2692 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2653 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1570 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1514 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5686521 # ITB inst accesses -system.cpu1.itb.hits 5679651 # DTB hits -system.cpu1.itb.misses 6870 # DTB misses -system.cpu1.itb.accesses 5686521 # DTB accesses -system.cpu1.numCycles 236844574 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5690692 # ITB inst accesses +system.cpu1.itb.hits 5683844 # DTB hits +system.cpu1.itb.misses 6848 # DTB misses +system.cpu1.itb.accesses 5690692 # DTB accesses +system.cpu1.numCycles 235812118 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14466322 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45074741 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7300035 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4444668 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9928510 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2284755 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 83810 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49428019 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1865 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 44064 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1232877 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5677454 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 353029 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3058 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76760101 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.724873 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076516 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14488159 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45028124 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7344792 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4479369 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9950354 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2325910 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82893 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 46948697 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1099 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1893 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 45519 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1268155 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 161 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5681743 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 353393 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2950 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74402978 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.748631 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.104884 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66839787 87.08% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 628644 0.82% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 837705 1.09% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1128430 1.47% 90.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1025116 1.34% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 549692 0.72% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1265677 1.65% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 371391 0.48% 94.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4113659 5.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64461074 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 633258 0.85% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 845202 1.14% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1118143 1.50% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1030578 1.39% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 551741 0.74% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1296054 1.74% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 370486 0.50% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4096442 5.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76760101 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030822 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190314 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15575790 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50164874 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8875530 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 651724 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1490012 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 958602 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85804 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53028773 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286820 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1490012 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16419373 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19259514 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27698423 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8639214 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3251470 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50560580 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 221 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 607469 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2007282 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 572 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52946210 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233908561 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213841042 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5698 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39345682 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13600527 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 580708 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 537933 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6505084 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9729570 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6369599 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 877361 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1114434 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47034811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 984793 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60942495 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91566 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9279731 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23349761 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 250555 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76760101 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793935 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.504235 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74402978 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031147 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190949 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15290128 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 48029788 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9010807 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 535995 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1534066 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 962796 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 84486 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53087117 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 281620 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1534066 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16089413 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6996685 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 28422508 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8819964 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12538212 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50579819 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 715 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 8590875 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 9852379 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1395671 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 1301 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52976488 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233969396 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213834273 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5207 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38971918 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14004569 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 583497 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 540607 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 5363476 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9768473 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6353478 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 903299 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1144541 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47001226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 985413 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60595640 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 98989 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9593116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24473464 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 250944 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74402978 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.814425 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.533021 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54532875 71.04% 71.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7326090 9.54% 80.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3469207 4.52% 85.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2884980 3.76% 88.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6118042 7.97% 96.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1370862 1.79% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 772587 1.01% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 222613 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62845 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 52794785 70.96% 70.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6823804 9.17% 80.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3272663 4.40% 84.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2786608 3.75% 88.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6272134 8.43% 96.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1319081 1.77% 98.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 820611 1.10% 99.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 247257 0.33% 99.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 66035 0.09% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76760101 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74402978 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29035 0.66% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29526 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available @@ -1911,182 +1933,182 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4177111 94.84% 95.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4196905 94.38% 95.05% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 220217 4.95% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13548 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28887832 47.40% 47.42% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46127 0.08% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 887 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26105748 42.84% 90.34% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5888317 9.66% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13541 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28679065 47.33% 47.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45344 0.07% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 858 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26009717 42.92% 90.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5847084 9.65% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60942495 # Type of FU issued -system.cpu1.iq.rate 0.257310 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4404233 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072269 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203173539 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57307144 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42269826 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12116 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6726 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5381 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65326800 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6380 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 306796 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60595640 # Type of FU issued +system.cpu1.iq.rate 0.256966 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4446652 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.073382 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200172970 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57588554 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41991709 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11520 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6240 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4992 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65022566 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6185 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 323560 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1984154 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3003 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15089 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 749009 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2067890 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2468 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15600 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 783792 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17027364 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 331342 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16950409 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331839 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1490012 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14823463 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 222107 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48121220 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96425 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9729570 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6369599 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 709638 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 48371 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4239 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15089 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167591 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133565 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 301156 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59912848 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25789830 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1029647 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1534066 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5578937 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 735039 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48101549 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 89840 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9768473 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6353478 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 710230 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 138266 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 531900 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15600 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 167974 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 132221 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 300195 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59563474 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25690610 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1032166 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 101616 # number of nop insts executed -system.cpu1.iew.exec_refs 31626536 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5854246 # Number of branches executed -system.cpu1.iew.exec_stores 5836706 # Number of stores executed -system.cpu1.iew.exec_rate 0.252963 # Inst execution rate -system.cpu1.iew.wb_sent 59450905 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42275207 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23556720 # num instructions producing a value -system.cpu1.iew.wb_consumers 42880647 # num instructions consuming a value +system.cpu1.iew.exec_nop 114910 # number of nop insts executed +system.cpu1.iew.exec_refs 31485549 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5840798 # Number of branches executed +system.cpu1.iew.exec_stores 5794939 # Number of stores executed +system.cpu1.iew.exec_rate 0.252589 # Inst execution rate +system.cpu1.iew.wb_sent 59096440 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41996701 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23719594 # num instructions producing a value +system.cpu1.iew.wb_consumers 43668575 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178493 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549356 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178094 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.543173 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9147109 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 734238 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260548 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75270089 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.511960 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.483838 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9469311 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 734469 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259123 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 72868911 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.524128 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.502288 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60996835 81.04% 81.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7463530 9.92% 90.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1923766 2.56% 93.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1066165 1.42% 94.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 822611 1.09% 96.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 493470 0.66% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 696092 0.92% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 369554 0.49% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1438066 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 58802570 80.70% 80.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7335717 10.07% 90.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1834357 2.52% 93.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1110131 1.52% 94.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 806352 1.11% 95.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 478738 0.66% 96.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 708592 0.97% 97.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 352493 0.48% 98.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1439961 1.98% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75270089 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30381625 # Number of instructions committed -system.cpu1.commit.committedOps 38535309 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 72868911 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30042313 # Number of instructions committed +system.cpu1.commit.committedOps 38192613 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13366006 # Number of memory references committed -system.cpu1.commit.loads 7745416 # Number of loads committed -system.cpu1.commit.membars 193947 # Number of memory barriers committed -system.cpu1.commit.branches 5114433 # Number of branches committed -system.cpu1.commit.fp_insts 5338 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34292499 # Number of committed integer instructions. -system.cpu1.commit.function_calls 482077 # Number of function calls committed. +system.cpu1.commit.refs 13270269 # Number of memory references committed +system.cpu1.commit.loads 7700583 # Number of loads committed +system.cpu1.commit.membars 192827 # Number of memory barriers committed +system.cpu1.commit.branches 5091642 # Number of branches committed +system.cpu1.commit.fp_insts 4942 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33962282 # Number of committed integer instructions. +system.cpu1.commit.function_calls 485556 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 25125071 65.20% 65.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 43345 0.11% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 887 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 7745416 20.10% 85.41% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 5620590 14.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 24878693 65.14% 65.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 42793 0.11% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 858 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.25% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 7700583 20.16% 85.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 5569686 14.58% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 38535309 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1438066 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 38192613 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1439961 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120626402 # The number of ROB reads -system.cpu1.rob.rob_writes 96898257 # The number of ROB writes -system.cpu1.timesIdled 866184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160084473 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2317121408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30313431 # Number of Instructions Simulated -system.cpu1.committedOps 38467115 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.813189 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.813189 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127989 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127989 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271901021 # number of integer regfile reads -system.cpu1.int_regfile_writes 43646883 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45279 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42402 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133121444 # number of misc regfile reads -system.cpu1.misc_regfile_writes 593543 # number of misc regfile writes +system.cpu1.rob.rob_reads 118199712 # The number of ROB reads +system.cpu1.rob.rob_writes 96901530 # The number of ROB writes +system.cpu1.timesIdled 866503 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 161409140 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2317329341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29966199 # Number of Instructions Simulated +system.cpu1.committedOps 38116499 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 7.869270 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.869270 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127077 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127077 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 270334360 # number of integer regfile reads +system.cpu1.int_regfile_writes 43344614 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45048 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42280 # number of floating regfile writes +system.cpu1.misc_regfile_reads 130449609 # number of misc regfile reads +system.cpu1.misc_regfile_writes 594503 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2103,17 +2125,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1734475259291 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1734330533049 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83062 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal Binary files differindex 973d0288c..46f8f01b2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal |