diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
6 files changed, 9643 insertions, 6862 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 0b387654e..bab672da1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533116 # Number of seconds simulated -sim_ticks 2533115780500 # Number of ticks simulated -final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534279 # Number of seconds simulated +sim_ticks 2534279149500 # Number of ticks simulated +final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55678 # Simulator instruction rate (inst/s) -host_op_rate 71642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2338649550 # Simulator tick rate (ticks/s) -host_mem_usage 398880 # Number of bytes of host memory used -host_seconds 1083.15 # Real time elapsed on the host -sim_insts 60307726 # Number of instructions simulated -sim_ops 77599286 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +host_inst_rate 43780 # Simulator instruction rate (inst/s) +host_op_rate 56332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1839722930 # Simulator tick rate (ticks/s) +host_mem_usage 400528 # Number of bytes of host memory used +host_seconds 1377.53 # Real time elapsed on the host +sim_insts 60307893 # Number of instructions simulated +sim_ops 77599512 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory +system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096806 # Total number of read requests seen -system.physmem.writeReqs 813108 # Total number of write requests seen -system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195584 # Total number of bytes read from memory -system.physmem.bytesWritten 52038912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15098054 # Total number of read requests seen +system.physmem.writeReqs 813133 # Total number of write requests seen +system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966275456 # Total number of bytes read from memory +system.physmem.bytesWritten 52040512 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533114676500 # Total gap between requests +system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534279100000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes +system.physmem.readPktSize::3 14943424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154562 # Categorize read packet sizes +system.physmem.readPktSize::6 154594 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59090 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59115 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -139,59 +139,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see -system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482470000 # Total cycles spent in databus access -system.physmem.totBankLat 16917518750 # Total cycles spent in bank access -system.physmem.avgQLat 26047.39 # Average queueing delay per request -system.physmem.avgBankLat 1120.63 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation +system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests +system.physmem.totBusLat 75488575000 # Total cycles spent in databus access +system.physmem.totBankLat 15730536250 # Total cycles spent in bank access +system.physmem.avgQLat 23521.25 # Average queueing delay per request +system.physmem.avgBankLat 1041.92 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.02 # Average memory access latency -system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 29563.16 # Average memory access latency +system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.11 # Average write queue length over time -system.physmem.readRowHits 15020181 # Number of row buffer hits during reads -system.physmem.writeRowHits 793022 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159216.11 # Average gap between requests +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 11.71 # Average write queue length over time +system.physmem.readRowHits 15070837 # Number of row buffer hits during reads +system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes +system.physmem.avgGap 159276.56 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -204,43 +471,258 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54705448 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16150672 # Transaction distribution +system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.trans_dist::WriteReq 763336 # Transaction distribution +system.membus.trans_dist::WriteResp 763336 # Transaction distribution +system.membus.trans_dist::Writeback 59115 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution +system.membus.trans_dist::ReadExReq 131424 # Transaction distribution +system.membus.trans_dist::ReadExResp 131424 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14672817 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits +system.iobus.throughput 48115298 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution +system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.trans_dist::WriteReq 8158 # Transaction distribution +system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.branchPred.lookups 14673159 # Number of BP lookups +system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987449 # DTB read hits -system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227758 # DTB write hits +system.cpu.checker.dtb.read_hits 14987453 # DTB read hits +system.cpu.checker.dtb.read_misses 7307 # DTB read misses +system.cpu.checker.dtb.write_hits 11227781 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994751 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229947 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994760 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229970 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215207 # DTB hits -system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224698 # DTB accesses -system.cpu.checker.itb.inst_hits 61481725 # ITB inst hits +system.cpu.checker.dtb.hits 26215234 # DTB hits +system.cpu.checker.dtb.misses 9496 # DTB misses +system.cpu.checker.dtb.accesses 26224730 # DTB accesses +system.cpu.checker.itb.inst_hits 61481893 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -257,36 +739,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486196 # ITB inst accesses -system.cpu.checker.itb.hits 61481725 # DTB hits +system.cpu.checker.itb.inst_accesses 61486364 # ITB inst accesses +system.cpu.checker.itb.hits 61481893 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486196 # DTB accesses -system.cpu.checker.numCycles 77885092 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486364 # DTB accesses +system.cpu.checker.numCycles 77885319 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51400888 # DTB read hits -system.cpu.dtb.read_misses 64225 # DTB read misses -system.cpu.dtb.write_hits 11700104 # DTB write hits -system.cpu.dtb.write_misses 15848 # DTB write misses +system.cpu.dtb.read_hits 51397173 # DTB read hits +system.cpu.dtb.read_misses 63986 # DTB read misses +system.cpu.dtb.write_hits 11699533 # DTB write hits +system.cpu.dtb.write_misses 15890 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465113 # DTB read accesses -system.cpu.dtb.write_accesses 11715952 # DTB write accesses +system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51461159 # DTB read accesses +system.cpu.dtb.write_accesses 11715423 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100992 # DTB hits -system.cpu.dtb.misses 80073 # DTB misses -system.cpu.dtb.accesses 63181065 # DTB accesses -system.cpu.itb.inst_hits 12331220 # ITB inst hits -system.cpu.itb.inst_misses 11422 # ITB inst misses +system.cpu.dtb.hits 63096706 # DTB hits +system.cpu.dtb.misses 79876 # DTB misses +system.cpu.dtb.accesses 63176582 # DTB accesses +system.cpu.itb.inst_hits 12260245 # ITB inst hits +system.cpu.itb.inst_misses 11468 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,113 +777,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4954 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4980 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12342642 # ITB inst accesses -system.cpu.itb.hits 12331220 # DTB hits -system.cpu.itb.misses 11422 # DTB misses -system.cpu.itb.accesses 12342642 # DTB accesses -system.cpu.numCycles 471822965 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12271713 # ITB inst accesses +system.cpu.itb.hits 12260245 # DTB hits +system.cpu.itb.misses 11468 # DTB misses +system.cpu.itb.accesses 12271713 # DTB accesses +system.cpu.numCycles 475189978 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -430,383 +912,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued -system.cpu.iq.rate 0.263501 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued +system.cpu.iq.rate 0.261620 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221132 # number of nop insts executed -system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed -system.cpu.iew.exec_branches 11557425 # Number of branches executed -system.cpu.iew.exec_stores 12211932 # Number of stores executed -system.cpu.iew.exec_rate 0.257596 # Inst execution rate -system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47248258 # num instructions producing a value -system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value +system.cpu.iew.exec_nop 221659 # number of nop insts executed +system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed +system.cpu.iew.exec_branches 11560329 # Number of branches executed +system.cpu.iew.exec_stores 12210910 # Number of stores executed +system.cpu.iew.exec_rate 0.255996 # Inst execution rate +system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268053 # num instructions producing a value +system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458107 # Number of instructions committed -system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458274 # Number of instructions committed +system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386657 # Number of memory references committed -system.cpu.commit.loads 15654563 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961339 # Number of branches committed +system.cpu.commit.refs 27386690 # Number of memory references committed +system.cpu.commit.loads 15654575 # Number of loads committed +system.cpu.commit.membars 403596 # Number of memory barriers committed +system.cpu.commit.branches 9961373 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. +system.cpu.commit.function_calls 991268 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242323943 # The number of ROB reads -system.cpu.rob.rob_writes 202004834 # The number of ROB writes -system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307726 # Number of Instructions Simulated -system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated -system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550297303 # number of integer regfile reads -system.cpu.int_regfile_writes 88455601 # number of integer regfile writes -system.cpu.fp_regfile_reads 8347 # number of floating regfile reads -system.cpu.fp_regfile_writes 2910 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads -system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979954 # number of replacements -system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use -system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits -system.cpu.icache.overall_hits::total 11267650 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses -system.cpu.icache.overall_misses::total 1060047 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 243879966 # The number of ROB reads +system.cpu.rob.rob_writes 201882555 # The number of ROB writes +system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307893 # Number of Instructions Simulated +system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated +system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550704703 # number of integer regfile reads +system.cpu.int_regfile_writes 88578313 # number of integer regfile writes +system.cpu.fp_regfile_reads 8302 # number of floating regfile reads +system.cpu.fp_regfile_writes 2882 # number of floating regfile writes +system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads +system.cpu.misc_regfile_writes 831896 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 980157 # number of replacements +system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use +system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits +system.cpu.icache.overall_hits::total 11196212 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses +system.cpu.icache.overall_misses::total 1060409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79541 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79541 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79541 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79541 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79541 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79541 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980506 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980506 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980506 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980506 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980506 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980506 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11382269996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11382269996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11382269996 # 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mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079537 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079537 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.567409 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.567409 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79698 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 755022750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8056699254 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8815309004 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 7078250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166940694000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166947772250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26398880620 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26398880620 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7078250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193339574620 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193346652870 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026822 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016006 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984449 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984449 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541265 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541265 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092654 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61214.751905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.118744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61930.328272 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.343407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.343407 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38253.282311 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38253.282311 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55471.523768 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55471.523768 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +1442,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643450 # number of replacements -system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21511687 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643962 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.405212 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13758946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13758946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259114 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259114 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018060 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018060 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018060 # number of overall hits -system.cpu.dcache.overall_hits::total 21018060 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736156 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736156 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963249 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963249 # number of WriteReq misses +system.cpu.dcache.replacements 643353 # number of replacements +system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use +system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21012027 # number of overall hits +system.cpu.dcache.overall_hits::total 21012027 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963942 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963942 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 13539 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 13539 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699405 # number of overall misses -system.cpu.dcache.overall_misses::total 3699405 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9739284500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9739284500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104713593229 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104713593229 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114452877729 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114452877729 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114452877729 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114452877729 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14495102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14495102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701440 # number of overall misses +system.cpu.dcache.overall_misses::total 3701440 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10068067500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10068067500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 132595635732 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 132595635732 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 183801000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 183801000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 231000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 231000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 142663703232 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 142663703232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 142663703232 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 142663703232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256393 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256393 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713467 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713467 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713467 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713467 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15400 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32274 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26462 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 287 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.238908 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.202091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks -system.cpu.dcache.writebacks::total 607758 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks +system.cpu.dcache.writebacks::total 607669 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,16 +1618,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 960d43f01..7f7f9360b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102954 # Number of seconds simulated -sim_ticks 1102954033500 # Number of ticks simulated -final_tick 1102954033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.613797 # Number of seconds simulated +sim_ticks 2613796876500 # Number of ticks simulated +final_tick 2613796876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66183 # Simulator instruction rate (inst/s) -host_op_rate 85190 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1185337549 # Simulator tick rate (ticks/s) -host_mem_usage 402972 # Number of bytes of host memory used -host_seconds 930.50 # Real time elapsed on the host -sim_insts 61582952 # Number of instructions simulated -sim_ops 79269552 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +host_inst_rate 54493 # Simulator instruction rate (inst/s) +host_op_rate 70162 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2268463215 # Simulator tick rate (ticks/s) +host_mem_usage 404628 # Number of bytes of host memory used +host_seconds 1152.23 # Real time elapsed on the host +sim_insts 62788171 # Number of instructions simulated +sim_ops 80843130 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 410112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4380532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 404608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226032 # Number of bytes read from this memory -system.physmem.bytes_read::total 59181988 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 410112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 404608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4260416 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4352820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 426432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5278640 # Number of bytes read from this memory +system.physmem.bytes_read::total 131565412 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4275200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7287760 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6322 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81683 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257809 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66569 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82505 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302272 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66800 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823405 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44207449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3971636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 366840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4738214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53657710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 366840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3862732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6607492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3862732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44207449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3987049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 366840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7467561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60265202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257809 # Total number of read requests seen -system.physmem.writeReqs 823405 # Total number of write requests seen -system.physmem.cpureqs 242034 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400499776 # Total number of bytes read from memory -system.physmem.bytesWritten 52697920 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59181988 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7287760 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12609 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391210 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391533 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391266 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51229 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51667 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52037 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51503 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51884 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51249 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51891 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824084 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46335096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1665325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2019530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50334979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163147 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1635628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6504 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1152399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2794531 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1635628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46335096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1671828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3171928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53129510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302272 # Total number of read requests seen +system.physmem.writeReqs 824084 # Total number of write requests seen +system.physmem.cpureqs 244248 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979345408 # Total number of bytes read from memory +system.physmem.bytesWritten 52741376 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131565412 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7304336 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 446 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14097 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956336 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 957144 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 956165 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955908 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956251 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 956256 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 52171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 52441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51720 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 52086 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51540 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51490 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51756 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51508 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32620 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102952897500 # Total gap between requests +system.physmem.numWrRetry 32582 # Number of times wr buffer was full causing retry +system.physmem.totGap 2613795718500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 6094848 # Categorize read packet sizes +system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162856 # Categorize read packet sizes +system.physmem.readPktSize::6 163351 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::2 757284 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66569 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 15214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66800 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1071823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1000587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1004460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3729147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2791599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2788638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2744704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,59 +156,350 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32633 # What write queue length does an incoming req see -system.physmem.totQLat 199184958750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239005190000 # Sum of mem lat for all requests -system.physmem.totBusLat 31288700000 # Total cycles spent in databus access -system.physmem.totBankLat 8531531250 # Total cycles spent in bank access -system.physmem.avgQLat 31830.17 # Average queueing delay per request -system.physmem.avgBankLat 1363.36 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32605 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48021 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 21491.760022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1412.636943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31347.507834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 10706 22.29% 22.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 4255 8.86% 31.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2654 5.53% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 2034 4.24% 40.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1364 2.84% 43.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1232 2.57% 46.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 971 2.02% 48.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 916 1.91% 50.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 629 1.31% 51.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 621 1.29% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 497 1.03% 53.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 447 0.93% 54.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 308 0.64% 55.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 288 0.60% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 206 0.43% 56.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 291 0.61% 57.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 124 0.26% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 166 0.35% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 102 0.21% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 142 0.30% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 76 0.16% 58.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 430 0.90% 59.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 2116 4.41% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 511 1.06% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 96 0.20% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 187 0.39% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 61 0.13% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 129 0.27% 65.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 42 0.09% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 82 0.17% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 32 0.07% 66.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 81 0.17% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 30 0.06% 66.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 40 0.08% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 20 0.04% 66.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 38 0.08% 66.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 8 0.02% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 24 0.05% 66.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 13 0.03% 66.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 21 0.04% 66.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 4 0.01% 66.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 15 0.03% 66.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 7 0.01% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 25 0.05% 66.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 10 0.02% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 14 0.03% 66.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 5 0.01% 66.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 16 0.03% 66.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 3 0.01% 66.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 10 0.02% 66.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 6 0.01% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 12 0.02% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 3 0.01% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 12 0.02% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 7 0.01% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 8 0.02% 66.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 5 0.01% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 6 0.01% 66.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 4 0.01% 66.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 10 0.02% 67.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 8 0.02% 67.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 9 0.02% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 7 0.01% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 36 0.07% 67.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 3 0.01% 67.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 8 0.02% 67.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 3 0.01% 67.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 8 0.02% 67.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 1 0.00% 67.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 7 0.01% 67.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 1 0.00% 67.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 5 0.01% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 4 0.01% 67.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 2 0.00% 67.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 3 0.01% 67.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5087 3 0.01% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 10 0.02% 67.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 3 0.01% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 3 0.01% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 2 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 1 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 2 0.00% 67.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 3 0.01% 67.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 4 0.01% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 2 0.00% 67.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 5 0.01% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 2 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 67.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 7 0.01% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 4 0.01% 67.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 2 0.00% 67.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 2 0.00% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 1 0.00% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 67.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 1 0.00% 67.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 2 0.00% 67.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 13 0.03% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 6 0.01% 67.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 1 0.00% 67.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 3 0.01% 67.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 5 0.01% 67.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7263 3 0.01% 67.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 2 0.00% 67.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 6 0.01% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 4 0.01% 67.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 67.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 4 0.01% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 67.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 6 0.01% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 67.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 6 0.01% 67.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 67.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 320 0.67% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 2 0.00% 68.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 3 0.01% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 2 0.00% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9439 1 0.00% 68.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 3 0.01% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9759 1 0.00% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9920-9951 1 0.00% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 16 0.03% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10463 1 0.00% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10783 1 0.00% 68.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 4 0.01% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11359 1 0.00% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12895 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12959 1 0.00% 68.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13855 1 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14111 1 0.00% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 1 0.00% 68.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 2 0.00% 68.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14879 2 0.00% 68.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 2 0.00% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15455 1 0.00% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16159 2 0.00% 68.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 68.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 1 0.00% 68.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 2 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 1 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 1 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 1 0.00% 68.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17823 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17887 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 1 0.00% 68.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19072-19103 1 0.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 1 0.00% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 3 0.01% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19999 1 0.00% 68.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 1 0.00% 68.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 15 0.03% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20608-20639 1 0.00% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 4 0.01% 68.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22303 2 0.00% 68.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 1 0.00% 68.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 3 0.01% 68.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 3 0.01% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23391 1 0.00% 68.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 3 0.01% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23872-23903 1 0.00% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 2 0.00% 68.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 1 0.00% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 3 0.01% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24863 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25119 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 1 0.00% 68.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25951 1 0.00% 68.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26143 2 0.00% 68.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 2 0.00% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 2 0.00% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27167 1 0.00% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27423 2 0.00% 68.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27615 1 0.00% 68.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 3 0.01% 68.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 2 0.00% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 4 0.01% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 2 0.00% 68.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 68.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 2 0.00% 68.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 7 0.01% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31519 1 0.00% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 3 0.01% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 3 0.01% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 3 0.01% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 2 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 1 0.00% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 55 0.11% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-34015 1 0.00% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34079 1 0.00% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 2 0.00% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35359 1 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 1 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35999 1 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36127 2 0.00% 68.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36511 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36639 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38175 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39199 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39263 1 0.00% 68.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39647 1 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40384-40415 1 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41247 2 0.00% 68.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 2 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42271 1 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42719 1 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42783 1 0.00% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43039 1 0.00% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44063 3 0.01% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44447 1 0.00% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44703 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46623 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46943 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-47007 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 68.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49439 2 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50719 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50911 1 0.00% 68.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 2 0.00% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 2 0.00% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52608-52639 1 0.00% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54784-54815 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55327 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55616-55647 1 0.00% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56095 1 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57088-57119 2 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58143 1 0.00% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59584-59615 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59648-59679 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60447 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61215 1 0.00% 68.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61568-61599 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61952-61983 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62976-63007 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64064-64095 1 0.00% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64543 1 0.00% 68.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65055 25 0.05% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65119 6 0.01% 68.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 7 0.01% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 19 0.04% 68.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65439 7 0.01% 68.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 18 0.04% 68.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14562 30.32% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::97536-97567 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::103680-103711 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130207 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130655 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130688-130719 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 321 0.67% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131328-131359 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::140032-140063 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::162560-162591 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::182528-182559 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48021 # Bytes accessed per row activation +system.physmem.totQLat 359781455750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 452374882000 # Sum of mem lat for all requests +system.physmem.totBusLat 76509130000 # Total cycles spent in databus access +system.physmem.totBankLat 16084296250 # Total cycles spent in bank access +system.physmem.avgQLat 23512.32 # Average queueing delay per request +system.physmem.avgBankLat 1051.14 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38193.53 # Average memory access latency -system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29563.46 # Average memory access latency +system.physmem.avgRdBW 374.68 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.18 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.79 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.07 # Average write queue length over time -system.physmem.readRowHits 6213915 # Number of row buffer hits during reads -system.physmem.writeRowHits 799980 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.16 # Row buffer hit rate for writes -system.physmem.avgGap 155757.60 # Average gap between requests +system.physmem.busUtil 3.08 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 13.40 # Average write queue length over time +system.physmem.readRowHits 15272830 # Number of row buffer hits during reads +system.physmem.writeRowHits 805042 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.69 # Row buffer hit rate for writes +system.physmem.avgGap 162082.23 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -218,246 +509,307 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72561 # number of replacements -system.l2c.tagsinuse 53740.730134 # Cycle average of tags in use -system.l2c.total_refs 1839807 # Total number of references to valid blocks. -system.l2c.sampled_refs 137757 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.355452 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54057191 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352590 # Transaction distribution +system.membus.trans_dist::ReadResp 16352590 # Transaction distribution +system.membus.trans_dist::WriteReq 769166 # Transaction distribution +system.membus.trans_dist::WriteResp 769166 # Transaction distribution +system.membus.trans_dist::Writeback 66800 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35679 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18283 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14097 # Transaction distribution +system.membus.trans_dist::ReadExReq 138270 # Transaction distribution +system.membus.trans_dist::ReadExResp 137887 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4376896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32254354 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34654528 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17759220 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20183988 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 138869748 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 141294516 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141294516 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1493240500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17657749750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 11792000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 1805500 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4833822840 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34180950731 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.l2c.replacements 73069 # number of replacements +system.l2c.tagsinuse 53059.477869 # Cycle average of tags in use +system.l2c.total_refs 1873536 # Total number of references to valid blocks. +system.l2c.sampled_refs 138222 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.554543 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39373.368087 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826392 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.258184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4017.777159 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2831.337785 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 9.908379 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3708.426786 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3795.827361 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600790 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061306 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043203 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000151 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056586 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.057920 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820018 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386080 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166672 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4930 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589304 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198131 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1401635 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581048 # number of Writeback hits -system.l2c.Writeback_hits::total 581048 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1122 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 742 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1864 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 337 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48001 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58894 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106895 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21639 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386080 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214673 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4930 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 257025 # number of demand (read+write) hits -system.l2c.demand_hits::total 1508530 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21639 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4056 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386080 # number of overall hits -system.l2c.overall_hits::cpu0.data 214673 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30823 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097105 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097105 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61102.112440 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66724.991783 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63327.411493 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.099965 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.024613 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.503682 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.908740 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.811644 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.006608 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54663.358211 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58809.379683 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56945.687406 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -648,38 +1000,247 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5994746 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4572445 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294986 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3765254 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2911375 # Number of BTB hits +system.toL2Bus.throughput 58542991 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2739841 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2739840 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769166 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769166 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 34832 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53489 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259511 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259511 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 800088 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073172 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13793 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 57051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1229933 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4820895 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 15468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 74350 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 8084750 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25585472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34695904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 18508 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 92124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 39339008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 48266196 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 131012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148151136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148151136 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4868352 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4921338984 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1802175919 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1506283904 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 9191448 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 34164696 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 2769642515 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 3249270250 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 9767440 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 41898883 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 47250451 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322888 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322888 # Transaction distribution +system.iobus.trans_dist::WriteReq 8066 # Transaction distribution +system.iobus.trans_dist::WriteResp 8066 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384276 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32661908 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392552 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123503080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503080 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 4430000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376210000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu0.branchPred.lookups 6073314 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4627623 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295826 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3795187 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2949225 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.322141 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 671631 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28577 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.709610 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 683153 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28183 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8900432 # DTB read hits -system.cpu0.dtb.read_misses 28720 # DTB read misses -system.cpu0.dtb.write_hits 5136537 # DTB write hits -system.cpu0.dtb.write_misses 5640 # DTB write misses +system.cpu0.dtb.read_hits 8970256 # DTB read hits +system.cpu0.dtb.read_misses 29375 # DTB read misses +system.cpu0.dtb.write_hits 5214738 # DTB write hits +system.cpu0.dtb.write_misses 5731 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1815 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1027 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8929152 # DTB read accesses -system.cpu0.dtb.write_accesses 5142177 # DTB write accesses +system.cpu0.dtb.perms_faults 591 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8999631 # DTB read accesses +system.cpu0.dtb.write_accesses 5220469 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14036969 # DTB hits -system.cpu0.dtb.misses 34360 # DTB misses -system.cpu0.dtb.accesses 14071329 # DTB accesses -system.cpu0.itb.inst_hits 4213831 # ITB inst hits -system.cpu0.itb.inst_misses 5055 # ITB inst misses +system.cpu0.dtb.hits 14184994 # DTB hits +system.cpu0.dtb.misses 35106 # DTB misses +system.cpu0.dtb.accesses 14220100 # DTB accesses +system.cpu0.itb.inst_hits 4276462 # ITB inst hits +system.cpu0.itb.inst_misses 5070 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -688,530 +1249,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1341 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1351 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1480 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1356 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4218886 # ITB inst accesses -system.cpu0.itb.hits 4213831 # DTB hits -system.cpu0.itb.misses 5055 # DTB misses -system.cpu0.itb.accesses 4218886 # DTB accesses -system.cpu0.numCycles 67827180 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4281532 # ITB inst accesses +system.cpu0.itb.hits 4276462 # DTB hits +system.cpu0.itb.misses 5070 # DTB misses +system.cpu0.itb.accesses 4281532 # DTB accesses +system.cpu0.numCycles 69613456 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11769589 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31997398 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5994746 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3583006 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7510057 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450935 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 59891 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19410639 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47194 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1299057 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4212263 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157193 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2052 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41143300 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004817 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385260 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11926468 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32461716 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6073314 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3632378 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7613392 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1460130 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 63151 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20074417 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46093 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1371911 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4274981 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157877 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2111 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42149460 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.995068 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.376418 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33640645 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 563027 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816788 1.99% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 677485 1.65% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772099 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558236 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 667723 1.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351865 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3095432 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34543319 81.95% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 572779 1.36% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 825233 1.96% 85.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 684006 1.62% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 778589 1.85% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 565339 1.34% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 679715 1.61% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 356870 0.85% 92.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3143610 7.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41143300 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088383 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471749 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12271204 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20567331 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6814121 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512354 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 978290 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934838 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64553 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39983053 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212073 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 978290 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12839379 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5742381 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12712172 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6708467 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2162611 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38883586 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1814 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 436137 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1233923 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 17 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39230664 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175613245 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175579140 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34105 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30916187 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8314476 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411042 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370243 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5355635 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7643947 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5684540 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124242 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1215247 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36809311 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895353 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37222613 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81088 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6285112 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13160919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256794 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41143300 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904707 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.513127 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42149460 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.087243 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.466314 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12452855 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21284567 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6905227 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 522550 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 984261 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 948796 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64785 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40574738 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212216 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 984261 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13028707 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5941224 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13201317 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6800913 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2193038 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39456506 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 442978 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1248488 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 66 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39834265 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178291734 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178257443 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34291 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31450110 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8384154 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 420012 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 376763 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5452877 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7762434 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5776236 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132872 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1233884 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37360552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 904892 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37716432 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82271 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6323448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13282471 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257104 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42149460 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.894826 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.507768 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26016757 63.23% 63.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5731331 13.93% 77.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3155319 7.67% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471251 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2103314 5.11% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 932641 2.27% 98.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 493188 1.20% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184690 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54809 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26809075 63.60% 63.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5821539 13.81% 77.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3209963 7.62% 85.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2497911 5.93% 90.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2123670 5.04% 96.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 939017 2.23% 98.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 502938 1.19% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188935 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56412 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41143300 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42149460 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26572 2.49% 2.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841830 78.79% 81.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 199561 18.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27471 2.55% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 463 0.04% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 839894 78.10% 80.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207538 19.30% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22321556 59.97% 60.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46948 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9357811 25.14% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5443427 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22648900 60.05% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47937 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9431477 25.01% 85.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5535066 14.68% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37222613 # Type of FU issued -system.cpu0.iq.rate 0.548786 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1068416 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028703 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116763775 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43997708 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34321266 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8390 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4632 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3861 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38234480 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4400 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306660 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37716432 # Type of FU issued +system.cpu0.iq.rate 0.541798 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1075366 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028512 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118766388 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44596758 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34851054 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8389 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38735073 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4381 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316422 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372064 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13106 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537968 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1379018 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2578 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13049 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 541624 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192754 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5299 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149592 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 6129 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 978290 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4120588 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98455 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37822346 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 84553 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7643947 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5684540 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571228 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39920 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2911 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13106 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150072 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117309 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267381 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36846322 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9215739 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 376291 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 984261 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4297602 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 105996 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38383622 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 87186 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7762434 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5776236 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 577553 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40750 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2975 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13049 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150118 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117853 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267971 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37335026 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9287293 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 381406 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117682 # number of nop insts executed -system.cpu0.iew.exec_refs 14611771 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4852307 # Number of branches executed -system.cpu0.iew.exec_stores 5396032 # Number of stores executed -system.cpu0.iew.exec_rate 0.543238 # Inst execution rate -system.cpu0.iew.wb_sent 36653422 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34325127 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18280728 # num instructions producing a value -system.cpu0.iew.wb_consumers 35164479 # num instructions consuming a value +system.cpu0.iew.exec_nop 118178 # number of nop insts executed +system.cpu0.iew.exec_refs 14774953 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4916788 # Number of branches executed +system.cpu0.iew.exec_stores 5487660 # Number of stores executed +system.cpu0.iew.exec_rate 0.536319 # Inst execution rate +system.cpu0.iew.wb_sent 37140556 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34854926 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18563816 # num instructions producing a value +system.cpu0.iew.wb_consumers 35689656 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506067 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519863 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.500692 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520146 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6092264 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231469 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40165010 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778528 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.739872 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6130188 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 647788 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232202 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41165199 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.772263 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.733134 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28490647 70.93% 70.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5723698 14.25% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913208 4.76% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 977623 2.43% 92.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784001 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 521196 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 385694 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 221095 0.55% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1147848 2.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29286812 71.14% 71.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5810011 14.11% 85.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1968218 4.78% 90.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 996844 2.42% 92.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 804428 1.95% 94.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 515457 1.25% 95.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 392582 0.95% 96.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 223885 0.54% 97.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1166962 2.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40165010 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23670535 # Number of instructions committed -system.cpu0.commit.committedOps 31269580 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41165199 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24069809 # Number of instructions committed +system.cpu0.commit.committedOps 31790359 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11418455 # Number of memory references committed -system.cpu0.commit.loads 6271883 # Number of loads committed -system.cpu0.commit.membars 229601 # Number of memory barriers committed -system.cpu0.commit.branches 4243632 # Number of branches committed +system.cpu0.commit.refs 11618028 # Number of memory references committed +system.cpu0.commit.loads 6383416 # Number of loads committed +system.cpu0.commit.membars 231880 # Number of memory barriers committed +system.cpu0.commit.branches 4307208 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27627385 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489162 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1147848 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28099612 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498731 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1166962 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75528065 # The number of ROB reads -system.cpu0.rob.rob_writes 75703855 # The number of ROB writes -system.cpu0.timesIdled 360661 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26683880 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138039181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23589793 # Number of Instructions Simulated -system.cpu0.committedOps 31188838 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23589793 # Number of Instructions Simulated -system.cpu0.cpi 2.875277 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.875277 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347793 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347793 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171736211 # number of integer regfile reads -system.cpu0.int_regfile_writes 34071636 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3249 # number of floating regfile reads -system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12999243 # number of misc regfile reads -system.cpu0.misc_regfile_writes 450984 # number of misc regfile writes -system.cpu0.icache.replacements 392403 # number of replacements -system.cpu0.icache.tagsinuse 511.011252 # Cycle average of tags in use -system.cpu0.icache.total_refs 3789022 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 392915 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.643363 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.011252 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3789022 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3789022 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3789022 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3789022 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3789022 # number of overall hits -system.cpu0.icache.overall_hits::total 3789022 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423106 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423106 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423106 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423106 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423106 # number of overall misses -system.cpu0.icache.overall_misses::total 423106 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5802286496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5802286496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5802286496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5802286496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5802286496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5802286496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4212128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4212128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4212128 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4212128 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4212128 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4212128 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100449 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100449 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100449 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100449 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100449 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100449 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13713.552859 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13713.552859 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13713.552859 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13713.552859 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4195 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77052413 # The number of ROB reads +system.cpu0.rob.rob_writes 76827079 # The number of ROB writes +system.cpu0.timesIdled 370271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27463996 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5157937915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23989067 # Number of Instructions Simulated +system.cpu0.committedOps 31709617 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23989067 # Number of Instructions Simulated +system.cpu0.cpi 2.901883 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.901883 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.344604 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.344604 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174143996 # number of integer regfile reads +system.cpu0.int_regfile_writes 34604534 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3264 # number of floating regfile reads +system.cpu0.fp_regfile_writes 896 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13203658 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457594 # number of misc regfile writes +system.cpu0.icache.replacements 399659 # number of replacements +system.cpu0.icache.tagsinuse 511.575445 # Cycle average of tags in use +system.cpu0.icache.total_refs 3842942 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 400171 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.603250 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6980726000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.575445 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999171 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999171 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3842942 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3842942 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3842942 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3842942 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3842942 # number of overall hits +system.cpu0.icache.overall_hits::total 3842942 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431911 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431911 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 431911 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 431911 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 431911 # number of overall misses +system.cpu0.icache.overall_misses::total 431911 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969636493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5969636493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5969636493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5969636493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5969636493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5969636493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4274853 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4274853 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4274853 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4274853 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4274853 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4274853 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.101035 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.101035 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.101035 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.101035 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.101035 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.101035 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.450468 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13821.450468 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13821.450468 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13821.450468 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3644 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.923497 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.942529 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30174 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30174 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30174 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30174 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30174 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30174 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392932 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 392932 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 392932 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 392932 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 392932 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 392932 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4748967496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4748967496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4748967496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4748967496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4748967496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4748967496 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093286 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093286 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093286 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12085.977971 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31718 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31718 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31718 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31718 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31718 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31718 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400193 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 400193 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 400193 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 400193 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 400193 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 400193 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4864756575 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4864756575 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4864756575 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4864756575 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4864756575 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4864756575 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9682500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9682500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9682500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 9682500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093616 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093616 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093616 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12156.026155 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275974 # number of replacements -system.cpu0.dcache.tagsinuse 462.017037 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9251393 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276486 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.460620 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 462.017037 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.902377 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.902377 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5774321 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5774321 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157289 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3157289 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139126 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139126 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137035 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137035 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8931610 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8931610 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8931610 # number of overall hits -system.cpu0.dcache.overall_hits::total 8931610 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392659 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392659 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582356 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582356 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8783 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8783 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7478 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7478 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1975015 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1975015 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1975015 # number of overall misses -system.cpu0.dcache.overall_misses::total 1975015 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5465751000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5465751000 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6166980 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4739645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147909 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147909 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144513 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144513 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10906625 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10906625 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10906625 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181084 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181084 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13919.841389 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13919.841389 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.700067 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38468.700067 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10074.120460 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10074.120460 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6241.642150 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6241.642150 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33588.063566 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33588.063566 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8548 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2163 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 649 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 77 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.171032 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28.090909 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275313 # number of replacements +system.cpu0.dcache.tagsinuse 479.702966 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9426114 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 275825 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.174255 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 49336000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 479.702966 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.936920 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.936920 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5876643 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5876643 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3228072 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3228072 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139641 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139641 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137200 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137200 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9104715 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9104715 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9104715 # number of overall hits +system.cpu0.dcache.overall_hits::total 9104715 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392586 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392586 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1585207 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1585207 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8832 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8832 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7754 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7754 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977793 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977793 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977793 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977793 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5514730000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5514730000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76877974883 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 76877974883 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 89351500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 89351500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49685500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 49685500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82392704883 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82392704883 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82392704883 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82392704883 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269229 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6269229 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4813279 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4813279 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148473 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148473 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144954 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144954 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11082508 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11082508 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11082508 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11082508 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062621 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062621 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329340 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.329340 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178461 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178461 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178461 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178461 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14047.189660 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14047.189660 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48497.120492 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48497.120492 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10116.791214 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10116.791214 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6407.725045 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6407.725045 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41658.912173 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41658.912173 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10507 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 10018 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 605 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 134 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.366942 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 74.761194 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256417 # number of writebacks -system.cpu0.dcache.writebacks::total 256417 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203981 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203981 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452148 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1452148 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 473 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656129 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1656129 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656129 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1656129 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188678 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188678 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130208 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130208 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318886 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318886 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318886 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318886 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371660000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371660000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4050141991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4050141991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66675500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66675500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31721000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31721000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6421801991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6421801991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6421801991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6421801991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513534500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513534500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180320378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180320378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693854878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693854878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030595 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030595 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027472 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027472 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056183 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056183 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029238 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029238 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12569.880961 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12569.880961 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31105.170120 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31105.170120 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8023.525872 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8023.525872 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4242.476929 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4242.476929 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255296 # number of writebacks +system.cpu0.dcache.writebacks::total 255296 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203565 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203565 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454109 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454109 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 475 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 475 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657674 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657674 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657674 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657674 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189021 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189021 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131098 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131098 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8357 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8357 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7751 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7751 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320119 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320119 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2392342380 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2392342380 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5118910660 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5118910660 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67659513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67659513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34183001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34183001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7511253040 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7511253040 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7511253040 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7511253040 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13429863028 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13429863028 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251424879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251424879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14681287907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14681287907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030151 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030151 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027237 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027237 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053472 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053472 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028885 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028885 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12656.489914 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12656.489914 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39046.443577 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39046.443577 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8096.148498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8096.148498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4410.140756 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4410.140756 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1219,38 +1780,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9076266 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7463483 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407973 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6084116 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5247879 # Number of BTB hits +system.cpu1.branchPred.lookups 9253585 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7592303 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 416171 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6192388 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5325484 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.255407 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773475 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42302 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.000490 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 798470 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43798 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42903620 # DTB read hits -system.cpu1.dtb.read_misses 37068 # DTB read misses -system.cpu1.dtb.write_hits 6823215 # DTB write hits -system.cpu1.dtb.write_misses 10679 # DTB write misses +system.cpu1.dtb.read_hits 43179554 # DTB read hits +system.cpu1.dtb.read_misses 37431 # DTB read misses +system.cpu1.dtb.write_hits 6972554 # DTB write hits +system.cpu1.dtb.write_misses 10848 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2777 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2926 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 258 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 663 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42940688 # DTB read accesses -system.cpu1.dtb.write_accesses 6833894 # DTB write accesses +system.cpu1.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43216985 # DTB read accesses +system.cpu1.dtb.write_accesses 6983402 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49726835 # DTB hits -system.cpu1.dtb.misses 47747 # DTB misses -system.cpu1.dtb.accesses 49774582 # DTB accesses -system.cpu1.itb.inst_hits 8394995 # ITB inst hits -system.cpu1.itb.inst_misses 5378 # ITB inst misses +system.cpu1.dtb.hits 50152108 # DTB hits +system.cpu1.dtb.misses 48279 # DTB misses +system.cpu1.dtb.accesses 50200387 # DTB accesses +system.cpu1.itb.inst_hits 8467709 # ITB inst hits +system.cpu1.itb.inst_misses 5542 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1259,114 +1820,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1500 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1492 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8400373 # ITB inst accesses -system.cpu1.itb.hits 8394995 # DTB hits -system.cpu1.itb.misses 5378 # DTB misses -system.cpu1.itb.accesses 8400373 # DTB accesses -system.cpu1.numCycles 408777731 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8473251 # ITB inst accesses +system.cpu1.itb.hits 8467709 # DTB hits +system.cpu1.itb.misses 5542 # DTB misses +system.cpu1.itb.accesses 8473251 # DTB accesses +system.cpu1.numCycles 412553366 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19817241 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66077936 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9076266 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6021354 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14149044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3958978 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63415 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 75978247 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42826 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1407438 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8393192 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 739597 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114161892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700766 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.044841 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 20142179 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 67124404 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9253585 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6123954 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14367636 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3996679 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69030 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77666254 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41513 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1490350 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8465907 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 710561 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2899 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 116503477 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.698188 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.043258 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100020305 87.61% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 795953 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939001 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1889167 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1518004 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 578108 0.51% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2132011 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410005 0.36% 94.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5879338 5.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 102143196 87.67% 87.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 814134 0.70% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 962782 0.83% 89.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1912655 1.64% 90.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1508621 1.29% 92.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 586161 0.50% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2143967 1.84% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 421141 0.36% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6010820 5.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114161892 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022203 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161648 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21336269 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76905312 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12792890 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524784 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2602637 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1103950 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 97871 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75228090 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 324995 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2602637 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22719770 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31941572 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40729697 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11839035 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4329181 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69767929 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18791 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 669754 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086107 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 334 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73761871 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321211401 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321151882 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59519 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49052831 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24709040 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445091 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388163 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7873081 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13208830 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8144792 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1029727 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1553546 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63522315 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158429 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89134167 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94409 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16267434 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45777798 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277724 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114161892 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780770 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519105 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 116503477 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022430 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.162705 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21695015 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78657608 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12988209 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 540911 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2621734 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1137928 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100371 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 76331637 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 334218 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2621734 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23056356 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33279261 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41089956 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12073504 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4382666 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 71129037 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18835 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 684998 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3107715 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 374 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 75211284 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 327489941 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 327430919 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50108296 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 25102988 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 461152 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 401338 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8025308 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13414582 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8304810 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1056481 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1432553 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 64611179 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1174620 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90302569 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94169 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16313013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45540722 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 275640 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 116503477 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.775106 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513735 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83758719 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8417078 7.37% 80.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4293584 3.76% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3776789 3.31% 87.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10574202 9.26% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966117 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1029866 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 271331 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 74206 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 85607171 73.48% 73.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8609069 7.39% 80.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4398916 3.78% 84.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3887525 3.34% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10612061 9.11% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1964931 1.69% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1085414 0.93% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 259410 0.22% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 78980 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114161892 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 116503477 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32060 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32357 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1394,395 +1955,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7549280 95.84% 96.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 294896 3.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572484 95.70% 96.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 307046 3.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37620086 42.21% 42.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59138 0.07% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43968936 49.33% 91.96% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7170532 8.04% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38359652 42.48% 42.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1701 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44223929 48.97% 91.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7342124 8.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89134167 # Type of FU issued -system.cpu1.iq.rate 0.218050 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7877234 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088375 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300434418 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80956642 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53641825 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15018 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8136 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6869 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96689561 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7908 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342287 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90302569 # Type of FU issued +system.cpu1.iq.rate 0.218887 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7912883 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.087626 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 305148356 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 82107584 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54845197 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15407 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8039 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6808 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 97893314 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8206 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 355446 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3455090 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17135 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1305851 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3436601 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3841 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17378 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1303587 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31905929 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888458 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31958921 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 917809 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2602637 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24185109 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 359685 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64785366 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 111899 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13208830 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8144792 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869085 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64974 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3561 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17135 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 202123 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154728 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356851 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86703480 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43273897 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2430687 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2621734 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25482277 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363023 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 65889169 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 115264 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13414582 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8304810 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 878172 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 66494 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3874 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17378 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 205598 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 157346 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 362944 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87965313 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43561744 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2337256 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104622 # number of nop insts executed -system.cpu1.iew.exec_refs 50383100 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6997981 # Number of branches executed -system.cpu1.iew.exec_stores 7109203 # Number of stores executed -system.cpu1.iew.exec_rate 0.212104 # Inst execution rate -system.cpu1.iew.wb_sent 85724428 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53648694 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29926721 # num instructions producing a value -system.cpu1.iew.wb_consumers 53389506 # num instructions consuming a value +system.cpu1.iew.exec_nop 103370 # number of nop insts executed +system.cpu1.iew.exec_refs 50840273 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7156944 # Number of branches executed +system.cpu1.iew.exec_stores 7278529 # Number of stores executed +system.cpu1.iew.exec_rate 0.213222 # Inst execution rate +system.cpu1.iew.wb_sent 86983330 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54852005 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30529736 # num instructions producing a value +system.cpu1.iew.wb_consumers 54511543 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131242 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560536 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132957 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560060 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16147511 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880705 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311675 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111559255 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431612 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.399673 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16208484 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 898980 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 317402 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 113881743 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.432055 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.398122 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94810700 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8240774 7.39% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114811 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254575 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1245157 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 568382 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 999815 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 505524 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1819517 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 96739305 84.95% 84.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8399776 7.38% 92.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2206670 1.94% 94.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1295256 1.14% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1289720 1.13% 96.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 586162 0.51% 97.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 954092 0.84% 97.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 596070 0.52% 98.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1814692 1.59% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111559255 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38062798 # Number of instructions committed -system.cpu1.commit.committedOps 48150353 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 113881743 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38868743 # Number of instructions committed +system.cpu1.commit.committedOps 49203152 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16592681 # Number of memory references committed -system.cpu1.commit.loads 9753740 # Number of loads committed -system.cpu1.commit.membars 190132 # Number of memory barriers committed -system.cpu1.commit.branches 5967363 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42685619 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534609 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1819517 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16979204 # Number of memory references committed +system.cpu1.commit.loads 9977981 # Number of loads committed +system.cpu1.commit.membars 195491 # Number of memory barriers committed +system.cpu1.commit.branches 6119212 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43616743 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553203 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1814692 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172993511 # The number of ROB reads -system.cpu1.rob.rob_writes 131291211 # The number of ROB writes -system.cpu1.timesIdled 1408204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294615839 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796493799 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37993159 # Number of Instructions Simulated -system.cpu1.committedOps 48080714 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37993159 # Number of Instructions Simulated -system.cpu1.cpi 10.759246 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759246 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092943 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092943 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387964882 # number of integer regfile reads -system.cpu1.int_regfile_writes 56217113 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4997 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2346 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18468785 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405479 # number of misc regfile writes -system.cpu1.icache.replacements 595625 # number of replacements -system.cpu1.icache.tagsinuse 480.695488 # Cycle average of tags in use -system.cpu1.icache.total_refs 7752260 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 596137 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.004158 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74233129000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.695488 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938858 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938858 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7752260 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7752260 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7752260 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7752260 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7752260 # number of overall hits -system.cpu1.icache.overall_hits::total 7752260 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 640881 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 640881 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 640881 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 640881 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 640881 # number of overall misses -system.cpu1.icache.overall_misses::total 640881 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8621805995 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8621805995 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8621805995 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8621805995 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8621805995 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8621805995 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8393141 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8393141 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8393141 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8393141 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8393141 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8393141 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076358 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076358 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076358 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076358 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076358 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076358 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.052899 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.052899 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.052899 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13453.052899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.052899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13453.052899 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2044 # number of cycles access was blocked +system.cpu1.rob.rob_reads 176412864 # The number of ROB reads +system.cpu1.rob.rob_writes 133542996 # The number of ROB writes +system.cpu1.timesIdled 1428534 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 296049889 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4814402067 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38799104 # Number of Instructions Simulated +system.cpu1.committedOps 49133513 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38799104 # Number of Instructions Simulated +system.cpu1.cpi 10.633064 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.633064 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.094046 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.094046 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 393827212 # number of integer regfile reads +system.cpu1.int_regfile_writes 57409312 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5077 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2342 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18946986 # number of misc regfile reads +system.cpu1.misc_regfile_writes 419134 # number of misc regfile writes +system.cpu1.icache.replacements 614670 # number of replacements +system.cpu1.icache.tagsinuse 498.803951 # Cycle average of tags in use +system.cpu1.icache.total_refs 7804426 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 615182 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.686369 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74831061000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.803951 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974226 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974226 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7804426 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7804426 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7804426 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7804426 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7804426 # number of overall hits +system.cpu1.icache.overall_hits::total 7804426 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661434 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661434 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661434 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661434 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661434 # number of overall misses +system.cpu1.icache.overall_misses::total 661434 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8993382992 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8993382992 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8993382992 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8993382992 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8993382992 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8993382992 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8465860 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8465860 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8465860 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8465860 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8465860 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8465860 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078130 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.078130 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078130 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.078130 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078130 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.078130 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.795738 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13596.795738 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13596.795738 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13596.795738 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3054 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.883721 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.897561 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44715 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44715 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44715 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44715 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44715 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44715 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596166 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596166 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596166 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 596166 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 596166 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 596166 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7061200496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7061200496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7061200496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7061200496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7061200496 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7061200496 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2836500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2836500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2836500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2836500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071030 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071030 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.352908 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.352908 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.352908 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46219 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46219 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46219 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46219 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46219 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46219 # 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number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8309067 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4139347 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4139347 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97521 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97521 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94873 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94873 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12448414 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12448414 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12448414 # number of overall hits -system.cpu1.dcache.overall_hits::total 12448414 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 400056 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 400056 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135802 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135802 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15283.367829 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15283.367829 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39493.906966 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39493.906966 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9342.075093 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9342.075093 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5078.054299 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5078.054299 # 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number of replacements +system.cpu1.dcache.tagsinuse 487.194544 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13012998 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363907 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.759131 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70879256000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.194544 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951552 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951552 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8508304 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8508304 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4270423 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4270423 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99789 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 99789 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97069 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 97069 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12778727 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12778727 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12778727 # number of overall hits +system.cpu1.dcache.overall_hits::total 12778727 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 403002 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 403002 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1564321 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1564321 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14195 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14195 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10908 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10908 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1967323 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1967323 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1967323 # number of overall misses +system.cpu1.dcache.overall_misses::total 1967323 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6229483500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6229483500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75673370015 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 75673370015 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131282500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131282500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57807000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 57807000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 81902853515 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 81902853515 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 81902853515 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 81902853515 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8911306 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8911306 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5834744 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5834744 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113984 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 113984 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107977 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107977 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14746050 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14746050 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14746050 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14746050 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045224 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045224 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268104 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.268104 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124535 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124535 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133414 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133414 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133414 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133414 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15457.698721 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15457.698721 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48374.579140 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 48374.579140 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.502994 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.502994 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5299.504950 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5299.504950 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 41631.625064 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 41631.625064 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31799 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 19293 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3299 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 180 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.638982 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 107.183333 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324632 # number of writebacks -system.cpu1.dcache.writebacks::total 324632 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171788 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171788 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394549 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1394549 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1443 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1443 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566337 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566337 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566337 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566337 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161573 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161573 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10605 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10605 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389841 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389841 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389841 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389841 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2854852000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2854852000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5117226213 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5117226213 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89555500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89555500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32658000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32658000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7972078213 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7972078213 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7972078213 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7972078213 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989815500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989815500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35679552148 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35679552148 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204669367648 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204669367648 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026210 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026210 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112247 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112247 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100539 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100539 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027064 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027064 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12506.579985 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12506.579985 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31671.295408 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31671.295408 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7156.996723 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7156.996723 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3079.490806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3079.490806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327984 # number of writebacks +system.cpu1.dcache.writebacks::total 327984 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171525 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171525 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401265 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1401265 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572790 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1572790 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572790 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1572790 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231477 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231477 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163056 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163056 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10906 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10906 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394533 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394533 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394533 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394533 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2900781135 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2900781135 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6520340298 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6520340298 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90030007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90030007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35995000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35995000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9421121433 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9421121433 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9421121433 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9421121433 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169236235005 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169236235005 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34877229187 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34877229187 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204113464192 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204113464192 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025976 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027946 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027946 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111823 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101003 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101003 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026755 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026755 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12531.617115 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12531.617115 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39988.349389 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39988.349389 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7063.392986 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7063.392986 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3300.476802 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3300.476802 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1804,18 +2365,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540125454155 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540125454155 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540125454155 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540125454155 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1508067529269 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1508067529269 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42383 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50336 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index d0699dda9..b3687441c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533116 # Number of seconds simulated -sim_ticks 2533115780500 # Number of ticks simulated -final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534279 # Number of seconds simulated +sim_ticks 2534279149500 # Number of ticks simulated +final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64757 # Simulator instruction rate (inst/s) -host_op_rate 83325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2720016614 # Simulator tick rate (ticks/s) -host_mem_usage 398876 # Number of bytes of host memory used -host_seconds 931.29 # Real time elapsed on the host -sim_insts 60307726 # Number of instructions simulated -sim_ops 77599286 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +host_inst_rate 51469 # Simulator instruction rate (inst/s) +host_op_rate 66227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2162854547 # Simulator tick rate (ticks/s) +host_mem_usage 400508 # Number of bytes of host memory used +host_seconds 1171.73 # Real time elapsed on the host +sim_insts 60307893 # Number of instructions simulated +sim_ops 77599512 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory +system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096806 # Total number of read requests seen -system.physmem.writeReqs 813108 # Total number of write requests seen -system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195584 # Total number of bytes read from memory -system.physmem.bytesWritten 52038912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15098054 # Total number of read requests seen +system.physmem.writeReqs 813133 # Total number of write requests seen +system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966275456 # Total number of bytes read from memory +system.physmem.bytesWritten 52040512 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533114676500 # Total gap between requests +system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534279100000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14942208 # Categorize read packet sizes +system.physmem.readPktSize::3 14943424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154562 # Categorize read packet sizes +system.physmem.readPktSize::6 154594 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59090 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59115 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -139,59 +139,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see -system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482470000 # Total cycles spent in databus access -system.physmem.totBankLat 16917518750 # Total cycles spent in bank access -system.physmem.avgQLat 26047.39 # Average queueing delay per request -system.physmem.avgBankLat 1120.63 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation +system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests +system.physmem.totBusLat 75488575000 # Total cycles spent in databus access +system.physmem.totBankLat 15730536250 # Total cycles spent in bank access +system.physmem.avgQLat 23521.25 # Average queueing delay per request +system.physmem.avgBankLat 1041.92 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.02 # Average memory access latency -system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 29563.16 # Average memory access latency +system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.11 # Average write queue length over time -system.physmem.readRowHits 15020181 # Number of row buffer hits during reads -system.physmem.writeRowHits 793022 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159216.11 # Average gap between requests +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 11.71 # Average write queue length over time +system.physmem.readRowHits 15070837 # Number of row buffer hits during reads +system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes +system.physmem.avgGap 159276.56 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -204,44 +471,259 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54705448 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16150672 # Transaction distribution +system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.trans_dist::WriteReq 763336 # Transaction distribution +system.membus.trans_dist::WriteResp 763336 # Transaction distribution +system.membus.trans_dist::Writeback 59115 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution +system.membus.trans_dist::ReadExReq 131424 # Transaction distribution +system.membus.trans_dist::ReadExResp 131424 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14672817 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits +system.iobus.throughput 48115298 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution +system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.trans_dist::WriteReq 8158 # Transaction distribution +system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.branchPred.lookups 14673159 # Number of BP lookups +system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51400888 # DTB read hits -system.cpu.dtb.read_misses 64225 # DTB read misses -system.cpu.dtb.write_hits 11700104 # DTB write hits -system.cpu.dtb.write_misses 15848 # DTB write misses +system.cpu.dtb.read_hits 51397173 # DTB read hits +system.cpu.dtb.read_misses 63986 # DTB read misses +system.cpu.dtb.write_hits 11699533 # DTB write hits +system.cpu.dtb.write_misses 15890 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465113 # DTB read accesses -system.cpu.dtb.write_accesses 11715952 # DTB write accesses +system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51461159 # DTB read accesses +system.cpu.dtb.write_accesses 11715423 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100992 # DTB hits -system.cpu.dtb.misses 80073 # DTB misses -system.cpu.dtb.accesses 63181065 # DTB accesses -system.cpu.itb.inst_hits 12331220 # ITB inst hits -system.cpu.itb.inst_misses 11422 # ITB inst misses +system.cpu.dtb.hits 63096706 # DTB hits +system.cpu.dtb.misses 79876 # DTB misses +system.cpu.dtb.accesses 63176582 # DTB accesses +system.cpu.itb.inst_hits 12260245 # ITB inst hits +system.cpu.itb.inst_misses 11468 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,113 +732,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2492 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12342642 # ITB inst accesses -system.cpu.itb.hits 12331220 # DTB hits -system.cpu.itb.misses 11422 # DTB misses -system.cpu.itb.accesses 12342642 # DTB accesses -system.cpu.numCycles 471822965 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12271713 # ITB inst accesses +system.cpu.itb.hits 12260245 # DTB hits +system.cpu.itb.misses 11468 # DTB misses +system.cpu.itb.accesses 12271713 # DTB accesses +system.cpu.numCycles 475189978 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -385,383 +867,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued -system.cpu.iq.rate 0.263501 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued +system.cpu.iq.rate 0.261620 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221132 # number of nop insts executed -system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed -system.cpu.iew.exec_branches 11557425 # Number of branches executed -system.cpu.iew.exec_stores 12211932 # Number of stores executed -system.cpu.iew.exec_rate 0.257596 # Inst execution rate -system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47248258 # num instructions producing a value -system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value +system.cpu.iew.exec_nop 221659 # number of nop insts executed +system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed +system.cpu.iew.exec_branches 11560329 # Number of branches executed +system.cpu.iew.exec_stores 12210910 # Number of stores executed +system.cpu.iew.exec_rate 0.255996 # Inst execution rate +system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268053 # num instructions producing a value +system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458107 # Number of instructions committed -system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458274 # Number of instructions committed +system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386657 # Number of memory references committed -system.cpu.commit.loads 15654563 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961339 # Number of branches committed +system.cpu.commit.refs 27386690 # Number of memory references committed +system.cpu.commit.loads 15654575 # Number of loads committed +system.cpu.commit.membars 403596 # Number of memory barriers committed +system.cpu.commit.branches 9961373 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. +system.cpu.commit.function_calls 991268 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242323943 # The number of ROB reads -system.cpu.rob.rob_writes 202004834 # The number of ROB writes -system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307726 # Number of Instructions Simulated -system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated -system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550297300 # number of integer regfile reads -system.cpu.int_regfile_writes 88455600 # number of integer regfile writes -system.cpu.fp_regfile_reads 8347 # number of floating regfile reads -system.cpu.fp_regfile_writes 2910 # number of floating regfile writes -system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads -system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979954 # number of replacements -system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use -system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits -system.cpu.icache.overall_hits::total 11267650 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses -system.cpu.icache.overall_misses::total 1060047 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12327697 # 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number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13758946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259114 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259114 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21018060 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21018060 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21018060 # number of overall hits -system.cpu.dcache.overall_hits::total 21018060 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736156 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736156 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963249 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963249 # number of WriteReq misses +system.cpu.dcache.replacements 643353 # number of replacements +system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use +system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21012027 # number of overall hits +system.cpu.dcache.overall_hits::total 21012027 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963942 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104713593229 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114452877729 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114452877729 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114452877729 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114452877729 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14495102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14495102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3701440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3701440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3701440 # number of overall misses +system.cpu.dcache.overall_misses::total 3701440 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10068067500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10068067500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 132595635732 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 132595635732 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 183801000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 183801000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 231000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 231000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 142663703232 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 142663703232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 142663703232 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 142663703232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256393 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256393 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713467 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713467 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713467 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713467 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050893 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289946 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052806 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15400 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38542.757206 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32274 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26462 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 287 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.238908 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.202091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks -system.cpu.dcache.writebacks::total 607758 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks +system.cpu.dcache.writebacks::total 607669 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,16 +1573,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 7f7ee8a99..edfc62ccf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,175 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401343 # Number of seconds simulated -sim_ticks 2401342505500 # Number of ticks simulated -final_tick 2401342505500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401127 # Number of seconds simulated +sim_ticks 2401127269500 # Number of ticks simulated +final_tick 2401127269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199955 # Simulator instruction rate (inst/s) -host_op_rate 256803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7959007704 # Simulator tick rate (ticks/s) -host_mem_usage 399904 # Number of bytes of host memory used -host_seconds 301.71 # Real time elapsed on the host -sim_insts 60329298 # Number of instructions simulated -sim_ops 77481139 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 142330 # Simulator instruction rate (inst/s) +host_op_rate 182788 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5664980832 # Simulator tick rate (ticks/s) +host_mem_usage 401540 # Number of bytes of host memory used +host_seconds 423.85 # Real time elapsed on the host +sim_insts 60327009 # Number of instructions simulated +sim_ops 77475387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7093136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7145552 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 84928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 676160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 687680 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 175680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1309048 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 84928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 175680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 762720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3745536 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490604 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325756 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761352 # Number of bytes written to this memory +system.physmem.bytes_read::cpu2.inst 173184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1243936 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 173184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3744064 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1523456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 157860 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1334500 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759880 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111683 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1327 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10745 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20467 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58524 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372651 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331439 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812478 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 2706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 19444 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512400 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58501 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39465 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 333625 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812455 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47818820 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2953821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2975916 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286399 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 545132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51912951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73159 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1559768 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552090 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1559768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 72126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 518063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51917488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 72126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318024 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1559294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 634475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 65744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 555781 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1559294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47818820 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3574559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3610391 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352143 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1097221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54728606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12618023 # Total number of read requests seen -system.physmem.writeReqs 398732 # Total number of write requests seen -system.physmem.cpureqs 54886 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807553472 # Total number of bytes read from memory -system.physmem.bytesWritten 25518848 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102909560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2640668 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2360 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788742 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24831 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24649 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 24783 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 25404 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24880 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25222 # Track writes on a per bank basis +system.physmem.bw_total::cpu2.inst 72126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1073844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54732782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12420439 # Total number of read requests seen +system.physmem.writeReqs 390212 # Total number of write requests seen +system.physmem.cpureqs 53603 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 794908096 # Total number of bytes read from memory +system.physmem.bytesWritten 24973568 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 101274592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2588168 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2354 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 776339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 775940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 776092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 776425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 777292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 776809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 775620 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 775424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 775584 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 776041 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 775688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 776201 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 777483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 777433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 776149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 775918 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 25457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 25320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 25407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 26305 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 23374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 23183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 23262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 21306 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 21574 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24259 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 23496 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25221 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14347 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400307282000 # Total gap between requests +system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400092064000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 14 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::2 8 # Categorize read packet sizes +system.physmem.readPktSize::3 12386304 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35097 # Categorize read packet sizes +system.physmem.readPktSize::6 34127 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381303 # Categorize write packet sizes +system.physmem.writePktSize::2 373090 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17429 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 815886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17122 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 803531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 778993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 809862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3060255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2298083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2298065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2262695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 22591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -185,326 +173,482 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14349 # What write queue length does an incoming req see -system.physmem.totQLat 277119182500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 352940243750 # Sum of mem lat for all requests -system.physmem.totBusLat 63090115000 # Total cycles spent in databus access -system.physmem.totBankLat 12730946250 # Total cycles spent in bank access -system.physmem.avgQLat 21962.17 # Average queueing delay per request -system.physmem.avgBankLat 1008.95 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 16974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 16970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 16964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 16959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 16952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 16947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 16944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 16934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14427 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 39302.074493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 6009.687839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33098.413312 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 3004 14.40% 14.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 1328 6.37% 20.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 811 3.89% 24.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 565 2.71% 27.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 381 1.83% 29.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 362 1.74% 30.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 265 1.27% 32.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 238 1.14% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 172 0.82% 34.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 151 0.72% 34.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 130 0.62% 35.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 127 0.61% 36.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 66 0.32% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 86 0.41% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 45 0.22% 37.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 78 0.37% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 36 0.17% 37.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 26 0.12% 37.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 22 0.11% 37.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 43 0.21% 38.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 28 0.13% 38.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 87 0.42% 38.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 101 0.48% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 96 0.46% 39.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 23 0.11% 39.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 38 0.18% 39.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 20 0.10% 39.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 38 0.18% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 12 0.06% 40.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 22 0.11% 40.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 8 0.04% 40.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 17 0.08% 40.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 10 0.05% 40.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 9 0.04% 40.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 4 0.02% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 3 0.01% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 5 0.02% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 9 0.04% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 4 0.02% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 4 0.02% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 2 0.01% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 2 0.01% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 6 0.03% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 3 0.01% 40.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 7 0.03% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 1 0.00% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 2 0.01% 40.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 4 0.02% 40.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 1 0.00% 40.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 3 0.01% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 3 0.01% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 8 0.04% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 2 0.01% 40.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 3 0.01% 40.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 1 0.00% 40.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 3 0.01% 40.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 2 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 2 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 2 0.01% 40.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 1 0.00% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 1 0.00% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 1 0.00% 40.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 6 0.03% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 2 0.01% 40.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 3 0.01% 40.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 40.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 2 0.01% 40.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 2 0.01% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 1 0.00% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 1 0.00% 41.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 1 0.00% 41.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 4 0.02% 41.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 41.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.01% 41.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 1 0.00% 41.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.01% 41.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 1 0.00% 41.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 2 0.01% 41.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 41.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 1 0.00% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 2 0.01% 41.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11167 1 0.00% 41.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 1 0.00% 41.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 1 0.00% 41.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 2 0.01% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 1 0.00% 41.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 12093 57.97% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::127424-127455 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 181 0.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20861 # Bytes accessed per row activation +system.physmem.totQLat 241895050750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 315493767000 # Sum of mem lat for all requests +system.physmem.totBusLat 62102190000 # Total cycles spent in databus access +system.physmem.totBankLat 11496526250 # Total cycles spent in bank access +system.physmem.avgQLat 19475.57 # Average queueing delay per request +system.physmem.avgBankLat 925.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27971.12 # Average memory access latency -system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25401.18 # Average memory access latency +system.physmem.avgRdBW 331.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.71 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563435 # Number of row buffer hits during reads -system.physmem.writeRowHits 392399 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184401.36 # Average gap between requests -system.l2c.replacements 63248 # number of replacements -system.l2c.tagsinuse 50357.471102 # Cycle average of tags in use -system.l2c.total_refs 1749120 # Total number of references to valid blocks. -system.l2c.sampled_refs 128641 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.596909 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374433885500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36827.136068 # Average occupied blocks per requestor +system.physmem.busUtil 2.67 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 0.40 # Average write queue length over time +system.physmem.readRowHits 12404411 # Number of row buffer hits during reads +system.physmem.writeRowHits 385376 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes +system.physmem.avgGap 187351.30 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55731119 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 12759502 # Transaction distribution +system.membus.trans_dist::ReadResp 12759502 # Transaction distribution +system.membus.trans_dist::WriteReq 375940 # Transaction distribution +system.membus.trans_dist::WriteResp 375940 # Transaction distribution +system.membus.trans_dist::Writeback 17122 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2354 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2354 # Transaction distribution +system.membus.trans_dist::ReadExReq 26440 # Transaction distribution +system.membus.trans_dist::ReadExResp 26440 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1572986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 24772608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 24772608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 25608888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 26345594 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4772328 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5513215 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 99090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 99090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 103862760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 104603647 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817510 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 420513000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 13413227250 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) +system.membus.reqLayer3.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1495675396 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 27962648500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.l2c.replacements 63244 # number of replacements +system.l2c.tagsinuse 50337.430960 # Cycle average of tags in use +system.l2c.total_refs 1749337 # Total number of references to valid blocks. +system.l2c.sampled_refs 128639 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.598808 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374950539000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36831.801957 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5149.319270 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3787.835363 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 800.097709 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 742.779862 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 5.892734 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1445.756642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1597.659994 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.561938 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5222.807479 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3773.258681 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993312 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 729.926692 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 767.531716 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 5.853930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1434.252547 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1571.004504 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562009 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078572 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057798 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.079694 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057575 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.012209 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011334 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000090 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.022060 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024378 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768394 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8872 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3222 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 463074 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169165 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2536 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 132302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18053 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 283993 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 138836 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290665 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597754 # number of Writeback hits -system.l2c.Writeback_hits::total 597754 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.occ_percent::cpu1.inst 0.011138 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011712 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000089 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.021885 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.023972 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768088 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 461135 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166289 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 135286 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65788 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18369 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4267 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 282351 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 141179 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290913 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597640 # number of Writeback hits +system.l2c.Writeback_hits::total 597640 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60607 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19371 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33591 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113569 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8872 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3222 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 463074 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 229772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2536 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 132302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 84752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18053 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 283993 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 172427 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404234 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8872 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3222 # number of overall hits -system.l2c.overall_hits::cpu0.inst 463074 # number of overall hits -system.l2c.overall_hits::cpu0.data 229772 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2536 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1092 # number of overall hits -system.l2c.overall_hits::cpu1.inst 132302 # number of overall hits -system.l2c.overall_hits::cpu1.data 84752 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18053 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4139 # number of overall hits -system.l2c.overall_hits::cpu2.inst 283993 # number of overall hits -system.l2c.overall_hits::cpu2.data 172427 # number of overall hits -system.l2c.overall_hits::total 1404234 # number of overall hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60771 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19509 # 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average ReadReq mshr uncacheable latency @@ -654,438 +801,631 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 58868329 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1038711 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1038710 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 375940 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 375940 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 275281 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80190 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80190 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 843862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2343005 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15512 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 51160 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 3253539 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26980864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38469375 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21900 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 84004 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 65556143 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141250094 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100256 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2175069728 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1900577406 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1863798035 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 10055959 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 30318675 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48814240 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 12751762 # Transaction distribution +system.iobus.trans_dist::ReadResp 12751762 # Transaction distribution +system.iobus.trans_dist::WriteReq 2783 # Transaction distribution +system.iobus.trans_dist::WriteResp 2783 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 736482 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 25509090 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 740439 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 99830871 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209202 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7987000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 1551000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 361193000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 12386304000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 733699000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 24772608000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8064741 # DTB read hits -system.cpu0.dtb.read_misses 6215 # DTB read misses -system.cpu0.dtb.write_hits 6627061 # DTB write hits -system.cpu0.dtb.write_misses 2040 # DTB write misses +system.cpu0.dtb.read_hits 8064428 # DTB read hits +system.cpu0.dtb.read_misses 6238 # DTB read misses +system.cpu0.dtb.write_hits 6663212 # DTB write hits +system.cpu0.dtb.write_misses 2045 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5695 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5690 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8070956 # DTB read accesses -system.cpu0.dtb.write_accesses 6629101 # DTB write accesses +system.cpu0.dtb.read_accesses 8070666 # DTB read accesses +system.cpu0.dtb.write_accesses 6665257 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14691802 # DTB hits -system.cpu0.dtb.misses 8255 # DTB misses -system.cpu0.dtb.accesses 14700057 # DTB accesses -system.cpu0.itb.inst_hits 32689341 # ITB inst hits -system.cpu0.itb.inst_misses 3490 # ITB inst misses +system.cpu0.dtb.hits 14727640 # DTB hits +system.cpu0.dtb.misses 8283 # DTB misses +system.cpu0.dtb.accesses 14735923 # DTB accesses +system.cpu0.itb.inst_hits 32885888 # ITB inst hits +system.cpu0.itb.inst_misses 3493 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2596 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2597 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32692831 # ITB inst accesses -system.cpu0.itb.hits 32689341 # DTB hits -system.cpu0.itb.misses 3490 # DTB misses -system.cpu0.itb.accesses 32692831 # DTB accesses -system.cpu0.numCycles 114004049 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32889381 # ITB inst accesses +system.cpu0.itb.hits 32885888 # DTB hits +system.cpu0.itb.misses 3493 # DTB misses +system.cpu0.itb.accesses 32889381 # DTB accesses +system.cpu0.numCycles 114194187 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32197863 # Number of instructions committed -system.cpu0.committedOps 42390807 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37541776 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5152 # Number of float alu accesses -system.cpu0.num_func_calls 1189364 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4237827 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37541776 # number of integer instructions -system.cpu0.num_fp_insts 5152 # number of float instructions -system.cpu0.num_int_register_reads 191249726 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39627279 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3662 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15356244 # number of memory refs -system.cpu0.num_load_insts 8432602 # Number of load instructions -system.cpu0.num_store_insts 6923642 # Number of store instructions -system.cpu0.num_idle_cycles 13418877123.276752 # Number of idle cycles -system.cpu0.num_busy_cycles -13304873074.276752 # Number of busy cycles -system.cpu0.not_idle_fraction -116.705268 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.705268 # Percentage of idle cycles +system.cpu0.committedInsts 32400694 # Number of instructions committed +system.cpu0.committedOps 42604041 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37748945 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses +system.cpu0.num_func_calls 1185552 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4241024 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37748945 # number of integer instructions +system.cpu0.num_fp_insts 5021 # number of float instructions +system.cpu0.num_int_register_reads 192241357 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39867524 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written +system.cpu0.num_mem_refs 15390684 # number of memory refs +system.cpu0.num_load_insts 8430090 # Number of load instructions +system.cpu0.num_store_insts 6960594 # Number of store instructions +system.cpu0.num_idle_cycles 13437222906.022394 # Number of idle cycles +system.cpu0.num_busy_cycles -13323028719.022394 # Number of busy cycles +system.cpu0.not_idle_fraction -116.669938 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.669938 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 891776 # number of replacements -system.cpu0.icache.tagsinuse 511.602850 # Cycle average of tags in use -system.cpu0.icache.total_refs 44220417 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892288 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.558458 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8123363500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 478.597837 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.659572 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 15.345442 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.934761 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034491 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.029972 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed +system.cpu0.icache.replacements 891212 # number of replacements +system.cpu0.icache.tagsinuse 511.602596 # Cycle average of tags in use +system.cpu0.icache.total_refs 44302670 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 891724 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.682043 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 8165076000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 482.545707 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 22.025938 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 7.030951 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.942472 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.043019 # 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Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23235714 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630414 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.857865 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.756165 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.709007 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.531944 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968274 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.018963 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012758 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.218177 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 10.352055 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.426883 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.967223 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.020219 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012553 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6946152 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1881152 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4479308 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13306612 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5948925 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1341191 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2128617 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9418733 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131368 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34012 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72748 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238128 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137743 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35737 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73913 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12895077 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3222343 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6607925 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22725345 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12895077 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3222343 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6607925 # number of overall hits -system.cpu0.dcache.overall_hits::total 22725345 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169178 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 64842 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 284494 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 518514 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167271 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29535 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 600821 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 797627 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6375 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1725 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3870 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11970 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 336449 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94377 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 885315 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1316141 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 336449 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94377 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 885315 # number of overall misses -system.cpu0.dcache.overall_misses::total 1316141 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 903782500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4105019000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5008801500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 727658500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18527388398 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19255046898 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22582000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52040000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74622000 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13825126 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6116196 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1370726 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2729438 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216360 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137743 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35737 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76618 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250098 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35737 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73917 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13231526 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3316720 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7493240 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24041486 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13231526 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3316720 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7493240 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24041486 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023777 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033321 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059720 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037505 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027349 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021547 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220126 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078074 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046282 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048269 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050510 # 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miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216832 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.076367 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045966 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049609 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.049996 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025239 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028508 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116659 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054034 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025239 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028508 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116659 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054034 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14248.784565 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14514.852880 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9829.250955 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30634.922499 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35581.599196 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 27719.242590 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13121.992166 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13248.254461 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6243.103160 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17286.425718 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25564.242555 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18435.599528 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17286.425718 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25564.242555 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18435.599528 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10180 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1987 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1115 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 42 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.130045 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 47.309524 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19389.405214 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28616.656810 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20571.757912 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19389.405214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 28616.656810 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20571.757912 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10003 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3430 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1178 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.491511 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597754 # number of writebacks -system.cpu0.dcache.writebacks::total 597754 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146487 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146487 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 547791 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 547791 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 426 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 426 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 694278 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 694278 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 694278 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 694278 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64842 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138007 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4672112493 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27590939000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28973644000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56564583000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276412500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14137928134 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15414340634 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28867351500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43111572134 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71978923634 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028970 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019429 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008082 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048269 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044950 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011872 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011872 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.226767 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13012.144312 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12668.859595 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22637.159303 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27034.857496 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25461.720983 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.014493 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11689.459930 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11489.746566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597640 # number of writebacks +system.cpu0.dcache.writebacks::total 597640 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 147191 # 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number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29806 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 51832 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81638 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1787 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3452 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5239 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 95009 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 192161 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 287170 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 95009 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 192161 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 287170 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 798657500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1814845381 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2613502881 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 853492500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1663883074 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2517375574 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19875000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39692503 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59567503 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1652150000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3478728455 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5130878455 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1652150000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478728455 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5130878455 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27438525500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28895903000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56334428500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439019500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930302419 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15369321919 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28877545000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42826205419 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71703750419 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033512 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029420 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014862 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021489 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019306 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007991 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044631 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020906 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011943 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011943 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12248.784565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12932.789238 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12715.795501 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28634.922499 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32101.463845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30835.831035 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11121.992166 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11498.407590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.013934 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,219 +1438,219 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2161402 # DTB read hits -system.cpu1.dtb.read_misses 2114 # DTB read misses -system.cpu1.dtb.write_hits 1457218 # DTB write hits -system.cpu1.dtb.write_misses 386 # DTB write misses +system.cpu1.dtb.read_hits 2160353 # DTB read hits +system.cpu1.dtb.read_misses 2072 # DTB read misses +system.cpu1.dtb.write_hits 1463428 # DTB write hits +system.cpu1.dtb.write_misses 375 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1741 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2163516 # DTB read accesses -system.cpu1.dtb.write_accesses 1457604 # DTB write accesses +system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2162425 # DTB read accesses +system.cpu1.dtb.write_accesses 1463803 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3618620 # DTB hits -system.cpu1.dtb.misses 2500 # DTB misses -system.cpu1.dtb.accesses 3621120 # DTB accesses -system.cpu1.itb.inst_hits 8380082 # ITB inst hits -system.cpu1.itb.inst_misses 1132 # ITB inst misses +system.cpu1.dtb.hits 3623781 # DTB hits +system.cpu1.dtb.misses 2447 # DTB misses +system.cpu1.dtb.accesses 3626228 # DTB accesses +system.cpu1.itb.inst_hits 8343384 # ITB inst hits +system.cpu1.itb.inst_misses 1170 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8381214 # ITB inst accesses -system.cpu1.itb.hits 8380082 # DTB hits -system.cpu1.itb.misses 1132 # DTB misses -system.cpu1.itb.accesses 8381214 # DTB accesses -system.cpu1.numCycles 574618954 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8344554 # ITB inst accesses +system.cpu1.itb.hits 8343384 # DTB hits +system.cpu1.itb.misses 1170 # DTB misses +system.cpu1.itb.accesses 8344554 # DTB accesses +system.cpu1.numCycles 576594127 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8175033 # Number of instructions committed -system.cpu1.committedOps 10410069 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9322021 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses -system.cpu1.num_func_calls 315375 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1140852 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9322021 # number of integer instructions -system.cpu1.num_fp_insts 1998 # number of float instructions -system.cpu1.num_int_register_reads 53738545 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10097471 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3791152 # number of memory refs -system.cpu1.num_load_insts 2256757 # Number of load instructions -system.cpu1.num_store_insts 1534395 # Number of store instructions -system.cpu1.num_idle_cycles 532868716.793879 # Number of idle cycles -system.cpu1.num_busy_cycles 41750237.206121 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072657 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927343 # Percentage of idle cycles +system.cpu1.committedInsts 8139213 # Number of instructions committed +system.cpu1.committedOps 10387341 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9296011 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses +system.cpu1.num_func_calls 319457 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1149983 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9296011 # number of integer instructions +system.cpu1.num_fp_insts 2143 # number of float instructions +system.cpu1.num_int_register_reads 53626328 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10059981 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3800206 # number of memory refs +system.cpu1.num_load_insts 2257531 # Number of load instructions +system.cpu1.num_store_insts 1542675 # Number of store instructions +system.cpu1.num_idle_cycles 550949024.070645 # Number of idle cycles +system.cpu1.num_busy_cycles 25645102.929355 # Number of busy cycles +system.cpu1.not_idle_fraction 0.044477 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.955523 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4722397 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3838487 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221435 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 2952816 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527233 # Number of BTB hits +system.cpu2.branchPred.lookups 4706679 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3828645 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 220746 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3114772 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2519361 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.587216 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411089 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21408 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.884283 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 411150 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21524 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10881575 # DTB read hits -system.cpu2.dtb.read_misses 22640 # DTB read misses -system.cpu2.dtb.write_hits 3277177 # DTB write hits -system.cpu2.dtb.write_misses 5849 # DTB write misses +system.cpu2.dtb.read_hits 10881090 # DTB read hits +system.cpu2.dtb.read_misses 22334 # DTB read misses +system.cpu2.dtb.write_hits 3233578 # DTB write hits +system.cpu2.dtb.write_misses 5962 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2319 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 814 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2292 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 695 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10904215 # DTB read accesses -system.cpu2.dtb.write_accesses 3283026 # DTB write accesses +system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10903424 # DTB read accesses +system.cpu2.dtb.write_accesses 3239540 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14158752 # DTB hits -system.cpu2.dtb.misses 28489 # DTB misses -system.cpu2.dtb.accesses 14187241 # DTB accesses -system.cpu2.itb.inst_hits 4065885 # ITB inst hits -system.cpu2.itb.inst_misses 4502 # ITB inst misses +system.cpu2.dtb.hits 14114668 # DTB hits +system.cpu2.dtb.misses 28296 # DTB misses +system.cpu2.dtb.accesses 14142964 # DTB accesses +system.cpu2.itb.inst_hits 3988029 # ITB inst hits +system.cpu2.itb.inst_misses 4597 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1713 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1005 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 994 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4070387 # ITB inst accesses -system.cpu2.itb.hits 4065885 # DTB hits -system.cpu2.itb.misses 4502 # DTB misses -system.cpu2.itb.accesses 4070387 # DTB accesses -system.cpu2.numCycles 88259873 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 3992626 # ITB inst accesses +system.cpu2.itb.hits 3988029 # DTB hits +system.cpu2.itb.misses 4597 # DTB misses +system.cpu2.itb.accesses 3992626 # DTB accesses +system.cpu2.numCycles 88357796 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9453176 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32426467 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4722397 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2938322 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6835194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1814499 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51467 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18689225 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 953 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32914 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 708494 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4064555 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309850 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1926 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37018169 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050897 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436881 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9310481 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32575007 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4706679 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2930511 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6844695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1834626 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50535 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18792292 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 211 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 834 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32689 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721380 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3986556 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 271694 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2030 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37012176 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.054575 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.442886 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30188064 81.55% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 383346 1.04% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 510640 1.38% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 813031 2.20% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 657801 1.78% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 343878 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1012409 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 238466 0.64% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2870534 7.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30172484 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 383589 1.04% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509700 1.38% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 816595 2.21% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 649845 1.76% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 340688 0.92% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1002283 2.71% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 233105 0.63% 92.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2903887 7.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37018169 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053506 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367398 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10067654 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19275483 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6184949 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 295259 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1193811 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 613325 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53657 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36756215 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 182103 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1193811 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10642239 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6572797 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11156885 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5885889 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1565553 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34514239 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2456 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 419835 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 882809 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 92 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37003284 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157776579 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157748805 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27774 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25809996 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11193287 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230807 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207161 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3357083 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6535673 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3850744 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 536963 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 792176 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31747463 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511528 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34289699 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55083 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7395646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19879544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155324 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37018169 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.926294 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580927 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37012176 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053268 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368672 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9923582 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19398911 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6192413 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 289708 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1206624 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608704 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53227 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36668894 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179672 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1206624 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10457732 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6796532 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11090349 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5929465 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1530564 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34717207 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2441 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 375073 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 892617 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 118 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37295857 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 158754403 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 158727276 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27127 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25598469 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11697387 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231672 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208131 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3300393 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6518889 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3789656 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530954 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 691805 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31588093 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511099 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34136489 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54725 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7434189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19599124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154239 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37012176 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.922304 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.578312 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24442328 66.03% 66.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3909913 10.56% 76.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2354045 6.36% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974122 5.33% 88.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2799200 7.56% 95.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 884316 2.39% 98.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 484064 1.31% 99.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 134882 0.36% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35299 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24481195 66.14% 66.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3912173 10.57% 76.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2318887 6.27% 82.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2014061 5.44% 88.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2743513 7.41% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 884212 2.39% 98.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 492586 1.33% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 130661 0.35% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34888 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37018169 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37012176 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18550 1.21% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18493 1.21% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available @@ -1338,148 +1678,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1408407 91.61% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110486 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1405660 91.60% 92.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110389 7.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61448 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19376629 56.51% 56.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 26012 0.08% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11380471 33.19% 89.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3444734 10.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61311 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19306288 56.56% 56.74% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 26277 0.08% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 7 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 369 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11344167 33.23% 90.05% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3398057 9.95% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34289699 # Type of FU issued -system.cpu2.iq.rate 0.388508 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537443 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044837 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107211457 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39659859 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27420215 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6989 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3825 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3150 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35761973 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3721 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 208327 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34136489 # Type of FU issued +system.cpu2.iq.rate 0.386344 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534543 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044953 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106895526 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39538518 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27366143 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7075 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3717 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3145 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35605938 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3783 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206498 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1579914 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1893 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9373 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 582518 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1561517 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1841 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9166 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 566678 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5363105 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352533 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5349938 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 380447 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1193811 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4877812 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91796 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32340028 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60265 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6535673 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3850744 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369403 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31610 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2472 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9373 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105135 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88586 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193721 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33297921 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11093060 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 991778 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1206624 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5097630 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 92333 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32182024 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61203 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6518889 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3789656 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368677 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31621 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2335 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9166 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105355 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88176 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193531 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33238932 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11092763 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 897557 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 81037 # number of nop insts executed -system.cpu2.iew.exec_refs 14504508 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3695173 # Number of branches executed -system.cpu2.iew.exec_stores 3411448 # Number of stores executed -system.cpu2.iew.exec_rate 0.377271 # Inst execution rate -system.cpu2.iew.wb_sent 32878469 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27423365 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15687848 # num instructions producing a value -system.cpu2.iew.wb_consumers 28539684 # num instructions consuming a value +system.cpu2.iew.exec_nop 82832 # number of nop insts executed +system.cpu2.iew.exec_refs 14457569 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3671446 # Number of branches executed +system.cpu2.iew.exec_stores 3364806 # Number of stores executed +system.cpu2.iew.exec_rate 0.376186 # Inst execution rate +system.cpu2.iew.wb_sent 32811396 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27369288 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15602510 # num instructions producing a value +system.cpu2.iew.wb_consumers 28268763 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.310712 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549685 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309755 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.551935 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7335381 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356204 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168508 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35824220 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.690433 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.719118 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7374898 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356860 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168297 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35805367 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.685358 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714033 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27176930 75.86% 75.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4185525 11.68% 87.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1261410 3.52% 91.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 649563 1.81% 92.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 571804 1.60% 94.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 316250 0.88% 95.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 400543 1.12% 96.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 292091 0.82% 97.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 970104 2.71% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27231349 76.05% 76.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4142496 11.57% 87.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1257531 3.51% 91.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 645964 1.80% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 562986 1.57% 94.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317406 0.89% 95.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 386660 1.08% 96.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302677 0.85% 97.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 958298 2.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35824220 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20010366 # Number of instructions committed -system.cpu2.commit.committedOps 24734227 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35805367 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19842604 # Number of instructions committed +system.cpu2.commit.committedOps 24539507 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8223985 # Number of memory references committed -system.cpu2.commit.loads 4955759 # Number of loads committed -system.cpu2.commit.membars 94186 # Number of memory barriers committed -system.cpu2.commit.branches 3169280 # Number of branches committed -system.cpu2.commit.fp_insts 3103 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21954082 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294910 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 970104 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8180350 # Number of memory references committed +system.cpu2.commit.loads 4957372 # Number of loads committed +system.cpu2.commit.membars 94561 # Number of memory barriers committed +system.cpu2.commit.branches 3152552 # Number of branches committed +system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21772655 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294654 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 958298 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66398809 # The number of ROB reads -system.cpu2.rob.rob_writes 65374131 # The number of ROB writes -system.cpu2.timesIdled 360148 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51241704 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567295976 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19956402 # Number of Instructions Simulated -system.cpu2.committedOps 24680263 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19956402 # Number of Instructions Simulated -system.cpu2.cpi 4.422635 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.422635 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.226110 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.226110 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153855471 # number of integer regfile reads -system.cpu2.int_regfile_writes 29258344 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22383 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20838 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9035132 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240694 # number of misc regfile writes +system.cpu2.rob.rob_reads 66237138 # The number of ROB reads +system.cpu2.rob.rob_writes 65080734 # The number of ROB writes +system.cpu2.timesIdled 362582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51345620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3559271384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19787102 # Number of Instructions Simulated +system.cpu2.committedOps 24484005 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19787102 # Number of Instructions Simulated +system.cpu2.cpi 4.465424 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.465424 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.223943 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.223943 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153570043 # number of integer regfile reads +system.cpu2.int_regfile_writes 29228694 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22407 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8993137 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241651 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1834,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981038235668 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981038235668 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981038235668 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981038235668 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1181598504500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1181598504500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 8bb759cd2..1abf69682 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,163 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.543311 # Number of seconds simulated -sim_ticks 2543310963000 # Number of ticks simulated -final_tick 2543310963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548434 # Number of seconds simulated +sim_ticks 2548433543500 # Number of ticks simulated +final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64896 # Simulator instruction rate (inst/s) -host_op_rate 83503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2736674491 # Simulator tick rate (ticks/s) -host_mem_usage 401948 # Number of bytes of host memory used -host_seconds 929.34 # Real time elapsed on the host -sim_insts 60310426 # Number of instructions simulated -sim_ops 77602848 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 62524 # Simulator instruction rate (inst/s) +host_op_rate 80452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2641694597 # Simulator tick rate (ticks/s) +host_mem_usage 403600 # Number of bytes of host memory used +host_seconds 964.70 # Real time elapsed on the host +sim_insts 60316814 # Number of instructions simulated +sim_ops 77611972 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1152 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 505600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4226512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 293504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4868124 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007148 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 505600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 293504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1344512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1671600 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802416 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 441408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4859600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 357888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4231256 # Number of bytes read from this memory +system.physmem.bytes_read::total 131003368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 441408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 357888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1678512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1337588 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799652 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 18 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 76071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293491 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59161 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336128 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417900 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813189 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47619237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 75965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5592 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293431 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 419628 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 334397 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47523518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 452 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1661815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1914089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51510472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198796 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1488730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 528646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2674630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1488730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47619237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 173208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1906897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 140435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1660336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51405448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 173208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 140435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 658645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 524867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47523518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 452 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2190461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2571343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54185102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293491 # Total number of read requests seen -system.physmem.writeReqs 813189 # Total number of write requests seen -system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978783424 # Total number of bytes read from memory -system.physmem.bytesWritten 52044096 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131007148 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6802416 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4673 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956089 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956033 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50730 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 173208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2565541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 140435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2185203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54073617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293431 # Total number of read requests seen +system.physmem.writeReqs 813143 # Total number of write requests seen +system.physmem.cpureqs 218375 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978779584 # Total number of bytes read from memory +system.physmem.bytesWritten 52041152 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131003368 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799652 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955530 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955758 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955787 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956070 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955978 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51082 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51266 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51317 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51099 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50759 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50974 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51122 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32475 # Number of times wr buffer was full causing retry -system.physmem.totGap 2543309787500 # Total gap between requests +system.physmem.numWrRetry 32387 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548432371500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 43 # Categorize read packet sizes +system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154632 # Categorize read packet sizes +system.physmem.readPktSize::6 154573 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754028 # Categorize write packet sizes +system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59161 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3605165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 59966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1060830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 986831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 991569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2806537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2762834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -168,282 +156,517 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35292 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see -system.physmem.totQLat 346644691750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439813624250 # Sum of mem lat for all requests -system.physmem.totBusLat 76467385000 # Total cycles spent in databus access -system.physmem.totBankLat 16701547500 # Total cycles spent in bank access -system.physmem.avgQLat 22666.18 # Average queueing delay per request -system.physmem.avgBankLat 1092.07 # Average bank access latency per request +system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32415 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 5 0.01% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 4 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 4 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 3 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 2 0.00% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 3 0.01% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 2 0.00% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 5 0.01% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 4 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 3 0.01% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5087 2 0.00% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 5 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 6 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.00% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 2 0.00% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 6 0.01% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 2 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 1 0.00% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 3 0.01% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 5 0.01% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 2 0.00% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 20 0.05% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.00% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 3 0.01% 61.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 2 0.00% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 9 0.02% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 4 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 7 0.02% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 4 0.01% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 2 0.00% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 309 0.77% 62.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 1 0.00% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9695 1 0.00% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 1 0.00% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 1 0.00% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30623 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 1 0.00% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32799 2 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 6 0.01% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35359 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42975 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58143 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58655 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61120-61151 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::123712-123743 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130048-130079 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161280-161311 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168384-168415 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::187392-187423 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation +system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467100000 # Total cycles spent in databus access +system.physmem.totBankLat 15405417500 # Total cycles spent in bank access +system.physmem.avgQLat 20197.04 # Average queueing delay per request +system.physmem.avgBankLat 1007.32 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28758.25 # Average memory access latency -system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 26204.36 # Average memory access latency +system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.13 # Average write queue length over time -system.physmem.readRowHits 15218324 # Number of row buffer hits during reads -system.physmem.writeRowHits 794497 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes -system.physmem.avgGap 157904.04 # Average gap between requests -system.l2c.replacements 64400 # number of replacements -system.l2c.tagsinuse 51409.834545 # Cycle average of tags in use -system.l2c.total_refs 1903586 # Total number of references to valid blocks. -system.l2c.sampled_refs 129789 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.666775 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2531435998500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36958.443874 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 20.878124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5181.005742 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3269.589268 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 7.697989 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3013.641151 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2958.578047 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563941 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000319 # Average percentage of cache occupancy +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 1.10 # Average write queue length over time +system.physmem.readRowHits 15267875 # Number of row buffer hits during reads +system.physmem.writeRowHits 798648 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes +system.physmem.avgGap 158223.12 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55014580 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346067 # Transaction distribution +system.membus.trans_dist::ReadResp 16346070 # Transaction distribution +system.membus.trans_dist::WriteReq 763348 # Transaction distribution +system.membus.trans_dist::WriteResp 763348 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution +system.membus.trans_dist::ReadExReq 131411 # Transaction distribution +system.membus.trans_dist::ReadExResp 131411 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution +system.membus.trans_dist::StoreCondReq 3 # Transaction distribution +system.membus.trans_dist::StoreCondResp 3 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32163398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550150 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692492 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19090473 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 137803020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140201001 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140201001 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1492522500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 17540815750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3583500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4705924038 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34177393245 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.l2c.replacements 64346 # number of replacements +system.l2c.tagsinuse 51424.069961 # Cycle average of tags in use +system.l2c.total_refs 1905385 # Total number of references to valid blocks. +system.l2c.sampled_refs 129735 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.686746 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2511358439500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36974.185132 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 11.366489 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000367 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4621.370879 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3355.179290 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 15.725461 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3578.652286 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2867.590058 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.564181 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000173 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.079056 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.049890 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.045985 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.045144 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784452 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 489769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 212787 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6706 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 481086 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -634,680 +861,876 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7600384 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6061207 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379102 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4941026 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4041960 # Number of BTB hits +system.toL2Bus.throughput 58505331 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution +system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution +system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution +system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148893553 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48461480 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution +system.iobus.trans_dist::WriteReq 8160 # Transaction distribution +system.iobus.trans_dist::WriteResp 8160 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500861 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu0.branchPred.lookups 7472736 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.804063 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 728879 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39033 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26040938 # DTB read hits -system.cpu0.dtb.read_misses 40555 # DTB read misses -system.cpu0.dtb.write_hits 5901951 # DTB write hits -system.cpu0.dtb.write_misses 9434 # DTB write misses -system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25723416 # DTB read hits +system.cpu0.dtb.read_misses 39440 # DTB read misses +system.cpu0.dtb.write_hits 6006462 # DTB write hits +system.cpu0.dtb.write_misses 9528 # DTB write misses +system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5623 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26081493 # DTB read accesses -system.cpu0.dtb.write_accesses 5911385 # DTB write accesses +system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25762856 # DTB read accesses +system.cpu0.dtb.write_accesses 6015990 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31942889 # DTB hits -system.cpu0.dtb.misses 49989 # DTB misses -system.cpu0.dtb.accesses 31992878 # DTB accesses -system.cpu0.itb.inst_hits 6096045 # ITB inst hits -system.cpu0.itb.inst_misses 7428 # ITB inst misses +system.cpu0.dtb.hits 31729878 # DTB hits +system.cpu0.dtb.misses 48968 # DTB misses +system.cpu0.dtb.accesses 31778846 # DTB accesses +system.cpu0.itb.inst_hits 6261683 # ITB inst hits +system.cpu0.itb.inst_misses 7235 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1569 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6103473 # ITB inst accesses -system.cpu0.itb.hits 6096045 # DTB hits -system.cpu0.itb.misses 7428 # DTB misses -system.cpu0.itb.accesses 6103473 # DTB accesses -system.cpu0.numCycles 239139269 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses +system.cpu0.itb.hits 6261683 # DTB hits +system.cpu0.itb.misses 7235 # DTB misses +system.cpu0.itb.accesses 6268918 # DTB accesses +system.cpu0.numCycles 237920120 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15469651 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47735703 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7600384 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4770839 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10588915 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2554228 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92050 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48266741 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1619 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2012 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51922 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1409369 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6094028 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397204 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3100 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77649364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.760813 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.117939 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67068023 86.37% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685973 0.88% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 883508 1.14% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1225779 1.58% 89.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1145464 1.48% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 573659 0.74% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1320882 1.70% 93.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397746 0.51% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4348330 5.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77649364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031782 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199615 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16523555 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49304070 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9588345 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 552618 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1678659 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1021998 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90748 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56218321 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303479 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1678659 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17458336 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19025484 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27018348 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9133613 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3332888 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53403158 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13481 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 625557 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2163090 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 470 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55533202 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243132036 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243084049 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47987 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40330710 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15202492 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 427890 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 379964 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6776397 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10330089 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6786263 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1056196 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1308824 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49548242 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1040790 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63116713 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95333 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10484602 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26435485 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 265976 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77649364 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.812843 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.518782 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54835526 70.62% 70.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7206411 9.28% 79.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3684013 4.74% 84.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3126457 4.03% 88.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6296301 8.11% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1390393 1.79% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 812577 1.05% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231214 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66472 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77649364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 32527 0.73% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4227565 94.61% 95.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208097 4.66% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195790 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29888266 47.35% 47.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47148 0.07% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.74% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26756071 42.39% 90.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6228206 9.87% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63116713 # Type of FU issued -system.cpu0.iq.rate 0.263933 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4468193 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070793 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208483702 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61082486 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44086612 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12401 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6581 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5541 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67382548 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6568 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 320496 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued +system.cpu0.iq.rate 0.264111 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2269255 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15997 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 887357 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17163539 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367436 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1678659 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14252559 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 235358 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50705856 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 106082 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10330089 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6786263 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 740769 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 57048 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3493 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15997 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 185463 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146727 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 332190 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61942896 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26397875 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1173817 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116824 # number of nop insts executed -system.cpu0.iew.exec_refs 32569629 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6012851 # Number of branches executed -system.cpu0.iew.exec_stores 6171754 # Number of stores executed -system.cpu0.iew.exec_rate 0.259024 # Inst execution rate -system.cpu0.iew.wb_sent 61414090 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44092153 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24268667 # num instructions producing a value -system.cpu0.iew.wb_consumers 44593954 # num instructions consuming a value +system.cpu0.iew.exec_nop 123681 # number of nop insts executed +system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5821167 # Number of branches executed +system.cpu0.iew.exec_stores 6250185 # Number of stores executed +system.cpu0.iew.exec_rate 0.258616 # Inst execution rate +system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23943541 # num instructions producing a value +system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184379 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544214 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10328850 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 774814 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 289634 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75970705 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.524893 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.506232 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61754720 81.29% 81.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6906334 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2042059 2.69% 93.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1137631 1.50% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1039888 1.37% 95.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547173 0.72% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 697067 0.92% 97.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 371357 0.49% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1474476 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61770131 81.47% 81.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6789372 8.95% 90.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2077521 2.74% 93.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1107875 1.46% 94.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1001712 1.32% 95.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 557795 0.74% 96.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 684831 0.90% 97.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 401810 0.53% 98.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1431135 1.89% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75970705 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31216883 # Number of instructions committed -system.cpu0.commit.committedOps 39876471 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75822182 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30629038 # Number of instructions committed +system.cpu0.commit.committedOps 39434598 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13959740 # Number of memory references committed -system.cpu0.commit.loads 8060834 # Number of loads committed -system.cpu0.commit.membars 211745 # Number of memory barriers committed -system.cpu0.commit.branches 5194005 # Number of branches committed -system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35234084 # Number of committed integer instructions. -system.cpu0.commit.function_calls 512673 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1474476 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13932896 # Number of memory references committed +system.cpu0.commit.loads 7948043 # Number of loads committed +system.cpu0.commit.membars 201908 # Number of memory barriers committed +system.cpu0.commit.branches 4992421 # Number of branches committed +system.cpu0.commit.fp_insts 5469 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34986832 # Number of committed integer instructions. +system.cpu0.commit.function_calls 490811 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1431135 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123727475 # The number of ROB reads -system.cpu0.rob.rob_writes 102131366 # The number of ROB writes -system.cpu0.timesIdled 883402 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161489905 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289692501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31137553 # Number of Instructions Simulated -system.cpu0.committedOps 39797141 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31137553 # Number of Instructions Simulated -system.cpu0.cpi 7.680092 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.680092 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130207 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130207 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280388173 # number of integer regfile reads -system.cpu0.int_regfile_writes 45343219 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22835 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19826 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15490012 # number of misc regfile reads -system.cpu0.misc_regfile_writes 428542 # number of misc regfile writes -system.cpu0.icache.replacements 983837 # number of replacements -system.cpu0.icache.tagsinuse 511.608434 # Cycle average of tags in use -system.cpu0.icache.total_refs 11044105 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984349 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.219705 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.557711 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 155.050723 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696402 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302833 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5554519 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5489586 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11044105 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5554519 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5489586 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11044105 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5554519 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5489586 # number of overall hits -system.cpu0.icache.overall_hits::total 11044105 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539384 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 525964 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539384 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 525964 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539384 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 525964 # number of overall misses -system.cpu0.icache.overall_misses::total 1065348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306834994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6986624997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14293459991 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7306834994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6986624997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14293459991 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7306834994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6986624997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14293459991 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6093903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 6015550 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12109453 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6093903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 6015550 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12109453 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6093903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 6015550 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12109453 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088512 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087434 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.087977 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088512 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087434 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.087977 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088512 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087434 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.087977 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13546.629107 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13283.466163 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.705143 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13416.705143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13546.629107 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13416.705143 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5066 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 940 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 333 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.213213 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 940 # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 124149615 # The number of ROB reads +system.cpu0.rob.rob_writes 103265708 # The number of ROB writes +system.cpu0.timesIdled 892080 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 160264371 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2282472691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30545540 # Number of Instructions Simulated +system.cpu0.committedOps 39351100 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30545540 # Number of Instructions Simulated +system.cpu0.cpi 7.789030 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.789030 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.128386 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.128386 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 279175646 # number of integer regfile reads +system.cpu0.int_regfile_writes 45166448 # number of integer regfile writes +system.cpu0.fp_regfile_reads 23007 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19790 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15439802 # number of misc regfile reads +system.cpu0.misc_regfile_writes 404480 # number of misc regfile writes +system.cpu0.icache.replacements 984632 # number of replacements +system.cpu0.icache.tagsinuse 511.564307 # Cycle average of tags in use +system.cpu0.icache.total_refs 10914069 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 985144 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.078653 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6937099000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 153.323923 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 358.240384 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.299461 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.699688 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999149 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5710872 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5203197 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10914069 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5710872 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5203197 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10914069 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5710872 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5203197 # number of overall hits +system.cpu0.icache.overall_hits::total 10914069 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 548607 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 517852 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066459 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 548607 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 517852 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1066459 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 548607 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 517852 # number of overall misses +system.cpu0.icache.overall_misses::total 1066459 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7528963984 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7029593986 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14558557970 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7528963984 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 7029593986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14558557970 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7528963984 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7029593986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14558557970 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6259479 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5721049 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11980528 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6259479 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5721049 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11980528 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6259479 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5721049 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11980528 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087644 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090517 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.089016 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087644 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090517 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.089016 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087644 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090517 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.089016 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13723.784028 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13574.523196 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13651.305835 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13651.305835 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13651.305835 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7371 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 409 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.022005 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41253 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39724 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80977 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41253 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39724 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80977 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41253 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39724 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80977 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498131 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486240 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984371 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 498131 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 486240 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984371 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 498131 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 486240 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984371 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5959731494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5688421497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648152991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5959731494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5688421497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11648152991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5959731494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5688421497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11648152991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081289 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081289 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081289 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11964.185112 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11698.793799 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11833.092392 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11964.185112 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11698.793799 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11833.092392 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11964.185112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11698.793799 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11833.092392 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41633 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39659 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 81292 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41633 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39659 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 81292 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41633 # 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643632 # number of replacements -system.cpu0.dcache.tagsinuse 511.992721 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21539031 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644144 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.438223 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 318.855973 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 193.136748 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.622766 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.377220 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7102728 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6679613 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13782341 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3764279 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3497770 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7262049 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125347 # 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Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 48810000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 193.724997 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 318.267071 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.378369 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.621615 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7114161 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6663960 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13778121 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3647393 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3614436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261829 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94557500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187486000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1902095 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1808948 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711043 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1902095 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1808948 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711043 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5421439000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6015207500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11436646500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76471634301 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 66135076354 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 142606710655 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98609000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 88268000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186877000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 77000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 155000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 60098211346 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 65800734293 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125898945639 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 60098211346 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 65800734293 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125898945639 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7534890 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6997319 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14532209 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5169161 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5053751 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222912 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132212 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 125382 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257594 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120155 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247628 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12704051 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12051070 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24755121 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12704051 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12051070 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24755121 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057355 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045404 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051600 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.271781 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.307886 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289630 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051924 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053995 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052932 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106860174570 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109111895021 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215972069591 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028239 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024754 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026561 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023281 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025434 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024345 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046516 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048356 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025646 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025646 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13610.576652 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13541.952208 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13579.782066 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33576.301968 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34401.903281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.691752 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11743.414634 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12210.951674 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11975.517891 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8272921091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7745751501 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16018672592 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8272921091 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7745751501 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16018672592 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90317850501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 92017839000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182335689501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18608772616 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14303930851 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32912703467 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 156000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 156000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 108926623117 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106321769851 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215248392968 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024709 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028567 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026587 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024933 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023757 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051475 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043710 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047379 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000043 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000038 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1322,324 +1745,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7054454 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5657096 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 345347 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4549622 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3820237 # Number of BTB hits +system.cpu1.branchPred.lookups 7176614 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 83.968229 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 674890 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35092 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25326740 # DTB read hits -system.cpu1.dtb.read_misses 36422 # DTB read misses -system.cpu1.dtb.write_hits 5812086 # DTB write hits -system.cpu1.dtb.write_misses 9253 # DTB write misses -system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25652921 # DTB read hits +system.cpu1.dtb.read_misses 36442 # DTB read misses +system.cpu1.dtb.write_hits 5708219 # DTB write hits +system.cpu1.dtb.write_misses 9483 # DTB write misses +system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5525 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1356 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25363162 # DTB read accesses -system.cpu1.dtb.write_accesses 5821339 # DTB write accesses +system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25689363 # DTB read accesses +system.cpu1.dtb.write_accesses 5717702 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31138826 # DTB hits -system.cpu1.dtb.misses 45675 # DTB misses -system.cpu1.dtb.accesses 31184501 # DTB accesses -system.cpu1.itb.inst_hits 6017589 # ITB inst hits -system.cpu1.itb.inst_misses 6780 # ITB inst misses +system.cpu1.dtb.hits 31361140 # DTB hits +system.cpu1.dtb.misses 45925 # DTB misses +system.cpu1.dtb.accesses 31407065 # DTB accesses +system.cpu1.itb.inst_hits 5722854 # ITB inst hits +system.cpu1.itb.inst_misses 6790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6024369 # ITB inst accesses -system.cpu1.itb.hits 6017589 # DTB hits -system.cpu1.itb.misses 6780 # DTB misses -system.cpu1.itb.accesses 6024369 # DTB accesses -system.cpu1.numCycles 234207757 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses +system.cpu1.itb.hits 5722854 # DTB hits +system.cpu1.itb.misses 6790 # DTB misses +system.cpu1.itb.accesses 5729644 # DTB accesses +system.cpu1.numCycles 238719781 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15218240 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46698589 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7054454 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4495127 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10302624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2620130 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82175 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 46347162 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2022 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43841 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1251673 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 166 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 6015552 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 445431 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2871 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75042047 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773320 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138232 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64747187 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 625900 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 833929 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1208466 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1046555 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 538335 0.72% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1373859 1.83% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351234 0.47% 94.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4316582 5.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75042047 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030120 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199390 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16229024 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47299345 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9347740 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 453958 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1709750 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 948283 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85990 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54953007 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286020 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1709750 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17168291 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18529773 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25747808 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8785346 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3098929 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51771461 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7122 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 486511 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2115721 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53850166 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237651325 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237608915 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42410 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38062786 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15787379 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 405266 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 358955 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6248671 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9866186 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6689314 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 887473 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1140418 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47717114 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 944883 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60871845 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81909 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10575332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 28005773 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 237169 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75042047 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811170 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521401 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53284770 71.01% 71.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6662382 8.88% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3536622 4.71% 84.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2873956 3.83% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6247532 8.33% 96.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1425164 1.90% 98.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 742478 0.99% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209609 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59534 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75042047 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 26737 0.61% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4146600 94.82% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199958 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167876 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28487291 46.80% 47.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46424 0.08% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 902 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26063934 42.82% 89.97% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6105398 10.03% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60871845 # Type of FU issued -system.cpu1.iq.rate 0.259905 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4373296 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071844 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201275709 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59245662 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41829457 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10720 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5895 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4750 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65071600 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5665 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 304013 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued +system.cpu1.iq.rate 0.256467 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2271620 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3204 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14692 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 855526 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16940305 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 458975 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1709750 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13959970 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 234377 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48767354 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 97921 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9866186 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6689314 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 671038 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52079 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3815 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14692 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167743 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133124 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300867 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59498020 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25657253 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1373825 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105357 # number of nop insts executed -system.cpu1.iew.exec_refs 31711723 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5535621 # Number of branches executed -system.cpu1.iew.exec_stores 6054470 # Number of stores executed -system.cpu1.iew.exec_rate 0.254039 # Inst execution rate -system.cpu1.iew.wb_sent 58916799 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41834207 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22806182 # num instructions producing a value -system.cpu1.iew.wb_consumers 41818913 # num instructions consuming a value +system.cpu1.iew.exec_nop 99212 # number of nop insts executed +system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5705434 # Number of branches executed +system.cpu1.iew.exec_stores 5976719 # Number of stores executed +system.cpu1.iew.exec_rate 0.252085 # Inst execution rate +system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23216135 # num instructions producing a value +system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178620 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545356 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10492813 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 707714 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260708 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73332297 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516509 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496867 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59797837 81.54% 81.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6663272 9.09% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1912982 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1016048 1.39% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959954 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 526368 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 702800 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 373366 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1379670 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73332297 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29243924 # Number of instructions committed -system.cpu1.commit.committedOps 37876758 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29838157 # Number of instructions committed +system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13428354 # Number of memory references committed -system.cpu1.commit.loads 7594566 # Number of loads committed -system.cpu1.commit.membars 191899 # Number of memory barriers committed -system.cpu1.commit.branches 4767702 # Number of branches committed -system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33624060 # Number of committed integer instructions. -system.cpu1.commit.function_calls 478655 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1379670 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13458430 # Number of memory references committed +system.cpu1.commit.loads 7709539 # Number of loads committed +system.cpu1.commit.membars 201879 # Number of memory barriers committed +system.cpu1.commit.branches 4970440 # Number of branches committed +system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions. +system.cpu1.commit.function_calls 500692 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119446868 # The number of ROB reads -system.cpu1.rob.rob_writes 98500710 # The number of ROB writes -system.cpu1.timesIdled 873517 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159165710 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285782593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29172873 # Number of Instructions Simulated -system.cpu1.committedOps 37805707 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29172873 # Number of Instructions Simulated -system.cpu1.cpi 8.028272 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.028272 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124560 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124560 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269572472 # number of integer regfile reads -system.cpu1.int_regfile_writes 42951903 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22113 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14815337 # number of misc regfile reads -system.cpu1.misc_regfile_writes 403940 # number of misc regfile writes +system.cpu1.rob.rob_reads 120414089 # The number of ROB reads +system.cpu1.rob.rob_writes 97409741 # The number of ROB writes +system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29771274 # Number of Instructions Simulated +system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated +system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads +system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads +system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1654,17 +2077,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192618547941 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192618547941 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index a80cc588c..fb76d8786 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,154 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.610012 # Number of seconds simulated -sim_ticks 2610011895000 # Number of ticks simulated -final_tick 2610011895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.627154 # Number of seconds simulated +sim_ticks 2627154206500 # Number of ticks simulated +final_tick 2627154206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 531747 # Simulator instruction rate (inst/s) -host_op_rate 676644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23052454652 # Simulator tick rate (ticks/s) -host_mem_usage 397728 # Number of bytes of host memory used -host_seconds 113.22 # Real time elapsed on the host -sim_insts 60204721 # Number of instructions simulated -sim_ops 76610045 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +host_inst_rate 361221 # Simulator instruction rate (inst/s) +host_op_rate 459651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15759970234 # Simulator tick rate (ticks/s) +host_mem_usage 398468 # Number of bytes of host memory used +host_seconds 166.70 # Real time elapsed on the host +sim_insts 60214798 # Number of instructions simulated +sim_ops 76622863 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 356960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4558796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 347904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4486256 # Number of bytes read from this memory -system.physmem.bytes_read::total 132433500 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 356960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 347904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1510336 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1505932 # Number of bytes written to this memory -system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 292384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4914704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 411968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4151472 # Number of bytes read from this memory +system.physmem.bytes_read::total 134026976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 292384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 411968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3695296 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1534856 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1481296 # Number of bytes written to this memory +system.physmem.bytes_written::total 6711448 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11780 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 71264 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 70124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 377584 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 376483 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47004917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 10771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 76826 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 64893 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690962 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57739 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 383714 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 370324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811777 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47296902 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 136766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1746657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 133296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1718864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50740573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 136766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 133296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1407135 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 578670 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 576983 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2562788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1407135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47004917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 111293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1870733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 156812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1580216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51016029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 111293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 156812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1406578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 584228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2554646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1406578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47296902 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 136766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2325327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 133296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2295847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53303362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494031 # Total number of read requests seen -system.physmem.writeReqs 811452 # Total number of write requests seen -system.physmem.cpureqs 213827 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991617984 # Total number of bytes read from memory -system.physmem.bytesWritten 51932928 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132433500 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 27 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4514 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 974843 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 968563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 968385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 968241 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 967643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967509 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50998 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50782 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50199 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 111293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2454961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 156812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2144057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53570675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690962 # Total number of read requests seen +system.physmem.writeReqs 811777 # Total number of write requests seen +system.physmem.cpureqs 214505 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1004221568 # Total number of bytes read from memory +system.physmem.bytesWritten 51953728 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 134026976 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6711448 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 980549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 980310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 980142 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 980447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 986846 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 980559 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 980589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 980289 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 980613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 980424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 979732 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 979654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 980193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 980214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 980246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 980129 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51073 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51427 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51034 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50704 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50829 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2610007487000 # Total gap between requests +system.physmem.totGap 2627149788000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6679 # Categorize read packet sizes -system.physmem.readPktSize::3 15335424 # Categorize read packet sizes +system.physmem.readPktSize::2 6680 # Categorize read packet sizes +system.physmem.readPktSize::3 15532032 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 151928 # Categorize read packet sizes +system.physmem.readPktSize::6 152250 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 754067 # Categorize write packet sizes +system.physmem.writePktSize::2 754038 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57385 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1116599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3652366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2754414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2758656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2734326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 61705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 111551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 162629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57739 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1134037 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 977508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1022657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3835405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2876027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2874808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2829459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 16845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 41555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -164,258 +152,521 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 338127200750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 432998808250 # Sum of mem lat for all requests -system.physmem.totBusLat 77470020000 # Total cycles spent in databus access -system.physmem.totBankLat 17401587500 # Total cycles spent in bank access -system.physmem.avgQLat 21823.10 # Average queueing delay per request -system.physmem.avgBankLat 1123.12 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 38107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27715.971974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2557.155392 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33302.761922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5424 14.23% 14.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3316 8.70% 22.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2198 5.77% 28.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1686 4.42% 33.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1157 3.04% 36.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1029 2.70% 38.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 812 2.13% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 726 1.91% 42.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 578 1.52% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 463 1.21% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 465 1.22% 46.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 413 1.08% 47.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 261 0.68% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 269 0.71% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 229 0.60% 49.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 239 0.63% 50.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 136 0.36% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 99 0.26% 51.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 99 0.26% 51.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 86 0.23% 52.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 761 2.00% 54.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 211 0.55% 54.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 139 0.36% 55.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 123 0.32% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 64 0.17% 55.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 78 0.20% 56.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 56 0.15% 56.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 58 0.15% 56.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 48 0.13% 56.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 69 0.18% 56.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 34 0.09% 56.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 27 0.07% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 25 0.07% 56.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 9 0.02% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 23 0.06% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 23 0.06% 57.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 14 0.04% 57.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 8 0.02% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 9 0.02% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 5 0.01% 57.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 6 0.02% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 4 0.01% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 8 0.02% 57.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 4 0.01% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 7 0.02% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 11 0.03% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 9 0.02% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 3 0.01% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 10 0.03% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 6 0.02% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 4 0.01% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 4 0.01% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 5 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 3 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 1 0.00% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 3 0.01% 57.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 2 0.01% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 4 0.01% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 2 0.01% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 4 0.01% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 2 0.01% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 3 0.01% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 1 0.00% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 23 0.06% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 4 0.01% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 3 0.01% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 2 0.01% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 18 0.05% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 5 0.01% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 1 0.00% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 3 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 4 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 6 0.02% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 3 0.01% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 5 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 310 0.81% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9855 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 17 0.04% 59.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 2 0.01% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 2 0.01% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 1 0.00% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 2 0.01% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14911 1 0.00% 59.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 2 0.01% 59.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18751 2 0.01% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 1 0.00% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 1 0.00% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 3 0.01% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 3 0.01% 59.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 1 0.00% 59.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 1 0.00% 59.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25920-25983 1 0.00% 59.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 59.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 3 0.01% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 1 0.00% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 59.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31103 2 0.01% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 1 0.00% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 1 0.00% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33472-33535 2 0.01% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 19 0.05% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35391 1 0.00% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36927 2 0.01% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38207 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-41023 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 2 0.01% 59.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 59.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48447 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50751 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51519 1 0.00% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52480-52543 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56128-56191 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58687 1 0.00% 59.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60032-60095 1 0.00% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60672-60735 1 0.00% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 1 0.00% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 15122 39.68% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71808-71871 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::82176-82239 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::88064-88127 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99712-99775 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 356 0.93% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38107 # Bytes accessed per row activation +system.physmem.totQLat 304254816750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 398977768000 # Sum of mem lat for all requests +system.physmem.totBusLat 78454680000 # Total cycles spent in databus access +system.physmem.totBankLat 16268271250 # Total cycles spent in bank access +system.physmem.avgQLat 19390.48 # Average queueing delay per request +system.physmem.avgBankLat 1036.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27946.22 # Average memory access latency -system.physmem.avgRdBW 379.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25427.28 # Average memory access latency +system.physmem.avgRdBW 382.25 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.78 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.12 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.25 # Average write queue length over time -system.physmem.readRowHits 15419474 # Number of row buffer hits during reads -system.physmem.writeRowHits 794097 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.86 # Row buffer hit rate for writes -system.physmem.avgGap 160069.31 # Average gap between requests -system.l2c.replacements 61815 # number of replacements -system.l2c.tagsinuse 50922.556971 # Cycle average of tags in use -system.l2c.total_refs 1697645 # Total number of references to valid blocks. -system.l2c.sampled_refs 127200 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.346266 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2558113998500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37911.407860 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000643 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3494.638706 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3026.772488 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3500.625095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2989.111995 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.578482 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.physmem.busUtil 3.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 1.26 # Average write queue length over time +system.physmem.readRowHits 15666209 # Number of row buffer hits during reads +system.physmem.writeRowHits 798397 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.35 # Row buffer hit rate for writes +system.physmem.avgGap 159194.77 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54483503 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743616 # Transaction distribution +system.membus.trans_dist::ReadResp 16743616 # Transaction distribution +system.membus.trans_dist::WriteReq 763392 # Transaction distribution +system.membus.trans_dist::WriteResp 763392 # Transaction distribution +system.membus.trans_dist::Writeback 57739 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 131423 # Transaction distribution +system.membus.trans_dist::ReadExResp 131423 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32956771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343633 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16482168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18880309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 140738424 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 143136565 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143136565 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1225633000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 18165198500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer3.occupancy 3755000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4987617364 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 35065696500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -556,10 +803,6 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -571,137 +814,329 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 52848676 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471696 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471696 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596576 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1725238 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5754024 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 19969 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50318 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7549549 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54758516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83805889 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79212 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 138672017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138672017 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 169604 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4809056500 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3862257000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4394586000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 12869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 30515000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48206783 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution +system.iobus.trans_dist::WriteReq 8167 # Transaction distribution +system.iobus.trans_dist::WriteResp 8167 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646653 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 31064064000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7403435 # DTB read hits -system.cpu0.dtb.read_misses 6873 # DTB read misses -system.cpu0.dtb.write_hits 5501198 # DTB write hits -system.cpu0.dtb.write_misses 1842 # DTB write misses -system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7331530 # DTB read hits +system.cpu0.dtb.read_misses 6749 # DTB read misses +system.cpu0.dtb.write_hits 5629181 # DTB write hits +system.cpu0.dtb.write_misses 1838 # DTB write misses +system.cpu0.dtb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 225 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7410308 # DTB read accesses -system.cpu0.dtb.write_accesses 5503040 # DTB write accesses +system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7338279 # DTB read accesses +system.cpu0.dtb.write_accesses 5631019 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12904633 # DTB hits -system.cpu0.dtb.misses 8715 # DTB misses -system.cpu0.dtb.accesses 12913348 # DTB accesses -system.cpu0.itb.inst_hits 30303054 # ITB inst hits -system.cpu0.itb.inst_misses 3598 # ITB inst misses +system.cpu0.dtb.hits 12960711 # DTB hits +system.cpu0.dtb.misses 8587 # DTB misses +system.cpu0.dtb.accesses 12969298 # DTB accesses +system.cpu0.itb.inst_hits 29905877 # ITB inst hits +system.cpu0.itb.inst_misses 3541 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2696 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2713 # 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number of times the floating registers were written -system.cpu0.num_mem_refs 13487423 # number of memory refs -system.cpu0.num_load_insts 7732203 # Number of load instructions -system.cpu0.num_store_insts 5755220 # Number of store instructions -system.cpu0.num_idle_cycles -6063478143.749568 # Number of idle cycles -system.cpu0.num_busy_cycles 8731821098.749567 # Number of busy cycles -system.cpu0.not_idle_fraction 3.272376 # Percentage of non-idle cycles -system.cpu0.idle_fraction -2.272376 # Percentage of idle cycles +system.cpu0.committedInsts 29354437 # Number of instructions committed +system.cpu0.committedOps 37594269 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33819709 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4399 # Number of float alu accesses +system.cpu0.num_func_calls 1050996 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3901744 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33819709 # number of integer instructions +system.cpu0.num_fp_insts 4399 # number of float instructions +system.cpu0.num_int_register_reads 193860060 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36222671 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 2980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1422 # number of times the floating registers were written +system.cpu0.num_mem_refs 13528220 # number of memory refs +system.cpu0.num_load_insts 7652095 # Number of load instructions +system.cpu0.num_store_insts 5876125 # Number of store instructions +system.cpu0.num_idle_cycles 3959269974.685009 # Number of idle cycles +system.cpu0.num_busy_cycles -1333655320.685009 # Number of busy cycles +system.cpu0.not_idle_fraction -0.507940 # Percentage of non-idle cycles +system.cpu0.idle_fraction 1.507940 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83014 # 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Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 70.788428 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 19951126000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 211.269662 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 299.611865 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.412636 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.585179 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997815 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29481581 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 31170510 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60652091 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29481581 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 31170510 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.977374 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13926.334992 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13764.720918 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,158 +1145,158 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 413545 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 442640 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5158283000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10080107000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4921824000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5158283000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10080107000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 429084500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 429084500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014188 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013686 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11764.720918 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # 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Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.725538 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999830 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6510445 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6686708 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13197153 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4886816 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5087431 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974247 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 106752 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129570 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236322 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112519 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135213 # 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average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13593.111910 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21483.311702 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21483.311702 # average overall miss latency +system.cpu0.dcache.replacements 627777 # number of replacements +system.cpu0.dcache.tagsinuse 511.879644 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23662359 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 628289 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.661584 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 650252000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 250.372579 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 261.507065 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.489009 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.510756 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999765 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6433193 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6766702 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13199895 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4991648 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4983805 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9975453 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044973 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046412 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026382 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025713 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026043 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026382 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025713 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026043 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14804.377653 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14618.131709 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14708.568272 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43235.379455 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40410.705667 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41880.049431 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13481.052275 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14456.887299 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13955.351709 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25689.890188 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25689.890188 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,159 +1305,151 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596298 # number of writebacks -system.cpu0.dcache.writebacks::total 596298 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186239 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182677 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368916 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 123980 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126580 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250560 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5767 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5644 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11411 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 310219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 309257 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619476 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 310219 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 309257 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619476 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2283659500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2226518000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4510177500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3776729000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3782537500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7559266500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68521500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63767500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132289000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6060388500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6009055500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12069444000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6060388500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6009055500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12069444000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91364168500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90730673500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182094842000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9290730500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9409303000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18700033500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654899000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100139976500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794875500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027811 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027194 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024743 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024277 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051254 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046062 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12261.983258 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.277670 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.486290 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.405227 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29882.584137 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.486351 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11881.654240 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11298.281361 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.111910 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596576 # number of writebacks +system.cpu0.dcache.writebacks::total 596576 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 179297 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 189949 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369246 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130279 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 120170 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250449 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5911 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5590 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11501 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 309576 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 310119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619695 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 309576 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 310119 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619695 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295786500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2396801500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4692588000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372104000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4615814500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9987918500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67864500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69634000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137498500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7667890500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7012616000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14680506500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7667890500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7012616000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14680506500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527278500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90544684500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182071963000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13203337000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13032051000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235388000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104730615500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103576735500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208307351000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027115 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027305 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023544 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047860 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044973 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046412 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12804.377653 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.131709 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12708.568272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41235.379455 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38410.705667 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39880.049431 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11481.052275 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12456.887299 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11955.351709 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7594461 # DTB read hits -system.cpu1.dtb.read_misses 6935 # DTB read misses -system.cpu1.dtb.write_hits 5731015 # DTB write hits -system.cpu1.dtb.write_misses 1760 # DTB write misses -system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7669515 # DTB read hits +system.cpu1.dtb.read_misses 7262 # DTB read misses +system.cpu1.dtb.write_hits 5604176 # DTB write hits +system.cpu1.dtb.write_misses 1826 # DTB write misses +system.cpu1.dtb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6595 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7601396 # DTB read accesses -system.cpu1.dtb.write_accesses 5732775 # DTB write accesses +system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7676777 # DTB read accesses +system.cpu1.dtb.write_accesses 5606002 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13325476 # DTB hits -system.cpu1.dtb.misses 8695 # DTB misses -system.cpu1.dtb.accesses 13334171 # DTB accesses -system.cpu1.itb.inst_hits 31195731 # ITB inst hits -system.cpu1.itb.inst_misses 3619 # ITB inst misses +system.cpu1.dtb.hits 13273691 # DTB hits +system.cpu1.dtb.misses 9088 # DTB misses +system.cpu1.dtb.accesses 13282779 # DTB accesses +system.cpu1.itb.inst_hits 31603022 # ITB inst hits +system.cpu1.itb.inst_misses 3724 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1246 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2687 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2827 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31199350 # ITB inst accesses -system.cpu1.itb.hits 31195731 # DTB hits -system.cpu1.itb.misses 3619 # DTB misses -system.cpu1.itb.accesses 31199350 # DTB accesses -system.cpu1.numCycles 2551680835 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31606746 # ITB inst accesses +system.cpu1.itb.hits 31603022 # DTB hits +system.cpu1.itb.misses 3724 # DTB misses +system.cpu1.itb.accesses 31606746 # DTB accesses +system.cpu1.numCycles 2628693759 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30572055 # Number of instructions committed -system.cpu1.committedOps 38927185 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34988619 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5077 # Number of float alu accesses -system.cpu1.num_func_calls 1115365 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4021820 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34988619 # number of integer instructions -system.cpu1.num_fp_insts 5077 # number of float instructions -system.cpu1.num_int_register_reads 200559291 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37663256 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3651 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu1.num_mem_refs 13910241 # number of memory refs -system.cpu1.num_load_insts 7929873 # Number of load instructions -system.cpu1.num_store_insts 5980368 # Number of store instructions -system.cpu1.num_idle_cycles 10585260303.338047 # Number of idle cycles -system.cpu1.num_busy_cycles -8033579468.338046 # Number of busy cycles -system.cpu1.not_idle_fraction -3.148348 # Percentage of non-idle cycles -system.cpu1.idle_fraction 4.148348 # Percentage of idle cycles +system.cpu1.committedInsts 30860361 # Number of instructions committed +system.cpu1.committedOps 39028594 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35068610 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses +system.cpu1.num_func_calls 1089512 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4048013 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35068610 # number of integer instructions +system.cpu1.num_fp_insts 5870 # number of float instructions +system.cpu1.num_int_register_reads 201015882 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37978161 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4513 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written +system.cpu1.num_mem_refs 13873832 # number of memory refs +system.cpu1.num_load_insts 8013211 # Number of load instructions +system.cpu1.num_store_insts 5860621 # Number of store instructions +system.cpu1.num_idle_cycles 952679619.816103 # Number of idle cycles +system.cpu1.num_busy_cycles 1676014139.183897 # Number of busy cycles +system.cpu1.not_idle_fraction 0.637584 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.362416 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.replacements 0 # number of replacements @@ -1039,10 +1466,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947261004 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1195947261004 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1482619780500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1482619780500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |