diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
6 files changed, 6868 insertions, 6889 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 46a681edb..4d949983c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,126 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523205 # Number of seconds simulated -sim_ticks 2523204701000 # Number of ticks simulated -final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533245 # Number of seconds simulated +sim_ticks 2533245380500 # Number of ticks simulated +final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41110 # Simulator instruction rate (inst/s) -host_op_rate 52896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1720016966 # Simulator tick rate (ticks/s) -host_mem_usage 452892 # Number of bytes of host memory used -host_seconds 1466.97 # Real time elapsed on the host -sim_insts 60306320 # Number of instructions simulated -sim_ops 77597310 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 68339 # Simulator instruction rate (inst/s) +host_op_rate 87933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2870562080 # Simulator tick rate (ticks/s) +host_mem_usage 409768 # Number of bytes of host memory used +host_seconds 882.49 # Real time elapsed on the host +sim_insts 60308251 # Number of instructions simulated +sim_ops 77599937 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096856 # Total number of read requests seen -system.physmem.writeReqs 813138 # Total number of write requests seen -system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966198784 # Total number of bytes read from memory -system.physmem.bytesWritten 52040832 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis +system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096850 # Total number of read requests seen +system.physmem.writeReqs 813145 # Total number of write requests seen +system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966198400 # Total number of bytes read from memory +system.physmem.bytesWritten 52041280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523203522000 # Total gap between requests +system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533244279000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154612 # Categorize read packet sizes +system.physmem.readPktSize::6 154606 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1943854 # categorize write packet sizes +system.physmem.writePktSize::2 2927056 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59120 # categorize write packet sizes +system.physmem.writePktSize::6 59127 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -129,30 +117,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -184,61 +172,73 @@ system.physmem.wrQLenPdf::15 35354 # Wh system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests -system.physmem.totBusLat 60386192000 # Total cycles spent in databus access -system.physmem.totBankLat 16356620000 # Total cycles spent in bank access -system.physmem.avgQLat 21743.10 # Average queueing delay per request -system.physmem.avgBankLat 1083.47 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26826.57 # Average memory access latency -system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 10.68 # Average write queue length over time -system.physmem.readRowHits 15052450 # Number of row buffer hits during reads -system.physmem.writeRowHits 784654 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes -system.physmem.avgGap 158592.36 # Average gap between requests +system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests +system.physmem.totBusLat 75482595000 # Total cycles spent in databus access +system.physmem.totBankLat 16916941250 # Total cycles spent in bank access +system.physmem.avgQLat 26034.38 # Average queueing delay per request +system.physmem.avgBankLat 1120.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32154.97 # Average memory access latency +system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.avgWrQLen 12.52 # Average write queue length over time +system.physmem.readRowHits 15020214 # Number of row buffer hits during reads +system.physmem.writeRowHits 793069 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes +system.physmem.avgGap 159223.45 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14400111 # Number of BP lookups -system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits +system.cpu.branchPred.lookups 14667589 # Number of BP lookups +system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986991 # DTB read hits +system.cpu.checker.dtb.read_hits 14987593 # DTB read hits system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227488 # DTB write hits +system.cpu.checker.dtb.write_hits 11227866 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -249,13 +249,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994298 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229677 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994900 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11230055 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214479 # DTB hits +system.cpu.checker.dtb.hits 26215459 # DTB hits system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26223975 # DTB accesses -system.cpu.checker.itb.inst_hits 61480313 # ITB inst hits +system.cpu.checker.dtb.accesses 26224955 # DTB accesses +system.cpu.checker.itb.inst_hits 61482253 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -272,36 +272,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484784 # ITB inst accesses -system.cpu.checker.itb.hits 61480313 # DTB hits +system.cpu.checker.itb.inst_accesses 61486724 # ITB inst accesses +system.cpu.checker.itb.hits 61482253 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484784 # DTB accesses -system.cpu.checker.numCycles 77883110 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486724 # DTB accesses +system.cpu.checker.numCycles 77885746 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51212683 # DTB read hits -system.cpu.dtb.read_misses 73387 # DTB read misses -system.cpu.dtb.write_hits 11701466 # DTB write hits -system.cpu.dtb.write_misses 17011 # DTB write misses +system.cpu.dtb.read_hits 51389080 # DTB read hits +system.cpu.dtb.read_misses 73326 # DTB read misses +system.cpu.dtb.write_hits 11702658 # DTB write hits +system.cpu.dtb.write_misses 17128 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7759 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7749 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51286070 # DTB read accesses -system.cpu.dtb.write_accesses 11718477 # DTB write accesses +system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51462406 # DTB read accesses +system.cpu.dtb.write_accesses 11719786 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62914149 # DTB hits -system.cpu.dtb.misses 90398 # DTB misses -system.cpu.dtb.accesses 63004547 # DTB accesses -system.cpu.itb.inst_hits 11530598 # ITB inst hits -system.cpu.itb.inst_misses 11503 # ITB inst misses +system.cpu.dtb.hits 63091738 # DTB hits +system.cpu.dtb.misses 90454 # DTB misses +system.cpu.dtb.accesses 63182192 # DTB accesses +system.cpu.itb.inst_hits 12277036 # ITB inst hits +system.cpu.itb.inst_misses 11490 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -310,114 +310,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5166 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5150 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11542101 # ITB inst accesses -system.cpu.itb.hits 11530598 # DTB hits -system.cpu.itb.misses 11503 # DTB misses -system.cpu.itb.accesses 11542101 # DTB accesses -system.cpu.numCycles 469830472 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12288526 # ITB inst accesses +system.cpu.itb.hits 12277036 # DTB hits +system.cpu.itb.misses 11490 # DTB misses +system.cpu.itb.accesses 12288526 # DTB accesses +system.cpu.numCycles 472097236 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -445,383 +445,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued -system.cpu.iq.rate 0.261848 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued +system.cpu.iq.rate 0.263176 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221038 # number of nop insts executed -system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed -system.cpu.iew.exec_branches 11477980 # Number of branches executed -system.cpu.iew.exec_stores 12213052 # Number of stores executed -system.cpu.iew.exec_rate 0.257448 # Inst execution rate -system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47051195 # num instructions producing a value -system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value +system.cpu.iew.exec_nop 220577 # number of nop insts executed +system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed +system.cpu.iew.exec_branches 11563754 # Number of branches executed +system.cpu.iew.exec_stores 12214366 # Number of stores executed +system.cpu.iew.exec_rate 0.257379 # Inst execution rate +system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47207424 # num instructions producing a value +system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456701 # Number of instructions committed -system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458632 # Number of instructions committed +system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385892 # Number of memory references committed -system.cpu.commit.loads 15654083 # Number of loads committed -system.cpu.commit.membars 403583 # Number of memory barriers committed -system.cpu.commit.branches 9961154 # Number of branches committed +system.cpu.commit.refs 27386920 # Number of memory references committed +system.cpu.commit.loads 15654712 # Number of loads committed +system.cpu.commit.membars 403607 # Number of memory barriers committed +system.cpu.commit.branches 9961406 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68853054 # Number of committed integer instructions. -system.cpu.commit.function_calls 991222 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855494 # Number of committed integer instructions. +system.cpu.commit.function_calls 991273 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 238273902 # The number of ROB reads -system.cpu.rob.rob_writes 196332947 # The number of ROB writes -system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60306320 # Number of Instructions Simulated -system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated -system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547824488 # number of integer regfile reads -system.cpu.int_regfile_writes 87698032 # number of integer regfile writes -system.cpu.fp_regfile_reads 8340 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads -system.cpu.misc_regfile_writes 831851 # number of misc regfile writes -system.cpu.icache.replacements 979772 # number of replacements -system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use -system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits -system.cpu.icache.overall_hits::total 10466836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses -system.cpu.icache.overall_misses::total 1059904 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.rob.rob_reads 242460133 # The number of ROB reads +system.cpu.rob.rob_writes 201635862 # The number of ROB writes +system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60308251 # Number of Instructions Simulated +system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated +system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550197997 # number of integer regfile reads +system.cpu.int_regfile_writes 88410648 # number of integer regfile writes +system.cpu.fp_regfile_reads 8198 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads +system.cpu.misc_regfile_writes 831902 # number of misc regfile writes +system.cpu.icache.replacements 980802 # number of replacements +system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use +system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits +system.cpu.icache.overall_hits::total 11213050 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses +system.cpu.icache.overall_misses::total 1060138 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11335281493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11335281493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11335281493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085048 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78782 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 78782 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 78782 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 78782 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 78782 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 78782 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981356 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981356 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981356 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11396806498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11396806498 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11396806498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11396806498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11396806498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11396806498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079959 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079959 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079959 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11613.325336 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11613.325336 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563457 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000556 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64377 # number of replacements +system.cpu.l2cache.tagsinuse 51361.576516 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1911659 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129770 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.731132 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498200145000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36918.334944 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 32.795639 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8184.403113 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38151.749685 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38151.749685 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -942,161 +942,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289718 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052821 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052821 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.replacements 643060 # number of replacements +system.cpu.dcache.tagsinuse 511.992813 # Cycle average of tags in use +system.cpu.dcache.total_refs 21518829 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643572 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.436553 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 42289000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992813 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13762862 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13762862 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7262343 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7262343 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242888 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242888 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21025205 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21025205 # 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number of overall misses +system.cpu.dcache.overall_misses::total 3691646 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9676520000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9676520000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104419203240 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104419203240 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 271000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 271000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114095723240 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114095723240 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114095723240 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114095723240 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14494383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14494383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256426 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256426 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247620 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247620 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24716851 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24716851 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24716851 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24716851 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050469 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050469 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289570 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052795 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052795 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000077 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000077 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13227.945609 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13227.945609 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35275.268186 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35275.268186 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28001 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14318 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2522 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.102696 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 57.733871 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks -system.cpu.dcache.writebacks::total 607596 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607265 # number of writebacks +system.cpu.dcache.writebacks::total 607265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057299 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057299 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385397 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385397 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248950 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248950 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1118,16 +1118,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 572fe69c1..c67fcab1e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.092969 # Number of seconds simulated -sim_ticks 1092968826500 # Number of ticks simulated -final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.103053 # Number of seconds simulated +sim_ticks 1103052934500 # Number of ticks simulated +final_tick 1103052934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49884 # Simulator instruction rate (inst/s) -host_op_rate 64220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 885142778 # Simulator tick rate (ticks/s) -host_mem_usage 458008 # Number of bytes of host memory used -host_seconds 1234.79 # Real time elapsed on the host -sim_insts 61595972 # Number of instructions simulated -sim_ops 79298956 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 59 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 351 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 410 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 59 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 351 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 410 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 59 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 351 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 410 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 84555 # Simulator instruction rate (inst/s) +host_op_rate 108843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1514437253 # Simulator tick rate (ticks/s) +host_mem_usage 415912 # Number of bytes of host memory used +host_seconds 728.36 # Real time elapsed on the host +sim_insts 61586372 # Number of instructions simulated +sim_ops 79276491 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4356148 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 407360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5254000 # Number of bytes read from this memory -system.physmem.bytes_read::total 59186980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 407360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 816128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4265536 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 409536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368116 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5246000 # Number of bytes read from this memory +system.physmem.bytes_read::total 59190564 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268032 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7292880 # Number of bytes written to this memory +system.physmem.bytes_written::total 7295376 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6387 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68137 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66649 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81995 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257943 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66688 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823485 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44611322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 373998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3985610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 372710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4807090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54152487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 373998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 372710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 746707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3902706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15554 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2754282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6672542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3902706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44611322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 373998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4001164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 372710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7561372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60825028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257887 # Total number of read requests seen -system.physmem.writeReqs 823485 # Total number of write requests seen -system.physmem.cpureqs 281561 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400504768 # Total number of bytes read from memory -system.physmem.bytesWritten 52703040 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59186980 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7292880 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 99 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12576 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391078 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390638 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 390722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391599 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 391119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 391200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 390939 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51048 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50959 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51577 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51575 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51582 # Track writes on a per bank basis +system.physmem.num_writes::total 823524 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44203485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4755891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53660674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3869290 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15412 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729102 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6613804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3869290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44203485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3975436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 368026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7484993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60274478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257943 # Total number of read requests seen +system.physmem.writeReqs 823524 # Total number of write requests seen +system.physmem.cpureqs 281760 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400508352 # Total number of bytes read from memory +system.physmem.bytesWritten 52705536 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59190564 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7295376 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12603 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391392 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390909 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390860 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391269 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51695 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50999 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51498 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1176096 # Number of times wr buffer was full causing retry -system.physmem.totGap 1092967540000 # Total gap between requests +system.physmem.numWrRetry 2168609 # Number of times wr buffer was full causing retry +system.physmem.totGap 1103051731500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162934 # Categorize read packet sizes +system.physmem.readPktSize::6 162990 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1932932 # categorize write packet sizes +system.physmem.writePktSize::2 2925445 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66649 # categorize write packet sizes +system.physmem.writePktSize::6 66688 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -152,31 +134,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 12576 # categorize neither packet sizes +system.physmem.neitherpktsize::6 12603 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 496879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 431716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 387410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 401103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1104120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1111115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2162095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 27972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 13366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 13210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 24040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 31247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 494466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1085395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1097883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1063934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,291 +170,309 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31877 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 164150101325 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 197462743325 # Sum of mem lat for all requests -system.physmem.totBusLat 25031152000 # Total cycles spent in databus access -system.physmem.totBankLat 8281490000 # Total cycles spent in bank access -system.physmem.avgQLat 26231.33 # Average queueing delay per request -system.physmem.avgBankLat 1323.39 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31554.72 # Average memory access latency -system.physmem.avgRdBW 366.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 48.22 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 54.15 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.67 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 9.65 # Average write queue length over time -system.physmem.readRowHits 6229568 # Number of row buffer hits during reads -system.physmem.writeRowHits 789194 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 95.84 # Row buffer hit rate for writes -system.physmem.avgGap 154344.04 # Average gap between requests -system.l2c.replacements 72641 # number of replacements -system.l2c.tagsinuse 53795.283774 # Cycle average of tags in use -system.l2c.total_refs 1870380 # Total number of references to valid blocks. -system.l2c.sampled_refs 137779 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.575218 # Average number of references to valid blocks. +system.physmem.totQLat 198980528034 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 238811291784 # Sum of mem lat for all requests +system.physmem.totBusLat 31289360000 # Total cycles spent in databus access +system.physmem.totBankLat 8541403750 # Total cycles spent in bank access +system.physmem.avgQLat 31796.84 # Average queueing delay per request +system.physmem.avgBankLat 1364.91 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 38161.74 # Average memory access latency +system.physmem.avgRdBW 363.09 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.21 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.22 # Average read queue length over time +system.physmem.avgWrQLen 10.13 # Average write queue length over time +system.physmem.readRowHits 6214096 # Number of row buffer hits during reads +system.physmem.writeRowHits 800077 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes +system.physmem.avgGap 155765.99 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2632589947 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 294482820 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3488585424 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6685319684 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299167 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408113059 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2070313 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667167003 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167082649542 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050139238 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25325633830 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 26375773068 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299167 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458252297 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2070313 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 179992800833 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 193458422610 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036847 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030649 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017322 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810421 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837694 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821785 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769690 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.740072 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.757902 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566946 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567998 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567522 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097132 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097132 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45607.808701 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49524.094644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46147.540349 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.041821 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10169.721546 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.776953 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10050.587597 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.573171 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10045.529858 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36996.983462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41317.080364 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39366.945281 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -663,38 +663,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6012491 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4585363 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296577 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3765620 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2919015 # Number of BTB hits +system.cpu0.branchPred.lookups 6009414 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4584575 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296794 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3746905 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2916795 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.517514 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 674578 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28863 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.845448 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672462 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28490 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8918270 # DTB read hits -system.cpu0.dtb.read_misses 33761 # DTB read misses -system.cpu0.dtb.write_hits 5143475 # DTB write hits -system.cpu0.dtb.write_misses 6030 # DTB write misses +system.cpu0.dtb.read_hits 8911826 # DTB read hits +system.cpu0.dtb.read_misses 33481 # DTB read misses +system.cpu0.dtb.write_hits 5139826 # DTB write hits +system.cpu0.dtb.write_misses 6231 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2137 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1055 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 365 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2125 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 943 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 378 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 538 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8952031 # DTB read accesses -system.cpu0.dtb.write_accesses 5149505 # DTB write accesses +system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8945307 # DTB read accesses +system.cpu0.dtb.write_accesses 5146057 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14061745 # DTB hits -system.cpu0.dtb.misses 39791 # DTB misses -system.cpu0.dtb.accesses 14101536 # DTB accesses -system.cpu0.itb.inst_hits 4226389 # ITB inst hits -system.cpu0.itb.inst_misses 5148 # ITB inst misses +system.cpu0.dtb.hits 14051652 # DTB hits +system.cpu0.dtb.misses 39712 # DTB misses +system.cpu0.dtb.accesses 14091364 # DTB accesses +system.cpu0.itb.inst_hits 4224274 # ITB inst hits +system.cpu0.itb.inst_misses 5167 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -703,530 +703,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1370 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4231537 # ITB inst accesses -system.cpu0.itb.hits 4226389 # DTB hits -system.cpu0.itb.misses 5148 # DTB misses -system.cpu0.itb.accesses 4231537 # DTB accesses -system.cpu0.numCycles 67785734 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4229441 # ITB inst accesses +system.cpu0.itb.hits 4224274 # DTB hits +system.cpu0.itb.misses 5167 # DTB misses +system.cpu0.itb.accesses 4229441 # DTB accesses +system.cpu0.numCycles 67942321 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3593593 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7526717 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460555 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 62547 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20715231 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 54522 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85492 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4224665 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 156872 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2292 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41263116 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.003783 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.384047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11770700 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32037426 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6009414 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3589257 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7522750 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1459790 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61665 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20761422 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4873 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 52782 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85653 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4222584 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157713 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41308500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.002087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.382378 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33743827 81.78% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 566856 1.37% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818944 1.98% 85.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676218 1.64% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773991 1.88% 88.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 560705 1.36% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 670652 1.63% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352961 0.86% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098962 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33793144 81.81% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 566641 1.37% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818694 1.98% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676082 1.64% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 774764 1.88% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559890 1.36% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 668973 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352395 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3097917 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41263116 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088698 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472813 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12272697 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20662299 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6831890 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510283 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 985947 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 936613 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64715 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40060631 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213244 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 985947 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12836550 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5831447 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12738222 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6726939 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2144011 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38954643 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2110 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 419770 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1235917 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39310777 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175935751 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175901847 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 33904 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30931608 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8379168 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411632 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370766 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5325827 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7663556 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5690026 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120184 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1252239 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36870649 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 896350 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37273811 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81085 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6313763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13211798 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257333 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41263116 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.903320 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.511259 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41308500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088449 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471539 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12285141 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20700852 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6822655 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 515208 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 984644 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935535 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64887 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40031733 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213257 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 984644 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12853776 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5827758 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12754498 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6718585 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2169239 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38928303 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2058 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 438319 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1238743 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39288298 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175811025 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175776420 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34605 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30930446 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8357851 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411337 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370395 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5357325 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7655234 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5687790 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1133384 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1222152 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36851355 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895739 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37254250 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80693 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6299190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13209610 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256967 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41308500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901854 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.509387 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26116346 63.29% 63.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5727985 13.88% 77.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3164328 7.67% 84.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471717 5.99% 90.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2127646 5.16% 95.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 929575 2.25% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 487199 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 186194 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52126 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26145285 63.29% 63.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5753076 13.93% 77.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3163283 7.66% 84.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2484845 6.02% 90.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2098538 5.08% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 943313 2.28% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 484190 1.17% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 183544 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52426 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41263116 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41308500 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25847 2.42% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842941 78.82% 81.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200262 18.72% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25686 2.41% 2.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841970 78.85% 81.30% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 199670 18.70% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52409 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22347449 59.95% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46908 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9376305 25.16% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5450017 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22338200 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46968 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 17 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9368796 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447325 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37273811 # Type of FU issued -system.cpu0.iq.rate 0.549877 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1069503 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028693 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116992528 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44088817 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34369527 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8360 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3860 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38286519 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307254 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37254250 # Type of FU issued +system.cpu0.iq.rate 0.548322 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1067780 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028662 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116996499 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44054105 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34350443 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8454 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4728 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3907 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265398 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307211 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1385688 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2397 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13227 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 538655 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1378796 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2415 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13078 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537331 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192760 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5477 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192757 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5650 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 985947 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4198442 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 101973 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37885007 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 86572 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7663556 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5690026 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571892 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40888 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13227 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150955 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118096 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 269051 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36896358 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9233299 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377453 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 984644 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4190634 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100027 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37865226 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85653 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7655234 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5687790 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571722 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40568 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3395 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13078 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150532 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118543 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 269075 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36877414 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9226875 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376836 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118008 # number of nop insts executed -system.cpu0.iew.exec_refs 14636338 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4860481 # Number of branches executed -system.cpu0.iew.exec_stores 5403039 # Number of stores executed -system.cpu0.iew.exec_rate 0.544309 # Inst execution rate -system.cpu0.iew.wb_sent 36702505 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34373387 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18311880 # num instructions producing a value -system.cpu0.iew.wb_consumers 35235348 # num instructions consuming a value +system.cpu0.iew.exec_nop 118132 # number of nop insts executed +system.cpu0.iew.exec_refs 14626534 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4859341 # Number of branches executed +system.cpu0.iew.exec_stores 5399659 # Number of stores executed +system.cpu0.iew.exec_rate 0.542775 # Inst execution rate +system.cpu0.iew.wb_sent 36683533 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34354350 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18308250 # num instructions producing a value +system.cpu0.iew.wb_consumers 35218685 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.507089 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519702 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.505640 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519845 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6136748 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 639017 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232971 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40277169 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.776860 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.743491 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6121232 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638772 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232995 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40323856 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775878 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.738297 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28628964 71.08% 71.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5718437 14.20% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1895078 4.71% 89.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 977858 2.43% 92.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 774389 1.92% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 507385 1.26% 95.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386799 0.96% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 213802 0.53% 97.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1174457 2.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28652168 71.06% 71.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5718960 14.18% 85.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913940 4.75% 89.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 975658 2.42% 92.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 781823 1.94% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 527081 1.31% 95.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 383426 0.95% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 217091 0.54% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1153709 2.86% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40277169 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23678178 # Number of instructions committed -system.cpu0.commit.committedOps 31289712 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40323856 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23679897 # Number of instructions committed +system.cpu0.commit.committedOps 31286376 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11429239 # Number of memory references committed -system.cpu0.commit.loads 6277868 # Number of loads committed -system.cpu0.commit.membars 229666 # Number of memory barriers committed -system.cpu0.commit.branches 4244753 # Number of branches committed +system.cpu0.commit.refs 11426897 # Number of memory references committed +system.cpu0.commit.loads 6276438 # Number of loads committed +system.cpu0.commit.membars 229667 # Number of memory barriers committed +system.cpu0.commit.branches 4245099 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27646281 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489273 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1174457 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27642973 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489349 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1153709 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75678018 # The number of ROB reads -system.cpu0.rob.rob_writes 75840987 # The number of ROB writes -system.cpu0.timesIdled 360810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26522618 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2118110205 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23597436 # Number of Instructions Simulated -system.cpu0.committedOps 31208970 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23597436 # Number of Instructions Simulated -system.cpu0.cpi 2.872589 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.872589 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348118 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348118 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 172012852 # number of integer regfile reads -system.cpu0.int_regfile_writes 34120799 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads -system.cpu0.fp_regfile_writes 892 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13056447 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451188 # number of misc regfile writes -system.cpu0.icache.replacements 392549 # number of replacements -system.cpu0.icache.tagsinuse 511.079018 # Cycle average of tags in use -system.cpu0.icache.total_refs 3800627 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393061 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.669306 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6496390000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.079018 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998201 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998201 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3800627 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3800627 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3800627 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3800627 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3800627 # number of overall hits -system.cpu0.icache.overall_hits::total 3800627 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423907 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423907 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423907 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423907 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423907 # number of overall misses -system.cpu0.icache.overall_misses::total 423907 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5778558992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5778558992 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5778558992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5778558992 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5778558992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5778558992 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4224534 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4224534 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4224534 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4224534 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4224534 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4224534 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100344 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100344 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100344 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100344 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100344 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100344 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13631.666833 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13631.666833 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13631.666833 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13631.666833 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3110 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75726635 # The number of ROB reads +system.cpu0.rob.rob_writes 75801988 # The number of ROB writes +system.cpu0.timesIdled 359866 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26633821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138121828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23599155 # Number of Instructions Simulated +system.cpu0.committedOps 31205634 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23599155 # Number of Instructions Simulated +system.cpu0.cpi 2.879015 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.879015 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347341 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347341 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171917289 # number of integer regfile reads +system.cpu0.int_regfile_writes 34107060 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3422 # number of floating regfile reads +system.cpu0.fp_regfile_writes 966 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13053108 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451057 # number of misc regfile writes +system.cpu0.icache.replacements 392744 # number of replacements +system.cpu0.icache.tagsinuse 511.016860 # Cycle average of tags in use +system.cpu0.icache.total_refs 3798516 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393256 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.659143 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.016860 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998080 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998080 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3798516 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3798516 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3798516 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3798516 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3798516 # number of overall hits +system.cpu0.icache.overall_hits::total 3798516 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423935 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423935 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423935 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423935 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423935 # number of overall misses +system.cpu0.icache.overall_misses::total 423935 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803194996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5803194996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5803194996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5803194996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5803194996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5803194996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222451 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4222451 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4222451 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4222451 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4222451 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4222451 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100400 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100400 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100400 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100400 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100400 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100400 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13688.879182 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13688.879182 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13688.879182 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13688.879182 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3086 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.326797 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.932515 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30826 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30826 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30826 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30826 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30826 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30826 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393081 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393081 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393081 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393081 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393081 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393081 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4722265492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4722265492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4722265492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4722265492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4722265492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4722265492 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093047 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093047 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093047 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12013.466670 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30660 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30660 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30660 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30660 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30660 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30660 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393275 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393275 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393275 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393275 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393275 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393275 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745687496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745687496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745687496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4745687496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745687496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4745687496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093139 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093139 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093139 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.096805 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276186 # number of replacements -system.cpu0.dcache.tagsinuse 460.207954 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9271152 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276698 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.506393 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.207954 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.898844 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.898844 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5791916 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5791916 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159128 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159128 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139197 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139197 # 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number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7503 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1976708 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1976708 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1976708 # number of overall misses -system.cpu0.dcache.overall_misses::total 1976708 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5419802000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5419802000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59847292371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 59847292371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88405500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88405500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46738000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46738000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 65267094371 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 65267094371 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 65267094371 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 65267094371 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6183413 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6183413 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744339 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4744339 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # 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miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051885 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051885 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180889 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180889 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180889 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180889 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13843.789352 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13843.789352 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37753.518220 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 37753.518220 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10040.374787 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10040.374787 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6229.241637 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6229.241637 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33018.075695 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33018.075695 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8715 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3535 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 594 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.671717 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 42.590361 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275861 # number of replacements +system.cpu0.dcache.tagsinuse 459.614904 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9266976 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276373 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.530685 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43517000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 459.614904 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.897685 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.897685 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5785932 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5785932 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3160921 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3160921 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139137 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139137 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137051 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137051 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8946853 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8946853 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8946853 # number of overall hits +system.cpu0.dcache.overall_hits::total 8946853 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 390976 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 390976 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582272 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582272 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1973248 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1973248 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1973248 # number of overall misses +system.cpu0.dcache.overall_misses::total 1973248 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5434487500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5434487500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60315071371 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60315071371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88202500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88202500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46670000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46670000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65749558871 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65749558871 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65749558871 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65749558871 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176908 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6176908 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743193 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743193 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147912 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147912 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144535 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144535 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10920101 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10920101 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10920101 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10920101 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063296 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063296 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333588 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333588 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059326 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059326 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051780 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051780 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180699 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180699 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180699 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180699 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13899.798197 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13899.798197 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38119.281243 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38119.281243 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10051.566952 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10051.566952 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6235.970069 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6235.970069 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33320.474097 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33320.474097 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8364 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5666 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 593 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.104553 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 69.950617 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256562 # number of writebacks -system.cpu0.dcache.writebacks::total 256562 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202833 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202833 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454685 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454685 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 458 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 458 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657518 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657518 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657518 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657518 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188664 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188664 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130526 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130526 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8347 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8347 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7503 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7503 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319190 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319190 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319190 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319190 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355812500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2355812500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3979098490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3979098490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66495500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66495500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31732000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31732000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6334910990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6334910990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6334910990 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6334910990 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504511500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504511500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128583377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128583377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14633094877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14633094877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027512 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027512 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051885 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051885 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12486.815185 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12486.815185 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30485.102508 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30485.102508 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7966.395112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7966.395112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4229.241637 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4229.241637 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256398 # number of writebacks +system.cpu0.dcache.writebacks::total 256398 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202708 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202708 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451928 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451928 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 451 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 451 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1654636 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1654636 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1654636 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1654636 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188268 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188268 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130344 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130344 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8324 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318612 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318612 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318612 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318612 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2372133500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2372133500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4018964492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4018964492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66568500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66568500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31704000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31704000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6391097992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6391097992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6391097992 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6391097992 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514906500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514906500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180228378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180228378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695134878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695134878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030479 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030479 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027480 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027480 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056277 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056277 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051773 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051773 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029177 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029177 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12599.770009 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12599.770009 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30833.521236 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30833.521236 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7997.176838 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7997.176838 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4236.803421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4236.803421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1234,38 +1234,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8781590 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7165099 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 410272 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5784510 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4949628 # Number of BTB hits +system.cpu1.branchPred.lookups 9060826 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7443379 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 410189 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6060421 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5228505 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.566937 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773605 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42847 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.272967 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772521 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43024 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42721233 # DTB read hits -system.cpu1.dtb.read_misses 41267 # DTB read misses -system.cpu1.dtb.write_hits 6827437 # DTB write hits -system.cpu1.dtb.write_misses 11457 # DTB write misses +system.cpu1.dtb.read_hits 42893856 # DTB read hits +system.cpu1.dtb.read_misses 41286 # DTB read misses +system.cpu1.dtb.write_hits 6825448 # DTB write hits +system.cpu1.dtb.write_misses 11345 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2630 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2300 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2725 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 348 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42762500 # DTB read accesses -system.cpu1.dtb.write_accesses 6838894 # DTB write accesses +system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42935142 # DTB read accesses +system.cpu1.dtb.write_accesses 6836793 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49548670 # DTB hits -system.cpu1.dtb.misses 52724 # DTB misses -system.cpu1.dtb.accesses 49601394 # DTB accesses -system.cpu1.itb.inst_hits 7583980 # ITB inst hits -system.cpu1.itb.inst_misses 5601 # ITB inst misses +system.cpu1.dtb.hits 49719304 # DTB hits +system.cpu1.dtb.misses 52631 # DTB misses +system.cpu1.dtb.accesses 49771935 # DTB accesses +system.cpu1.itb.inst_hits 8340296 # ITB inst hits +system.cpu1.itb.inst_misses 5581 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1274,114 +1274,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1561 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1543 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1591 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1561 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7589581 # ITB inst accesses -system.cpu1.itb.hits 7583980 # DTB hits -system.cpu1.itb.misses 5601 # DTB misses -system.cpu1.itb.accesses 7589581 # DTB accesses -system.cpu1.numCycles 406854445 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8345877 # ITB inst accesses +system.cpu1.itb.hits 8340296 # DTB hits +system.cpu1.itb.misses 5581 # DTB misses +system.cpu1.itb.accesses 8345877 # DTB accesses +system.cpu1.numCycles 408908787 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5723233 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13164545 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3370379 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 67214 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77426772 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4687 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 46358 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129737 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 707 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7581976 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 531329 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3060 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 112134243 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.659620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.988948 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19741855 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 65652351 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9060826 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6001026 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14075401 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3918937 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 65639 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77552970 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4686 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 46851 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129796 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8338330 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 726090 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3044 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114288783 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.696009 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.038635 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 98977030 88.27% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796888 0.71% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939707 0.84% 89.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1694875 1.51% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1403619 1.25% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 573280 0.51% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1928107 1.72% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410374 0.37% 95.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5410363 4.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100220679 87.69% 87.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 798295 0.70% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 938778 0.82% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1873808 1.64% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1510998 1.32% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 574008 0.50% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2116066 1.85% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410869 0.36% 94.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5845282 5.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 112134243 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021584 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.148737 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20329334 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77067438 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11999240 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 528326 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2209905 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105816 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98089 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69983071 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327113 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2209905 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21512186 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32033439 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40715711 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11249430 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4413572 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 66189803 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19593 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 681290 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3157378 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 32035 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69538015 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 303909752 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 303850528 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59224 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49060717 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20477298 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445152 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388313 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7961235 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12608499 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7947542 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1037744 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1535939 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60784720 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1155099 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87803920 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 97322 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13491429 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36062520 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 274254 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 112134243 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783025 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519999 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114288783 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022159 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.160555 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21260604 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77197159 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12728983 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 527252 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2574785 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1107873 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98231 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 74815491 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327601 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2574785 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22637961 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32138028 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40746993 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11784015 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4407001 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69468156 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19628 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 681075 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3151682 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32928 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73408550 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 319754725 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 319695969 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58756 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49044244 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24364306 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444465 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387610 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7946566 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13166209 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8131289 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1039797 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1544280 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63306558 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157694 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89041269 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 96485 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16034557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45010776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277192 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114288783 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.779090 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.516652 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 82080142 73.20% 73.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8453890 7.54% 80.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4228870 3.77% 84.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3673146 3.28% 87.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10396618 9.27% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1923791 1.72% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1051838 0.94% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 251187 0.22% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 74761 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83847546 73.36% 73.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8475969 7.42% 80.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4322490 3.78% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3758453 3.29% 87.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10560015 9.24% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1959947 1.71% 98.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1018953 0.89% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 271832 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73578 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 112134243 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114288783 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29715 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29343 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1409,395 +1409,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7547628 96.04% 96.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 280810 3.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7546096 95.87% 96.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 294849 3.75% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36673483 41.77% 42.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59172 0.07% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1514 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43579800 49.63% 91.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7175925 8.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37546524 42.17% 42.52% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59182 0.07% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43946850 49.36% 91.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7173254 8.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87803920 # Type of FU issued -system.cpu1.iq.rate 0.215812 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7859149 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089508 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 295735701 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75439999 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53226631 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15376 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8066 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6868 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95340871 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8201 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 343143 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89041269 # Type of FU issued +system.cpu1.iq.rate 0.217753 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7871282 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088400 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300376626 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80507257 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53605393 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14907 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6781 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96590759 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7860 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 340884 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2852269 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3976 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17384 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1106708 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3415033 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17027 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1294633 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919671 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 693087 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31913246 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 874031 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2209905 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24121244 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 365124 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 62044608 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 111941 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12608499 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7947542 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 865588 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 68372 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3578 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17384 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203207 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155936 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 359143 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86098386 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43091016 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1705534 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2574785 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24237525 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363690 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64568060 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112440 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13166209 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8131289 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869125 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 67667 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3747 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17027 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 202949 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155576 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 358525 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86656974 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43263445 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2384295 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104789 # number of nop insts executed -system.cpu1.iew.exec_refs 50204478 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6908033 # Number of branches executed -system.cpu1.iew.exec_stores 7113462 # Number of stores executed -system.cpu1.iew.exec_rate 0.211620 # Inst execution rate -system.cpu1.iew.wb_sent 85323128 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53233499 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29734399 # num instructions producing a value -system.cpu1.iew.wb_consumers 53052149 # num instructions consuming a value +system.cpu1.iew.exec_nop 103808 # number of nop insts executed +system.cpu1.iew.exec_refs 50374669 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6998395 # Number of branches executed +system.cpu1.iew.exec_stores 7111224 # Number of stores executed +system.cpu1.iew.exec_rate 0.211923 # Inst execution rate +system.cpu1.iew.wb_sent 85695257 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53612174 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29896757 # num instructions producing a value +system.cpu1.iew.wb_consumers 53335024 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130842 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560475 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131110 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560546 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13410332 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880845 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 313641 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 109924338 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.438116 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.408415 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 15938596 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880502 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 313478 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111713998 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.430926 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399973 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 93165965 84.75% 84.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8233685 7.49% 92.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2134554 1.94% 94.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1255111 1.14% 95.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1238932 1.13% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 576271 0.52% 96.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 972518 0.88% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 559108 0.51% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1788194 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94998150 85.04% 85.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8214546 7.35% 92.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2111823 1.89% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1251354 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1240107 1.11% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 568335 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 995989 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 499347 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1834347 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 109924338 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38068175 # Number of instructions committed -system.cpu1.commit.committedOps 48159625 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111713998 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38056856 # Number of instructions committed +system.cpu1.commit.committedOps 48140496 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16597064 # Number of memory references committed -system.cpu1.commit.loads 9756230 # Number of loads committed -system.cpu1.commit.membars 190160 # Number of memory barriers committed -system.cpu1.commit.branches 5968166 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42694155 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534687 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1788194 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16587832 # Number of memory references committed +system.cpu1.commit.loads 9751176 # Number of loads committed +system.cpu1.commit.membars 190071 # Number of memory barriers committed +system.cpu1.commit.branches 5966416 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42676497 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534458 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1834347 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 168661953 # The number of ROB reads -system.cpu1.rob.rob_writes 125442140 # The number of ROB writes -system.cpu1.timesIdled 1407356 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294720202 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1778443945 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37998536 # Number of Instructions Simulated -system.cpu1.committedOps 48089986 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37998536 # Number of Instructions Simulated -system.cpu1.cpi 10.707108 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.707108 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093396 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093396 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 385381686 # number of integer regfile reads -system.cpu1.int_regfile_writes 55406618 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18496665 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405533 # number of misc regfile writes -system.cpu1.icache.replacements 597187 # number of replacements -system.cpu1.icache.tagsinuse 480.515152 # Cycle average of tags in use -system.cpu1.icache.total_refs 6939274 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597699 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.609981 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74121232000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.515152 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938506 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938506 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6939274 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6939274 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6939274 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6939274 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6939274 # number of overall hits -system.cpu1.icache.overall_hits::total 6939274 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 642651 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 642651 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 642651 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 642651 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 642651 # number of overall misses -system.cpu1.icache.overall_misses::total 642651 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8610286993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8610286993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8610286993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8610286993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8610286993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8610286993 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7581925 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7581925 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7581925 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7581925 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7581925 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7581925 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084761 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084761 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084761 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084761 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084761 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084761 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13398.076083 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13398.076083 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13398.076083 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13398.076083 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2076 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 753 # number of cycles access was blocked +system.cpu1.rob.rob_reads 172914942 # The number of ROB reads +system.cpu1.rob.rob_writes 130824932 # The number of ROB writes +system.cpu1.timesIdled 1407670 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294620004 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796556351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37987217 # Number of Instructions Simulated +system.cpu1.committedOps 48070857 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37987217 # Number of Instructions Simulated +system.cpu1.cpi 10.764379 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.764379 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092899 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092899 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387772369 # number of integer regfile reads +system.cpu1.int_regfile_writes 56145305 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4887 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18518507 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405334 # number of misc regfile writes +system.cpu1.icache.replacements 597077 # number of replacements +system.cpu1.icache.tagsinuse 480.917703 # Cycle average of tags in use +system.cpu1.icache.total_refs 7696282 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597589 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.878888 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74223543500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.917703 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.939292 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.939292 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7696282 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7696282 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7696282 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7696282 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7696282 # number of overall hits +system.cpu1.icache.overall_hits::total 7696282 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641998 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641998 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641998 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641998 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641998 # number of overall misses +system.cpu1.icache.overall_misses::total 641998 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8633779496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8633779496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8633779496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8633779496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8633779496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8633779496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8338280 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8338280 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8338280 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8338280 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8338280 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8338280 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076994 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076994 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076994 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076994 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076994 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076994 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13448.296562 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13448.296562 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13448.296562 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13448.296562 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.069767 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 753 # average number of cycles each access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.203488 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44927 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44927 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44927 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44927 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44927 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44927 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597724 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597724 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597724 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597724 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597724 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597724 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7047898994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7047898994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7047898994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7047898994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7047898994 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7047898994 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078835 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078835 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078835 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11791.226375 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44386 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44386 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44386 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44386 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44386 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44386 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597612 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597612 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597612 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597612 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597612 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597612 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7074093496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7074093496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7074093496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7074093496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7074093496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7074093496 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3068500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3068500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3068500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3068500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071671 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071671 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071671 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11837.268154 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360661 # number of replacements -system.cpu1.dcache.tagsinuse 473.725553 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12688668 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 361027 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.146036 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70279173000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.725553 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.925245 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.925245 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8315910 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8315910 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4141838 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4141838 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97575 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97575 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94901 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94901 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12457748 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12457748 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12457748 # number of overall hits -system.cpu1.dcache.overall_hits::total 12457748 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 397655 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 397655 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1555408 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1555408 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10609 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10609 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1953063 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1953063 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1953063 # number of overall misses -system.cpu1.dcache.overall_misses::total 1953063 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5962620500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5962620500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 63820949998 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 63820949998 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128371500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 128371500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53750500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53750500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 69783570498 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 69783570498 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 69783570498 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 69783570498 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8713565 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8713565 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5697246 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5697246 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111512 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111512 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105510 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105510 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14410811 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14410811 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14410811 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14410811 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045636 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045636 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273011 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273011 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124982 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124982 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100550 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100550 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135528 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135528 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135528 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135528 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14994.456250 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14994.456250 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41031.645715 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41031.645715 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9210.841645 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9210.841645 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5066.500141 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5066.500141 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35730.322318 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 35730.322318 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 26431 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 15171 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 158 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.193118 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 96.018987 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360159 # number of replacements +system.cpu1.dcache.tagsinuse 474.597840 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12677942 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360527 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.165028 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70354983000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.597840 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.926949 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.926949 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8310534 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8310534 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138624 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138624 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97469 # 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number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53828000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53828000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67878169511 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67878169511 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67878169511 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67878169511 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708076 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8708076 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693368 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5693368 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111376 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111376 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105456 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105456 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14401444 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14401444 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14401444 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14401444 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045652 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045652 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273080 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273080 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124865 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124865 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100497 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100497 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135562 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135562 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135562 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135562 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.900257 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.900257 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39770.653890 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39770.653890 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9295.966060 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9295.966060 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.071523 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.071523 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34768.558250 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34768.558250 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 26588 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13412 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3258 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.160835 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 82.790123 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324726 # number of writebacks -system.cpu1.dcache.writebacks::total 324726 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169327 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169327 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393847 # 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number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12488 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389889 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389889 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389889 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389889 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2825835000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2825835000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5223945209 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5223945209 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27123329043 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27123329043 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196119308043 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196119308043 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026204 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026204 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111988 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111988 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100531 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100531 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027055 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027055 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.208787 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12376.208787 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32334.197046 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32334.197046 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7002.041960 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7002.041960 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3067.455454 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3067.455454 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324224 # number of writebacks +system.cpu1.dcache.writebacks::total 324224 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169594 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 169594 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393339 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1393339 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562933 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1562933 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562933 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1562933 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227948 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227948 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161405 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161405 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12460 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12460 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10596 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10596 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389353 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389353 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389353 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389353 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2844990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2844990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5144127207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5144127207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88536000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88536000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32636000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32636000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989117207 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7989117207 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989117207 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7989117207 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989822500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989822500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35094178017 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35094178017 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204084000517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204084000517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026177 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026177 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111873 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111873 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100478 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100478 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027036 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027036 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.872831 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12480.872831 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31870.928453 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31870.928453 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7105.617978 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7105.617978 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3080.030200 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3080.030200 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1819,18 +1819,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 497798121418 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 497798121418 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 497798121418 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 497798121418 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 539953604456 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 539953604456 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 539953604456 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 539953604456 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41715 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41721 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48838 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 80b8abc3e..406114ee2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,126 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523205 # Number of seconds simulated -sim_ticks 2523204701000 # Number of ticks simulated -final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533245 # Number of seconds simulated +sim_ticks 2533245380500 # Number of ticks simulated +final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50114 # Simulator instruction rate (inst/s) -host_op_rate 64483 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2096764175 # Simulator tick rate (ticks/s) -host_mem_usage 452888 # Number of bytes of host memory used -host_seconds 1203.38 # Real time elapsed on the host -sim_insts 60306320 # Number of instructions simulated -sim_ops 77597310 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 67317 # Simulator instruction rate (inst/s) +host_op_rate 86618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2827634962 # Simulator tick rate (ticks/s) +host_mem_usage 409784 # Number of bytes of host memory used +host_seconds 895.89 # Real time elapsed on the host +sim_insts 60308251 # Number of instructions simulated +sim_ops 77599937 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096856 # Total number of read requests seen -system.physmem.writeReqs 813138 # Total number of write requests seen -system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966198784 # Total number of bytes read from memory -system.physmem.bytesWritten 52040832 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis +system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096850 # Total number of read requests seen +system.physmem.writeReqs 813145 # Total number of write requests seen +system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966198400 # Total number of bytes read from memory +system.physmem.bytesWritten 52041280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523203522000 # Total gap between requests +system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533244279000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154612 # Categorize read packet sizes +system.physmem.readPktSize::6 154606 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1943854 # categorize write packet sizes +system.physmem.writePktSize::2 2927056 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59120 # categorize write packet sizes +system.physmem.writePktSize::6 59127 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -129,30 +117,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -184,79 +172,91 @@ system.physmem.wrQLenPdf::15 35354 # Wh system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests -system.physmem.totBusLat 60386192000 # Total cycles spent in databus access -system.physmem.totBankLat 16356620000 # Total cycles spent in bank access -system.physmem.avgQLat 21743.10 # Average queueing delay per request -system.physmem.avgBankLat 1083.47 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26826.57 # Average memory access latency -system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 10.68 # Average write queue length over time -system.physmem.readRowHits 15052450 # Number of row buffer hits during reads -system.physmem.writeRowHits 784654 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes -system.physmem.avgGap 158592.36 # Average gap between requests +system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests +system.physmem.totBusLat 75482595000 # Total cycles spent in databus access +system.physmem.totBankLat 16916941250 # Total cycles spent in bank access +system.physmem.avgQLat 26034.38 # Average queueing delay per request +system.physmem.avgBankLat 1120.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32154.97 # Average memory access latency +system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.avgWrQLen 12.52 # Average write queue length over time +system.physmem.readRowHits 15020214 # Number of row buffer hits during reads +system.physmem.writeRowHits 793069 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes +system.physmem.avgGap 159223.45 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14400111 # Number of BP lookups -system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits +system.cpu.branchPred.lookups 14667589 # Number of BP lookups +system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51212683 # DTB read hits -system.cpu.dtb.read_misses 73387 # DTB read misses -system.cpu.dtb.write_hits 11701466 # DTB write hits -system.cpu.dtb.write_misses 17011 # DTB write misses +system.cpu.dtb.read_hits 51389080 # DTB read hits +system.cpu.dtb.read_misses 73326 # DTB read misses +system.cpu.dtb.write_hits 11702658 # DTB write hits +system.cpu.dtb.write_misses 17128 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51286070 # DTB read accesses -system.cpu.dtb.write_accesses 11718477 # DTB write accesses +system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51462406 # DTB read accesses +system.cpu.dtb.write_accesses 11719786 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62914149 # DTB hits -system.cpu.dtb.misses 90398 # DTB misses -system.cpu.dtb.accesses 63004547 # DTB accesses -system.cpu.itb.inst_hits 11530598 # ITB inst hits -system.cpu.itb.inst_misses 11503 # ITB inst misses +system.cpu.dtb.hits 63091738 # DTB hits +system.cpu.dtb.misses 90454 # DTB misses +system.cpu.dtb.accesses 63182192 # DTB accesses +system.cpu.itb.inst_hits 12277036 # ITB inst hits +system.cpu.itb.inst_misses 11490 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -265,114 +265,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2585 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2578 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11542101 # ITB inst accesses -system.cpu.itb.hits 11530598 # DTB hits -system.cpu.itb.misses 11503 # DTB misses -system.cpu.itb.accesses 11542101 # DTB accesses -system.cpu.numCycles 469830472 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12288526 # ITB inst accesses +system.cpu.itb.hits 12277036 # DTB hits +system.cpu.itb.misses 11490 # DTB misses +system.cpu.itb.accesses 12288526 # DTB accesses +system.cpu.numCycles 472097236 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -400,383 +400,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued -system.cpu.iq.rate 0.261848 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued +system.cpu.iq.rate 0.263176 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221038 # number of nop insts executed -system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed -system.cpu.iew.exec_branches 11477980 # Number of branches executed -system.cpu.iew.exec_stores 12213052 # Number of stores executed -system.cpu.iew.exec_rate 0.257448 # Inst execution rate -system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47051195 # num instructions producing a value -system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value +system.cpu.iew.exec_nop 220577 # number of nop insts executed +system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed +system.cpu.iew.exec_branches 11563754 # Number of branches executed +system.cpu.iew.exec_stores 12214366 # Number of stores executed +system.cpu.iew.exec_rate 0.257379 # Inst execution rate +system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47207424 # num instructions producing a value +system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456701 # Number of instructions committed -system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458632 # Number of instructions committed +system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385892 # Number of memory references committed -system.cpu.commit.loads 15654083 # Number of loads committed -system.cpu.commit.membars 403583 # Number of memory barriers committed -system.cpu.commit.branches 9961154 # Number of branches committed +system.cpu.commit.refs 27386920 # Number of memory references committed +system.cpu.commit.loads 15654712 # Number of loads committed +system.cpu.commit.membars 403607 # Number of memory barriers committed +system.cpu.commit.branches 9961406 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68853054 # Number of committed integer instructions. -system.cpu.commit.function_calls 991222 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855494 # Number of committed integer instructions. +system.cpu.commit.function_calls 991273 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 238273902 # The number of ROB reads -system.cpu.rob.rob_writes 196332947 # The number of ROB writes -system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60306320 # Number of Instructions Simulated -system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated -system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547824485 # number of integer regfile reads -system.cpu.int_regfile_writes 87698031 # number of integer regfile writes -system.cpu.fp_regfile_reads 8340 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads -system.cpu.misc_regfile_writes 831851 # number of misc regfile writes -system.cpu.icache.replacements 979772 # number of replacements -system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use -system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits -system.cpu.icache.overall_hits::total 10466836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses -system.cpu.icache.overall_misses::total 1059904 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.rob.rob_reads 242460133 # The number of ROB reads +system.cpu.rob.rob_writes 201635862 # The number of ROB writes +system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60308251 # Number of Instructions Simulated +system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated +system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550197994 # number of integer regfile reads +system.cpu.int_regfile_writes 88410647 # number of integer regfile writes +system.cpu.fp_regfile_reads 8198 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads +system.cpu.misc_regfile_writes 831902 # number of misc regfile writes +system.cpu.icache.replacements 980802 # number of replacements +system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use +system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits +system.cpu.icache.overall_hits::total 11213050 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses +system.cpu.icache.overall_misses::total 1060138 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11335281493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11335281493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11335281493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085048 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78782 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 78782 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 78782 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 78782 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 78782 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 78782 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981356 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981356 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981356 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11396806498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11396806498 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11396806498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11396806498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11396806498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11396806498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079959 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64384 # number of replacements -system.cpu.l2cache.tagsinuse 51365.557849 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1909698 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129778 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.715114 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.occ_percent::cpu.inst 0.124884 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783715 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79915 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11190 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967706 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 386775 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1445586 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607265 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607265 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 17 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44427.646068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46212.888514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45276.594378 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.370459 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.370459 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.165453 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.165453 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38151.749685 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38151.749685 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -897,161 +897,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643386 # number of replacements -system.cpu.dcache.tagsinuse 511.994223 # Cycle average of tags in use -system.cpu.dcache.total_refs 21524162 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643898 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.427906 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994223 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13769851 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13769851 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7260574 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7260574 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243031 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243031 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247612 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247612 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24722988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24722988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24722988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24722988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050413 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050413 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289718 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052821 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052821 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.replacements 643060 # number of replacements +system.cpu.dcache.tagsinuse 511.992813 # Cycle average of tags in use +system.cpu.dcache.total_refs 21518829 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643572 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.436553 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 42289000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992813 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13762862 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13762862 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7262343 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7262343 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242888 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242888 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21025205 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21025205 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21025205 # number of overall hits +system.cpu.dcache.overall_hits::total 21025205 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960125 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13538 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13538 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3691646 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3691646 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3691646 # number of overall misses +system.cpu.dcache.overall_misses::total 3691646 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9676520000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9676520000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104419203240 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104419203240 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 271000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 271000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114095723240 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114095723240 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114095723240 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114095723240 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14494383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14494383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256426 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256426 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247620 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247620 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24716851 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24716851 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24716851 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24716851 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050469 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050469 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289570 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052795 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052795 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000077 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000077 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13227.945609 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13227.945609 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35275.268186 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35275.268186 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28001 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14318 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2522 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.102696 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 57.733871 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks -system.cpu.dcache.writebacks::total 607596 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607265 # number of writebacks +system.cpu.dcache.writebacks::total 607265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057299 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057299 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385397 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385397 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248950 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248950 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,16 +1073,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8a66caa53..49d5a4463 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,148 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401290 # Number of seconds simulated -sim_ticks 2401290348000 # Number of ticks simulated -final_tick 2401290348000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401347 # Number of seconds simulated +sim_ticks 2401347058000 # Number of ticks simulated +final_tick 2401347058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145439 # Simulator instruction rate (inst/s) -host_op_rate 186799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5788935854 # Simulator tick rate (ticks/s) -host_mem_usage 444568 # Number of bytes of host memory used -host_seconds 414.81 # Real time elapsed on the host -sim_insts 60329082 # Number of instructions simulated -sim_ops 77485321 # Number of ops (including micro ops) simulated +host_inst_rate 247220 # Simulator instruction rate (inst/s) +host_op_rate 317493 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9839599535 # Simulator tick rate (ticks/s) +host_mem_usage 400552 # Number of bytes of host memory used +host_seconds 244.05 # Real time elapsed on the host +sim_insts 60333921 # Number of instructions simulated +sim_ops 77484019 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 486624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7022480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 501472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7131280 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 77504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 723200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 203648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1332732 # Number of bytes read from this memory -system.physmem.bytes_read::total 124666476 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 486624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 77504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 203648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 767776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3747584 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1052224 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 85632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 677504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1269180 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 501472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 85632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1495356 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1764136 # Number of bytes written to this memory -system.physmem.bytes_written::total 6763400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1321004 # Number of bytes written to this memory +system.physmem.bytes_written::total 6762184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13806 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 109760 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111460 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20838 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512500 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58556 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 263056 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 19845 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512426 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58537 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 373839 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 441034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812510 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47815572 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 330251 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812491 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 202651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2924461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 208829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2969700 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 301171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 84808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 555007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51916452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 202651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 84808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 438191 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 734662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816569 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47815572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 528528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51913254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 208829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35660 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 622715 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 550110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814443 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 202651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3362652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 208829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3592415 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 384233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 84808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1289668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54733021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12619459 # Total number of read requests seen -system.physmem.writeReqs 508288 # Total number of write requests seen -system.physmem.cpureqs 56279 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807645376 # Total number of bytes read from memory -system.physmem.bytesWritten 32530432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 103001404 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 3076552 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 788367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 788430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 788204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 789073 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 789810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 789739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 789543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 789483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788174 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788123 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 30454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 30491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 30890 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 31526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 31443 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 31484 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 31752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 32161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 32686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 32676 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 32416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 32334 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 31816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 31518 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 32440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 32201 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 35660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1078638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54729250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12617453 # Total number of read requests seen +system.physmem.writeReqs 397526 # Total number of write requests seen +system.physmem.cpureqs 54288 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807516992 # Total number of bytes read from memory +system.physmem.bytesWritten 25441664 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102873020 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2634764 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789165 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789011 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 787997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788205 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788698 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24781 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25063 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24852 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 25063 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25236 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 24651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24325 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24934 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25132 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 316906 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400255112000 # Total gap between requests +system.physmem.numWrRetry 749984 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400311882000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 15 # Categorize read packet sizes system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 36532 # Categorize read packet sizes +system.physmem.readPktSize::6 34526 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 807804 # categorize write packet sizes +system.physmem.writePktSize::2 1130099 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 17390 # categorize write packet sizes +system.physmem.writePktSize::6 17411 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -151,26 +151,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2357 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2351 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 817349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 786840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 815906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2309875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2310166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4565473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 24603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 24600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 47884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 24589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 47866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 815640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 791627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -187,60 +187,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 22104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 22101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 22095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 22093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 22091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 22082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 22071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 22068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 22063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 22058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 22054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 22052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 13970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 13934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 13913 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 234677385926 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 297433333926 # Sum of mem lat for all requests -system.physmem.totBusLat 50477836000 # Total cycles spent in databus access -system.physmem.totBankLat 12278112000 # Total cycles spent in bank access -system.physmem.avgQLat 18596.47 # Average queueing delay per request -system.physmem.avgBankLat 972.95 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23569.42 # Average memory access latency -system.physmem.avgRdBW 336.34 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 13.55 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.89 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.28 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.19 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.12 # Average read queue length over time +system.physmem.totQLat 277194471582 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 353012127832 # Sum of mem lat for all requests +system.physmem.totBusLat 63087260000 # Total cycles spent in databus access +system.physmem.totBankLat 12730396250 # Total cycles spent in bank access +system.physmem.avgQLat 21969.13 # Average queueing delay per request +system.physmem.avgBankLat 1008.95 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27978.08 # Average memory access latency +system.physmem.avgRdBW 336.28 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.59 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.84 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.71 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12589970 # Number of row buffer hits during reads -system.physmem.writeRowHits 499207 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.77 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018136 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018242 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005957 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992079 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.505786 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.335210 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348001 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.111361 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.113643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.106460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.022534 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.113643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.106460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.022534 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45242.896780 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48508.487320 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48662.722349 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.734531 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.973755 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31515.049734 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41152.282713 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37741.003999 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39434.677126 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 32702.234186 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41675.876843 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39165.597102 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39434.677126 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32702.234186 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41675.876843 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39165.597102 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32347.861318 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40507.928995 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37645.705010 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -686,436 +683,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7853690 # DTB read hits -system.cpu0.dtb.read_misses 6243 # DTB read misses -system.cpu0.dtb.write_hits 6487171 # DTB write hits -system.cpu0.dtb.write_misses 1921 # DTB write misses +system.cpu0.dtb.read_hits 8069329 # DTB read hits +system.cpu0.dtb.read_misses 6237 # DTB read misses +system.cpu0.dtb.write_hits 6635324 # DTB write hits +system.cpu0.dtb.write_misses 2059 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5670 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5724 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7859933 # DTB read accesses -system.cpu0.dtb.write_accesses 6489092 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8075566 # DTB read accesses +system.cpu0.dtb.write_accesses 6637383 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14340861 # DTB hits -system.cpu0.dtb.misses 8164 # DTB misses -system.cpu0.dtb.accesses 14349025 # DTB accesses -system.cpu0.itb.inst_hits 31512097 # ITB inst hits -system.cpu0.itb.inst_misses 3518 # ITB inst misses +system.cpu0.dtb.hits 14704653 # DTB hits +system.cpu0.dtb.misses 8296 # DTB misses +system.cpu0.dtb.accesses 14712949 # DTB accesses +system.cpu0.itb.inst_hits 32681523 # ITB inst hits +system.cpu0.itb.inst_misses 3486 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 31515615 # ITB inst accesses -system.cpu0.itb.hits 31512097 # DTB hits -system.cpu0.itb.misses 3518 # DTB misses -system.cpu0.itb.accesses 31515615 # DTB accesses -system.cpu0.numCycles 112564012 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32685009 # ITB inst accesses +system.cpu0.itb.hits 32681523 # DTB hits +system.cpu0.itb.misses 3486 # DTB misses +system.cpu0.itb.accesses 32685009 # DTB accesses +system.cpu0.numCycles 114009309 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31022111 # Number of instructions committed -system.cpu0.committedOps 41078367 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 36251649 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5105 # Number of float alu accesses -system.cpu0.num_func_calls 1198861 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4217068 # number of instructions that are conditional controls -system.cpu0.num_int_insts 36251649 # number of integer instructions -system.cpu0.num_fp_insts 5105 # number of float instructions -system.cpu0.num_int_register_reads 184966774 # number of times the integer registers were read -system.cpu0.num_int_register_writes 38342244 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3615 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15003639 # number of memory refs -system.cpu0.num_load_insts 8220534 # Number of load instructions -system.cpu0.num_store_insts 6783105 # Number of store instructions -system.cpu0.num_idle_cycles 13359160341.338484 # Number of idle cycles -system.cpu0.num_busy_cycles -13246596329.338484 # Number of busy cycles -system.cpu0.not_idle_fraction -117.680563 # Percentage of non-idle cycles -system.cpu0.idle_fraction 118.680563 # Percentage of idle cycles +system.cpu0.committedInsts 32183346 # Number of instructions committed +system.cpu0.committedOps 42389974 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37541413 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5201 # Number of float alu accesses +system.cpu0.num_func_calls 1186772 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4235639 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37541413 # number of integer instructions +system.cpu0.num_fp_insts 5201 # number of float instructions +system.cpu0.num_int_register_reads 191262498 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39620034 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3719 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1484 # number of times the floating registers were written +system.cpu0.num_mem_refs 15366811 # number of memory refs +system.cpu0.num_load_insts 8436504 # Number of load instructions +system.cpu0.num_store_insts 6930307 # Number of store instructions +system.cpu0.num_idle_cycles 13418269361.007845 # Number of idle cycles +system.cpu0.num_busy_cycles -13304260052.007845 # Number of busy cycles +system.cpu0.not_idle_fraction -116.694507 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.694507 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892592 # number of replacements -system.cpu0.icache.tagsinuse 511.602515 # Cycle average of tags in use -system.cpu0.icache.total_refs 43093947 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 893104 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 48.251880 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8108198000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 496.911233 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 7.172611 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 7.518672 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.970530 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.014009 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.014685 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31040977 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8399762 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3653208 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43093947 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31040977 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8399762 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3653208 # 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number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 473826 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 127142 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 316554 # number of overall misses -system.cpu0.icache.overall_misses::total 917522 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1706895500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4221661989 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5928557489 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1706895500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4221661989 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5928557489 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1706895500 # 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average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18027.303598 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18027.303598 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9913 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3463 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1094 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 45 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.061243 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 76.955556 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597807 # number of writebacks -system.cpu0.dcache.writebacks::total 597807 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 131637 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 131637 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 540605 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 540605 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 422 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 422 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 672242 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 672242 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 672242 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 672242 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58240 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 124377 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182617 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29720 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52501 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82221 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1608 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3399 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5007 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 87960 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 176878 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 264838 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 87960 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 176878 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 264838 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 699397500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1604351000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2303748500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 688738500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1452391492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141129992 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 17815500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39577500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57393000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 101000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 101000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1388136000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3056742492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4444878492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1388136000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3056742492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4444878492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27612956500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29018137000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56631093500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1285303000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 12932223922 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14217526922 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28898259500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41950360922 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70848620422 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030320 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.024756 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013186 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021350 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019173 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008048 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046539 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043610 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020014 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026551 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.022786 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011005 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026551 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.022786 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011005 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12008.885646 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12899.097100 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12615.191904 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23174.242934 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27664.072913 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26041.157271 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11079.291045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11643.865843 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11462.552427 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14428.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14428.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597795 # number of writebacks +system.cpu0.dcache.writebacks::total 597795 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143860 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 143860 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 535045 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 535045 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 436 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 436 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 678905 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 678905 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 678905 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 678905 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65045 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137074 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202119 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29287 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52279 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81566 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1727 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3465 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5192 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94332 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 189353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283685 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94332 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 189353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283685 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 777582500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1781362000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2558944500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 664316500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1392170991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2056487491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19153500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40164500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59318000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1441899000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3173532991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4615431991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1441899000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3173532991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4615431991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27472084500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29005064000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56477148500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280597500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13851108534 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15131706034 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28752682000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42856172534 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71608854534 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032878 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014620 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021165 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019298 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044724 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020706 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11954.531478 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12995.622802 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12660.583617 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22682.982211 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26629.640793 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25212.557818 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.619572 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11591.486291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11424.884438 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1128,388 +1125,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2135190 # DTB read hits -system.cpu1.dtb.read_misses 2107 # DTB read misses -system.cpu1.dtb.write_hits 1477401 # DTB write hits -system.cpu1.dtb.write_misses 382 # DTB write misses +system.cpu1.dtb.read_hits 2193182 # DTB read hits +system.cpu1.dtb.read_misses 2113 # DTB read misses +system.cpu1.dtb.write_hits 1470431 # DTB write hits +system.cpu1.dtb.write_misses 386 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1694 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1737 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2137297 # DTB read accesses -system.cpu1.dtb.write_accesses 1477783 # DTB write accesses +system.cpu1.dtb.perms_faults 73 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2195295 # DTB read accesses +system.cpu1.dtb.write_accesses 1470817 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3612591 # DTB hits -system.cpu1.dtb.misses 2489 # DTB misses -system.cpu1.dtb.accesses 3615080 # DTB accesses -system.cpu1.itb.inst_hits 8526904 # ITB inst hits -system.cpu1.itb.inst_misses 1128 # ITB inst misses +system.cpu1.dtb.hits 3663613 # DTB hits +system.cpu1.dtb.misses 2499 # DTB misses +system.cpu1.dtb.accesses 3666112 # DTB accesses +system.cpu1.itb.inst_hits 8542569 # ITB inst hits +system.cpu1.itb.inst_misses 1142 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 843 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8528032 # ITB inst accesses -system.cpu1.itb.hits 8526904 # DTB hits -system.cpu1.itb.misses 1128 # DTB misses -system.cpu1.itb.accesses 8528032 # DTB accesses -system.cpu1.numCycles 573624739 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8543711 # ITB inst accesses +system.cpu1.itb.hits 8542569 # DTB hits +system.cpu1.itb.misses 1142 # DTB misses +system.cpu1.itb.accesses 8543711 # DTB accesses +system.cpu1.numCycles 574622770 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8322298 # Number of instructions committed -system.cpu1.committedOps 10507258 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9429869 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses -system.cpu1.num_func_calls 301953 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1117858 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9429869 # number of integer instructions -system.cpu1.num_fp_insts 2062 # number of float instructions -system.cpu1.num_int_register_reads 54131389 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10251114 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3780360 # number of memory refs -system.cpu1.num_load_insts 2226594 # Number of load instructions -system.cpu1.num_store_insts 1553766 # Number of store instructions -system.cpu1.num_idle_cycles -28509606.904042 # Number of idle cycles -system.cpu1.num_busy_cycles 602134345.904042 # Number of busy cycles -system.cpu1.not_idle_fraction 1.049701 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.049701 # Percentage of idle cycles +system.cpu1.committedInsts 8323313 # Number of instructions committed +system.cpu1.committedOps 10568521 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9455667 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses +system.cpu1.num_func_calls 319891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1162179 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9455667 # number of integer instructions +system.cpu1.num_fp_insts 2078 # number of float instructions +system.cpu1.num_int_register_reads 54536858 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10267786 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3838385 # number of memory refs +system.cpu1.num_load_insts 2289184 # Number of load instructions +system.cpu1.num_store_insts 1549201 # Number of store instructions +system.cpu1.num_idle_cycles 539990839.742371 # Number of idle cycles +system.cpu1.num_busy_cycles 34631930.257629 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060269 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939731 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4714679 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3830081 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 228509 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3129435 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2502665 # Number of BTB hits +system.cpu2.branchPred.lookups 4693263 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3812182 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 221977 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3118720 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2512857 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.971784 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 416919 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 22256 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.573344 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412180 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21663 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 11094758 # DTB read hits -system.cpu2.dtb.read_misses 26972 # DTB read misses -system.cpu2.dtb.write_hits 3400244 # DTB write hits -system.cpu2.dtb.write_misses 7099 # DTB write misses +system.cpu2.dtb.read_hits 10844301 # DTB read hits +system.cpu2.dtb.read_misses 26001 # DTB read misses +system.cpu2.dtb.write_hits 3253591 # DTB write hits +system.cpu2.dtb.write_misses 6154 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 3080 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 792 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 201 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 3046 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 667 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 424 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 11121730 # DTB read accesses -system.cpu2.dtb.write_accesses 3407343 # DTB write accesses +system.cpu2.dtb.perms_faults 434 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10870302 # DTB read accesses +system.cpu2.dtb.write_accesses 3259745 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14495002 # DTB hits -system.cpu2.dtb.misses 34071 # DTB misses -system.cpu2.dtb.accesses 14529073 # DTB accesses -system.cpu2.itb.inst_hits 3971406 # ITB inst hits -system.cpu2.itb.inst_misses 4850 # ITB inst misses +system.cpu2.dtb.hits 14097892 # DTB hits +system.cpu2.dtb.misses 32155 # DTB misses +system.cpu2.dtb.accesses 14130047 # DTB accesses +system.cpu2.itb.inst_hits 4034633 # ITB inst hits +system.cpu2.itb.inst_misses 4571 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1620 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1033 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 986 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 3976256 # ITB inst accesses -system.cpu2.itb.hits 3971406 # DTB hits -system.cpu2.itb.misses 4850 # DTB misses -system.cpu2.itb.accesses 3976256 # DTB accesses -system.cpu2.numCycles 88220053 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4039204 # ITB inst accesses +system.cpu2.itb.hits 4034633 # DTB hits +system.cpu2.itb.misses 4571 # DTB misses +system.cpu2.itb.accesses 4039204 # DTB accesses +system.cpu2.numCycles 88320298 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9444272 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32171210 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4714679 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2919584 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6810047 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1714054 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 54378 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19370743 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 384 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 766 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 36586 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 56559 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 314 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3969766 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 243007 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2358 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36954315 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.048838 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.435241 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9410725 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32093241 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4693263 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2925037 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6776745 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1793565 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51693 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19502883 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 35787 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57273 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4033217 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 303741 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2092 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37067906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.039760 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.425875 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30149445 81.59% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 388045 1.05% 82.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515673 1.40% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 809442 2.19% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 613859 1.66% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342479 0.93% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1057115 2.86% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 225211 0.61% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2853046 7.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30296325 81.73% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382563 1.03% 82.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 507321 1.37% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 805393 2.17% 86.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 652342 1.76% 88.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 346651 0.94% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 996850 2.69% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 239087 0.64% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2841374 7.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36954315 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053442 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.364670 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9982984 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19336478 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6240183 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 267118 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1126648 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608561 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 54769 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36760882 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 185685 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1126648 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10483708 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6549966 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11350548 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5986699 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1455863 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35043442 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2820 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 275900 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 915207 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 16681 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37480121 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 160397903 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 160370485 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27418 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 27101892 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10378228 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 234776 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 210973 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3167835 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6643625 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3930476 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 536055 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 848060 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32398169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511180 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35261741 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 57711 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6815727 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 17611211 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 150093 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36954315 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.954198 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.610437 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37067906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053139 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.363373 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10025306 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19435128 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6133360 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293839 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1179201 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 610191 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53369 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36416807 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180085 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1179201 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10595473 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6672537 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11193536 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5837719 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1588398 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34213134 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2954 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 427229 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 898663 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 11044 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36672264 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 156364458 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 156337893 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 26565 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25643428 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11028835 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232388 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208734 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3368643 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6480999 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3820565 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 539245 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 769553 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31495381 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 514788 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34101978 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55239 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7293710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19517466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 157489 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37067906 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.919987 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.574944 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24234818 65.58% 65.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3845219 10.41% 75.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2339985 6.33% 82.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2011458 5.44% 87.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2820235 7.63% 95.39% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1010729 2.74% 98.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 509292 1.38% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 148791 0.40% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 33788 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24513061 66.13% 66.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3940276 10.63% 76.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2351629 6.34% 83.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1969211 5.31% 88.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2763009 7.45% 95.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 888704 2.40% 98.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 473497 1.28% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 133879 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34640 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36954315 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37067906 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16803 1.09% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1412351 91.83% 92.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 108917 7.08% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16450 1.07% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1406460 91.72% 92.80% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110474 7.20% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 60938 0.17% 0.17% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 20064817 56.90% 57.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28831 0.08% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 373 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11537749 32.72% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3569015 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61347 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19254237 56.46% 56.64% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25603 0.08% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 363 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11339596 33.25% 89.97% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3420808 10.03% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35261741 # Type of FU issued -system.cpu2.iq.rate 0.399702 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1538071 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043619 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 109100819 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39730950 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28646602 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6706 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3736 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3123 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36735375 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3499 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 200241 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34101978 # Type of FU issued +system.cpu2.iq.rate 0.386117 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1533384 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044965 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106886012 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39309169 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27255453 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6518 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3637 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3015 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35570601 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3414 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207005 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1445664 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1895 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9919 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 541092 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1561439 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1810 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9237 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 573725 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5363616 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 332725 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5369512 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 345439 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1126648 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4836519 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 87210 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32990358 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 63317 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6643625 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3930476 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 365793 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29718 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2499 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9919 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 109460 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 91793 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 201253 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 34488012 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11310897 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 773729 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1179201 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4914537 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 93208 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32084127 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61095 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6480999 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3820565 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 371831 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 32634 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9237 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 106581 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88238 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 194819 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33130261 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11055368 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 971717 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 81009 # number of nop insts executed -system.cpu2.iew.exec_refs 14846360 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3721674 # Number of branches executed -system.cpu2.iew.exec_stores 3535463 # Number of stores executed -system.cpu2.iew.exec_rate 0.390932 # Inst execution rate -system.cpu2.iew.wb_sent 34107524 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28649725 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16504855 # num instructions producing a value -system.cpu2.iew.wb_consumers 29777909 # num instructions consuming a value +system.cpu2.iew.exec_nop 73958 # number of nop insts executed +system.cpu2.iew.exec_refs 14443007 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3675866 # Number of branches executed +system.cpu2.iew.exec_stores 3387639 # Number of stores executed +system.cpu2.iew.exec_rate 0.375115 # Inst execution rate +system.cpu2.iew.wb_sent 32719575 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27258468 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15578435 # num instructions producing a value +system.cpu2.iew.wb_consumers 28336805 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.324753 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.554265 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.308632 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549760 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6780603 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 361087 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 174485 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35827443 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.724416 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.779563 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7236388 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357299 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 169355 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35888560 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.684756 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.712853 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 26972703 75.29% 75.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4272213 11.92% 87.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1247843 3.48% 90.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 631329 1.76% 92.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 544091 1.52% 93.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 320362 0.89% 94.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 435465 1.22% 96.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 326356 0.91% 96.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1077081 3.01% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27290790 76.04% 76.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4165435 11.61% 87.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1253109 3.49% 91.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 644489 1.80% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 571851 1.59% 94.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 314297 0.88% 95.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 396110 1.10% 96.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 285595 0.80% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 966884 2.69% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35827443 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 21038967 # Number of instructions committed -system.cpu2.commit.committedOps 25953990 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35888560 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19876644 # Number of instructions committed +system.cpu2.commit.committedOps 24574906 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8587345 # Number of memory references committed -system.cpu2.commit.loads 5197961 # Number of loads committed -system.cpu2.commit.membars 96306 # Number of memory barriers committed -system.cpu2.commit.branches 3207336 # Number of branches committed -system.cpu2.commit.fp_insts 3087 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 23136134 # Number of committed integer instructions. -system.cpu2.commit.function_calls 296648 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1077081 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8166400 # Number of memory references committed +system.cpu2.commit.loads 4919560 # Number of loads committed +system.cpu2.commit.membars 94646 # Number of memory barriers committed +system.cpu2.commit.branches 3146883 # Number of branches committed +system.cpu2.commit.fp_insts 2975 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21821277 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294032 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 966884 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66956650 # The number of ROB reads -system.cpu2.rob.rob_writes 66650908 # The number of ROB writes -system.cpu2.timesIdled 359376 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51265738 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3569532047 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20984673 # Number of Instructions Simulated -system.cpu2.committedOps 25899696 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20984673 # Number of Instructions Simulated -system.cpu2.cpi 4.204023 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.204023 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.237867 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.237867 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 160070437 # number of integer regfile reads -system.cpu2.int_regfile_writes 30477342 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22294 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20824 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9434068 # number of misc regfile reads -system.cpu2.misc_regfile_writes 244358 # number of misc regfile writes +system.cpu2.rob.rob_reads 66205278 # The number of ROB reads +system.cpu2.rob.rob_writes 64842405 # The number of ROB writes +system.cpu2.timesIdled 359398 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51252392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567238209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19827262 # Number of Instructions Simulated +system.cpu2.committedOps 24525524 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19827262 # Number of Instructions Simulated +system.cpu2.cpi 4.454488 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.454488 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.224493 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.224493 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153057849 # number of integer regfile reads +system.cpu2.int_regfile_writes 29069811 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22288 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20782 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9001591 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241415 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1524,10 +1521,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925532055074 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 925532055074 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925532055074 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 925532055074 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981127238281 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981127238281 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981127238281 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981127238281 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 0ccf41cf5..5746894a9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.540276 # Number of seconds simulated -sim_ticks 2540275734000 # Number of ticks simulated -final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542409 # Number of seconds simulated +sim_ticks 2542409356000 # Number of ticks simulated +final_tick 2542409356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50621 # Simulator instruction rate (inst/s) -host_op_rate 65136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2132095179 # Simulator tick rate (ticks/s) -host_mem_usage 455960 # Number of bytes of host memory used -host_seconds 1191.45 # Real time elapsed on the host -sim_insts 60312498 # Number of instructions simulated -sim_ops 77605759 # Number of ops (including micro ops) simulated +host_inst_rate 77322 # Simulator instruction rate (inst/s) +host_op_rate 99492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3259551931 # Simulator tick rate (ticks/s) +host_mem_usage 413868 # Number of bytes of host memory used +host_seconds 779.99 # Real time elapsed on the host +sim_insts 60310148 # Number of instructions simulated +sim_ops 77602492 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 405568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3860688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 506624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4283408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5229152 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 405568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783168 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1412956 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1603284 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 292928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4810268 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006892 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 506624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 292928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1340604 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1675508 # Number of bytes written to this memory +system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 60357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81713 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59112 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 353239 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 400821 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813172 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47676135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 605 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 4577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75167 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 335151 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 418877 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47636124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 629 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1519791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1684783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 529 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 155498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2058498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51570836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 155498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315153 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 556222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 631146 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47676135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1892012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51528638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115217 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 527297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 659024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2675881 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47636124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 629 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2076012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 199269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2212080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 529 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 155498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2689643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54247478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293445 # Total number of read requests seen -system.physmem.writeReqs 813172 # Total number of write requests seen -system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978780480 # Total number of bytes read from memory -system.physmem.bytesWritten 52043008 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131004144 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.bw_total::cpu1.inst 115217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2551035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54204519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293487 # Total number of read requests seen +system.physmem.writeReqs 813201 # Total number of write requests seen +system.physmem.cpureqs 218488 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978783168 # Total number of bytes read from memory +system.physmem.bytesWritten 52044864 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131006892 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955910 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955538 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955410 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955922 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955719 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50359 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50035 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50823 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51147 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51116 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51295 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51031 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 956241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955557 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956091 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955522 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50805 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51195 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50636 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51230 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 693675 # Number of times wr buffer was full causing retry -system.physmem.totGap 2540274436500 # Total gap between requests +system.physmem.numWrRetry 1790732 # Number of times wr buffer was full causing retry +system.physmem.totGap 2542408198000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 44 # Categorize read packet sizes +system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154585 # Categorize read packet sizes +system.physmem.readPktSize::6 154628 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1447735 # categorize write packet sizes +system.physmem.writePktSize::2 2544760 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59112 # categorize write packet sizes +system.physmem.writePktSize::6 59173 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -141,28 +141,28 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1057043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 949780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 984222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2774561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2777593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5475568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 36103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 31668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 59387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1054866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -174,60 +174,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 31872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 31784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 31663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 31190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 30814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 30644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 30396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 31921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 31858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31605 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 295222941913 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 372544627913 # Sum of mem lat for all requests -system.physmem.totBusLat 61173736000 # Total cycles spent in databus access -system.physmem.totBankLat 16147950000 # Total cycles spent in bank access -system.physmem.avgQLat 19303.90 # Average queueing delay per request -system.physmem.avgBankLat 1055.87 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24359.78 # Average memory access latency -system.physmem.avgRdBW 385.30 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.49 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.57 # Average consumed read bandwidth in MB/s +system.physmem.totQLat 346733530557 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439908911807 # Sum of mem lat for all requests +system.physmem.totBusLat 76467385000 # Total cycles spent in databus access +system.physmem.totBankLat 16707996250 # Total cycles spent in bank access +system.physmem.avgQLat 22671.99 # Average queueing delay per request +system.physmem.avgBankLat 1092.49 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28764.48 # Average memory access latency +system.physmem.avgRdBW 384.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.54 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.17 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 1.11 # Average write queue length over time -system.physmem.readRowHits 15250779 # Number of row buffer hits during reads -system.physmem.writeRowHits 786181 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.68 # Row buffer hit rate for writes -system.physmem.avgGap 157716.20 # Average gap between requests +system.physmem.readRowHits 15218342 # Number of row buffer hits during reads +system.physmem.writeRowHits 794645 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes +system.physmem.avgGap 157847.98 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -240,245 +240,239 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64355 # number of replacements -system.l2c.tagsinuse 51419.267755 # Cycle average of tags in use -system.l2c.total_refs 1938049 # Total number of references to valid blocks. -system.l2c.sampled_refs 129745 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.937369 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2504164034000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36931.020579 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 16.606352 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000348 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4513.419817 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3324.401102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 19.072216 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.003905 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3703.882826 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2910.860610 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563523 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000253 # Average percentage of cache occupancy +system.l2c.replacements 64396 # number of replacements +system.l2c.tagsinuse 51411.059605 # Cycle average of tags in use +system.l2c.total_refs 1936288 # Total number of references to valid blocks. +system.l2c.sampled_refs 129787 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.918967 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2506346605000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36969.089517 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 15.370678 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050907 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94280181421 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95790429550 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190075661878 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025275 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015434 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989355 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988113 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988787 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.523087 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.558292 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541393 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.089857 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.089857 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44398.583251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46287.086671 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.967196 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.681646 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.748110 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39996.972474 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 36779.206178 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38271.613142 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -685,680 +667,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6894641 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5490275 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 340467 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4496048 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3641169 # Number of BTB hits +system.cpu0.branchPred.lookups 7548901 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6013590 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377467 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4898170 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4008296 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.985990 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672237 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 35025 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.832521 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 726547 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38944 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25321176 # DTB read hits -system.cpu0.dtb.read_misses 39544 # DTB read misses -system.cpu0.dtb.write_hits 5538222 # DTB write hits -system.cpu0.dtb.write_misses 9025 # DTB write misses -system.cpu0.dtb.flush_tlb 256 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25977003 # DTB read hits +system.cpu0.dtb.read_misses 44168 # DTB read misses +system.cpu0.dtb.write_hits 5905544 # DTB write hits +system.cpu0.dtb.write_misses 10435 # DTB write misses +system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 7899 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1433 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 8487 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1476 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25360720 # DTB read accesses -system.cpu0.dtb.write_accesses 5547247 # DTB write accesses +system.cpu0.dtb.perms_faults 629 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26021171 # DTB read accesses +system.cpu0.dtb.write_accesses 5915979 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30859398 # DTB hits -system.cpu0.dtb.misses 48569 # DTB misses -system.cpu0.dtb.accesses 30907967 # DTB accesses -system.cpu0.itb.inst_hits 5399990 # ITB inst hits -system.cpu0.itb.inst_misses 6797 # ITB inst misses +system.cpu0.dtb.hits 31882547 # DTB hits +system.cpu0.dtb.misses 54603 # DTB misses +system.cpu0.dtb.accesses 31937150 # DTB accesses +system.cpu0.itb.inst_hits 6053570 # ITB inst hits +system.cpu0.itb.inst_misses 7437 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 256 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2645 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2703 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1504 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5406787 # ITB inst accesses -system.cpu0.itb.hits 5399990 # DTB hits -system.cpu0.itb.misses 6797 # DTB misses -system.cpu0.itb.accesses 5406787 # DTB accesses -system.cpu0.numCycles 232916834 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6061007 # ITB inst accesses +system.cpu0.itb.hits 6053570 # DTB hits +system.cpu0.itb.misses 7437 # DTB misses +system.cpu0.itb.accesses 6061007 # DTB accesses +system.cpu0.numCycles 238938486 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4313406 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9542116 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2097502 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81571 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47928082 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 983 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1918 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 48764 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 90424 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5397887 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 280481 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3116 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 73293713 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.724548 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.073228 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15394391 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47363199 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7548901 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4734843 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10514679 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2521350 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 88217 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49746520 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 54986 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 100350 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6051440 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 388609 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3416 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77647495 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.755624 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.112120 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63759289 86.99% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 642563 0.88% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816896 1.11% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1076628 1.47% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1030388 1.41% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 525946 0.72% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1160801 1.58% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 367124 0.50% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3914078 5.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67140338 86.47% 86.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 685224 0.88% 87.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 881384 1.14% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1215413 1.57% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1119001 1.44% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 577018 0.74% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1310230 1.69% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 395483 0.51% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4323404 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 73293713 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029601 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.183647 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15070134 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 47635747 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8687716 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 522868 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1375117 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 927671 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 82962 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 50805033 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 279607 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1375117 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 15858431 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18747322 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 25731690 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8353206 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3225899 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 48905504 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13838 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 630791 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2093496 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 12811 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 50688794 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 222549147 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 222507399 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 41748 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38461100 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12227693 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 386484 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 344770 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6389877 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9452191 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6279292 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 988040 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1320602 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 45692134 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 977389 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 60037368 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 85152 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8499333 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 20279389 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 254746 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 73293713 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.819134 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.521823 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77647495 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031593 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.198223 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16447301 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49466389 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9519649 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 555058 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1656976 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1018880 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89951 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 55851060 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301878 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1656976 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17376198 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19158247 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27017971 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9071618 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3364444 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53098048 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 14247 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 629745 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2187800 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 13035 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55196889 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241870306 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 241822297 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48009 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40273759 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14923130 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 426834 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 378971 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6800028 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10269000 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6780798 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1063277 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1318043 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49318736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1023913 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62924434 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96522 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10293246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26052938 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 249929 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77647495 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.810386 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.515841 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 51609317 70.41% 70.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6835660 9.33% 79.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3457344 4.72% 84.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2997093 4.09% 88.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6031042 8.23% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1346418 1.84% 98.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 738853 1.01% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 217523 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 60463 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54849449 70.64% 70.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7244024 9.33% 79.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3688560 4.75% 84.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3114192 4.01% 88.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6252852 8.05% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1400137 1.80% 98.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 804405 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 228817 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65059 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 73293713 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77647495 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26194 0.60% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4172771 94.90% 95.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 28907 0.65% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 5 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221672 94.79% 95.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 203228 4.56% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 194561 0.32% 0.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28037950 46.70% 47.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 44753 0.07% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 838 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 25907736 43.15% 90.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5851514 9.75% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 196078 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29762339 47.30% 47.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47254 0.08% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1214 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26685508 42.41% 90.10% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6232016 9.90% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 60037368 # Type of FU issued -system.cpu0.iq.rate 0.257763 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4397050 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073239 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 197888427 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 55177485 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 41654501 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10625 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5737 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4733 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 64234192 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5665 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 298497 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62924434 # Type of FU issued +system.cpu0.iq.rate 0.263350 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4453812 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070780 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208088796 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60644934 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43952872 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12311 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6553 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67175656 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6512 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 321336 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1811405 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3010 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 725021 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2241404 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3447 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16174 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 877395 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17048224 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 266574 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17145295 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 358927 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1375117 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14032156 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 223286 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 46775692 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 94480 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9452191 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6279292 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 703336 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 50186 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4000 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 14875 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 165277 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 131199 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 296476 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59245437 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 25661722 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 791931 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1656976 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14313344 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 236698 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50458165 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105115 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10269000 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6780798 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 724480 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 58024 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3552 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16174 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184745 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145643 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 330388 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61778089 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26333265 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1146345 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 106169 # number of nop insts executed -system.cpu0.iew.exec_refs 31462090 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5561458 # Number of branches executed -system.cpu0.iew.exec_stores 5800368 # Number of stores executed -system.cpu0.iew.exec_rate 0.254363 # Inst execution rate -system.cpu0.iew.wb_sent 58848296 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 41659234 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23213315 # num instructions producing a value -system.cpu0.iew.wb_consumers 42468919 # num instructions consuming a value +system.cpu0.iew.exec_nop 115516 # number of nop insts executed +system.cpu0.iew.exec_refs 32508411 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5980040 # Number of branches executed +system.cpu0.iew.exec_stores 6175146 # Number of stores executed +system.cpu0.iew.exec_rate 0.258552 # Inst execution rate +system.cpu0.iew.wb_sent 61260719 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43958394 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24186405 # num instructions producing a value +system.cpu0.iew.wb_consumers 44536826 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.178859 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546595 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.183974 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543065 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8329034 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 722643 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 258629 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 71918596 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.527800 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.514238 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10181243 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 773984 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 288739 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75990519 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.523900 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.505441 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 58433692 81.25% 81.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6549576 9.11% 90.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1938281 2.70% 93.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1064527 1.48% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 992329 1.38% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 495986 0.69% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 654165 0.91% 97.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 355670 0.49% 98.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1434370 1.99% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61812445 81.34% 81.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6884323 9.06% 90.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2031918 2.67% 93.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1127942 1.48% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1041381 1.37% 95.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 554423 0.73% 96.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 699295 0.92% 97.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 364332 0.48% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1474460 1.94% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 71918596 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29885048 # Number of instructions committed -system.cpu0.commit.committedOps 37958605 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75990519 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31157319 # Number of instructions committed +system.cpu0.commit.committedOps 39811398 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13195057 # Number of memory references committed -system.cpu0.commit.loads 7640786 # Number of loads committed -system.cpu0.commit.membars 194107 # Number of memory barriers committed -system.cpu0.commit.branches 4848128 # Number of branches committed -system.cpu0.commit.fp_insts 4699 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33604858 # Number of committed integer instructions. -system.cpu0.commit.function_calls 476381 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1434370 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13930999 # Number of memory references committed +system.cpu0.commit.loads 8027596 # Number of loads committed +system.cpu0.commit.membars 211461 # Number of memory barriers committed +system.cpu0.commit.branches 5178005 # Number of branches committed +system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35182368 # Number of committed integer instructions. +system.cpu0.commit.function_calls 511213 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1474460 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 115883530 # The number of ROB reads -system.cpu0.rob.rob_writes 93994803 # The number of ROB writes -system.cpu0.timesIdled 855495 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 159623121 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2324012553 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29813564 # Number of Instructions Simulated -system.cpu0.committedOps 37887121 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29813564 # Number of Instructions Simulated -system.cpu0.cpi 7.812445 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.812445 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.128001 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.128001 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 268137987 # number of integer regfile reads -system.cpu0.int_regfile_writes 42752144 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22081 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19566 # number of floating regfile writes -system.cpu0.misc_regfile_reads 14602892 # number of misc regfile reads -system.cpu0.misc_regfile_writes 394034 # number of misc regfile writes -system.cpu0.icache.replacements 984960 # number of replacements -system.cpu0.icache.tagsinuse 511.605628 # Cycle average of tags in use -system.cpu0.icache.total_refs 10192469 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 985472 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.342728 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6475146000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 192.391014 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 319.214614 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.375764 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.623466 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999230 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 4895846 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5296623 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10192469 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4895846 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5296623 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10192469 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4895846 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5296623 # number of overall hits -system.cpu0.icache.overall_hits::total 10192469 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 501920 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 563999 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065919 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 501920 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 563999 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065919 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 501920 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 563999 # number of overall misses -system.cpu0.icache.overall_misses::total 1065919 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6726188495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7525770495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14251958990 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6726188495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7525770495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14251958990 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6726188495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7525770495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14251958990 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5397766 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5860622 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11258388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5397766 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5860622 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11258388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5397766 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5860622 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11258388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092987 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.096235 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.094678 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092987 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.096235 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.094678 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092987 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.096235 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.094678 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13400.917467 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13343.588366 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13370.583496 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13370.583496 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13370.583496 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5202 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 775 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 345 # number of cycles access was blocked +system.cpu0.rob.rob_reads 123547695 # The number of ROB reads +system.cpu0.rob.rob_writes 101683929 # The number of ROB writes +system.cpu0.timesIdled 881879 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161290991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289851507 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31079277 # Number of Instructions Simulated +system.cpu0.committedOps 39733356 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31079277 # Number of Instructions Simulated +system.cpu0.cpi 7.688032 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.688032 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130072 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130072 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 279629599 # number of integer regfile reads +system.cpu0.int_regfile_writes 45168223 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22746 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19898 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15538839 # number of misc regfile reads +system.cpu0.misc_regfile_writes 427973 # number of misc regfile writes +system.cpu0.icache.replacements 984670 # number of replacements +system.cpu0.icache.tagsinuse 511.607871 # Cycle average of tags in use +system.cpu0.icache.total_refs 10994375 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 985182 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.159740 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6536916000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 357.062519 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 154.545352 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.697388 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.301846 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999234 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7287778496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7022356993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14310135489 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6051317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 6008406 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12059723 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6051317 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 6008406 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12059723 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6051317 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 6008406 # 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average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13314.923053 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13432.357773 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.492013 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13314.923053 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13432.357773 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.492013 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13314.923053 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13432.357773 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1635 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 334 # 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number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11618272991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6767000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6767000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6767000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 6767000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087535 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088895 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40608 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39535 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80143 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 40608 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39535 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80143 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 40608 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39535 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80143 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 497335 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 487870 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 985205 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 497335 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 487870 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 985205 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 497335 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 487870 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 985205 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5948053496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5711985994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11660039490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5948053496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5711985994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11660039490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5948053496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5711985994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11660039490 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.082186 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081198 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081694 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.082186 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081198 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081694 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.082186 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081198 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081694 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11959.853009 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11708.008269 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.140392 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11959.853009 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11708.008269 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.140392 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11959.853009 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11708.008269 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.140392 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643643 # number of replacements -system.cpu0.dcache.tagsinuse 511.994132 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21553843 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644155 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.460647 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36157000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 257.044618 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 254.949514 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.502040 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.497948 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6668355 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 7127763 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13796118 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3513738 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3750110 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7263848 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119013 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 124173 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243186 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120748 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 126887 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247635 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10182093 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10877873 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21059966 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10182093 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10877873 # number of overall hits -system.cpu0.dcache.overall_hits::total 21059966 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 398872 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 347013 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 745885 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1308679 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1650694 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2959373 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5990 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 7586 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1707551 # 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number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1666394 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3070341 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191049 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 194866 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 385915 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 112555 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 136447 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249002 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5320 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6854 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12174 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3585837983 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4828490940 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8414328923 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 62428500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81807000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144235500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 89000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6175136983 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7422009940 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13597146923 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6175136983 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7422009940 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13597146923 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91055617500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91310638500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182366256000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 10805151656 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13444453545 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 24249605201 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 607854 # number of writebacks +system.cpu0.dcache.writebacks::total 607854 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 215439 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 144497 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 359936 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1276945 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1433111 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2710056 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 667 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 710 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1377 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1492384 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1577608 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3069992 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1492384 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1577608 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3069992 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211079 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 174740 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385819 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119679 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129263 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248942 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6103 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6084 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 330758 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 304003 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634761 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 330758 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 304003 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634761 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2867323500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2359031500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5226355000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4068255992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4371447438 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8439703430 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71165500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73921500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145087000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6935579492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6730478938 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13666058430 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6935579492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6730478938 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13666058430 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91842786000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90513364000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356150000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14606778738 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18392840622 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32999619360 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101860769156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104755092045 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206615861201 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027033 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026070 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026538 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023340 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025264 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042559 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052019 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047414 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025637 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025637 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13553.062303 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13309.243275 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13429.947009 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31858.540118 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35387.300124 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33792.214211 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11734.680451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11935.658010 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.831444 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12846.153846 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106449564738 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 108906204622 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215355769360 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028155 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024825 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026543 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023127 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025607 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046279 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048510 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000024 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025638 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025638 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13584.124901 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.237496 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13546.131735 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33993.064715 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33818.242173 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33902.288204 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11660.740619 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12150.147929 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.062772 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1373,324 +1355,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7461261 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5924878 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 387688 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4864845 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3916001 # Number of BTB hits +system.cpu1.branchPred.lookups 7102253 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5695769 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 349355 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4570648 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3841672 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.495905 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 732677 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 39651 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.050927 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 676938 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35276 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25842433 # DTB read hits -system.cpu1.dtb.read_misses 46174 # DTB read misses -system.cpu1.dtb.write_hits 6180963 # DTB write hits -system.cpu1.dtb.write_misses 11315 # DTB write misses +system.cpu1.dtb.read_hits 25380131 # DTB read hits +system.cpu1.dtb.read_misses 40834 # DTB read misses +system.cpu1.dtb.write_hits 5811015 # DTB write hits +system.cpu1.dtb.write_misses 9771 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 8574 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1449 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1494 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 622 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25888607 # DTB read accesses -system.cpu1.dtb.write_accesses 6192278 # DTB write accesses +system.cpu1.dtb.perms_faults 637 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25420965 # DTB read accesses +system.cpu1.dtb.write_accesses 5820786 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 32023396 # DTB hits -system.cpu1.dtb.misses 57489 # DTB misses -system.cpu1.dtb.accesses 32080885 # DTB accesses -system.cpu1.itb.inst_hits 5862958 # ITB inst hits -system.cpu1.itb.inst_misses 7630 # ITB inst misses +system.cpu1.dtb.hits 31191146 # DTB hits +system.cpu1.dtb.misses 50605 # DTB misses +system.cpu1.dtb.accesses 31241751 # DTB accesses +system.cpu1.itb.inst_hits 6010554 # ITB inst hits +system.cpu1.itb.inst_misses 6924 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2762 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2690 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1655 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5870588 # ITB inst accesses -system.cpu1.itb.hits 5862958 # DTB hits -system.cpu1.itb.misses 7630 # DTB misses -system.cpu1.itb.accesses 5870588 # DTB accesses -system.cpu1.numCycles 238328292 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6017478 # ITB inst accesses +system.cpu1.itb.hits 6010554 # DTB hits +system.cpu1.itb.misses 6924 # DTB misses +system.cpu1.itb.accesses 6017478 # DTB accesses +system.cpu1.numCycles 234669310 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4648678 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10301295 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2449187 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 90048 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49530341 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2013 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 58322 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 105488 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5860623 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 343915 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3550 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 77436496 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.743507 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.098927 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15209580 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46712783 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7102253 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4518610 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10317375 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2619576 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 83943 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47843149 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2062 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 49108 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 95676 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 6008408 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 439180 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3193 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 75397416 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.769986 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.133362 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 67142740 86.71% 86.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 670388 0.87% 87.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 904116 1.17% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1146258 1.48% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1035072 1.34% 91.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 585216 0.76% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1324002 1.71% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 382858 0.49% 94.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4245846 5.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65087895 86.33% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 627947 0.83% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 837408 1.11% 88.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1205044 1.60% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1066340 1.41% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 537838 0.71% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1370888 1.82% 93.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 355288 0.47% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4308768 5.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 77436496 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031307 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.191852 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16603606 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49335429 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9407116 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 490405 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1597859 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1045633 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 93792 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54840588 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 310696 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1597859 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17482170 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19064051 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27065673 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8938575 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3286155 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 52466184 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7798 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 497565 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2245284 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 18515 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54189093 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 239808372 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 239759506 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 48866 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39935280 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14253813 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 446450 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 393915 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6702948 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10122887 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6990261 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 974914 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1217289 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48733638 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1005144 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62551860 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 96432 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9690546 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24103101 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245099 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 77436496 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.807783 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.518787 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 75397416 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030265 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199058 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16234163 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47629419 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9365333 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 455355 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1710994 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 954633 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86850 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54991941 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 289065 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1710994 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17174187 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18737860 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25818505 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8802452 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3151356 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51852963 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7784 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 495819 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2156102 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 16790 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53921236 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237794819 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237752758 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42061 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38119457 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15801778 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 406275 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 360043 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6312412 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9898501 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6682455 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 887681 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1092966 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47793867 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 962748 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60992947 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 83561 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10588710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27790687 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 254225 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 75397416 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.808953 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.518534 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54919142 70.92% 70.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7063904 9.12% 80.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3691282 4.77% 84.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2953327 3.81% 88.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6235094 8.05% 96.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1492250 1.93% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 791283 1.02% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 225625 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64589 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53544512 71.02% 71.02% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6720979 8.91% 79.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3575565 4.74% 84.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2884458 3.83% 88.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6227948 8.26% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1437657 1.91% 98.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 736271 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210447 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59579 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 77436496 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 75397416 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27571 0.62% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4198494 94.58% 95.20% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 213042 4.80% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24253 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4149284 94.86% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200652 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 169105 0.27% 0.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29343777 46.91% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 48983 0.08% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1277 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26498919 42.36% 89.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6489779 10.38% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 167588 0.27% 0.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28559163 46.82% 47.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46488 0.08% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 897 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26112884 42.81% 89.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6105909 10.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62551860 # Type of FU issued -system.cpu1.iq.rate 0.262461 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4439108 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070967 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 207120715 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59438377 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43832825 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12343 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6735 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5565 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66815352 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6511 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 325479 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60992947 # Type of FU issued +system.cpu1.iq.rate 0.259910 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4374192 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071716 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201880877 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59353845 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41952881 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10603 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5821 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4743 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65193949 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5602 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306044 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2107508 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3797 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 16351 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 811464 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2270775 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14837 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 853246 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17060218 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 341441 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16957357 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 451019 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1597859 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14264833 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 247482 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49856426 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 107204 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10122887 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6990261 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 704284 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 59901 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3604 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 16351 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 190247 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 149600 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 339847 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61552998 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 26188496 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 998862 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1710994 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14077639 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 237686 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48863462 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 99358 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9898501 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6682455 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 687943 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 54116 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4064 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14837 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 169399 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135230 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 304629 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59633634 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25710347 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1359313 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 117644 # number of nop insts executed -system.cpu1.iew.exec_refs 32619530 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5900270 # Number of branches executed -system.cpu1.iew.exec_stores 6431034 # Number of stores executed -system.cpu1.iew.exec_rate 0.258270 # Inst execution rate -system.cpu1.iew.wb_sent 61059596 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43838390 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23681235 # num instructions producing a value -system.cpu1.iew.wb_consumers 43694541 # num instructions consuming a value +system.cpu1.iew.exec_nop 106847 # number of nop insts executed +system.cpu1.iew.exec_refs 31763994 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5570991 # Number of branches executed +system.cpu1.iew.exec_stores 6053647 # Number of stores executed +system.cpu1.iew.exec_rate 0.254118 # Inst execution rate +system.cpu1.iew.wb_sent 59059835 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41957624 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22877560 # num instructions producing a value +system.cpu1.iew.wb_consumers 41856848 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.183941 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.541972 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178795 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.546567 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9661212 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 760045 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 295282 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75838637 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.524766 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.504226 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10488461 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 708523 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 263786 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73686422 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.514905 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.496046 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61579117 81.20% 81.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7021291 9.26% 90.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2015124 2.66% 93.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1085811 1.43% 94.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1003078 1.32% 95.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 577963 0.76% 96.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 742657 0.98% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378274 0.50% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1435322 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60141742 81.62% 81.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6665026 9.05% 90.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1916982 2.60% 93.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1022287 1.39% 94.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 952512 1.29% 95.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 518669 0.70% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 704589 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 372223 0.51% 98.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1392392 1.89% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75838637 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30577831 # Number of instructions committed -system.cpu1.commit.committedOps 39797535 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73686422 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29303210 # Number of instructions committed +system.cpu1.commit.committedOps 37941475 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 14194176 # Number of memory references committed -system.cpu1.commit.loads 8015379 # Number of loads committed -system.cpu1.commit.membars 209589 # Number of memory barriers committed -system.cpu1.commit.branches 5113967 # Number of branches committed -system.cpu1.commit.fp_insts 5513 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35255841 # Number of committed integer instructions. -system.cpu1.commit.function_calls 515004 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1435322 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13456935 # Number of memory references committed +system.cpu1.commit.loads 7627726 # Number of loads committed +system.cpu1.commit.membars 192181 # Number of memory barriers committed +system.cpu1.commit.branches 4783662 # Number of branches committed +system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33675461 # Number of committed integer instructions. +system.cpu1.commit.function_calls 480108 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1392392 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 122900984 # The number of ROB reads -system.cpu1.rob.rob_writes 100566633 # The number of ROB writes -system.cpu1.timesIdled 901138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160891796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2255172449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30498934 # Number of Instructions Simulated -system.cpu1.committedOps 39718638 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30498934 # Number of Instructions Simulated -system.cpu1.cpi 7.814315 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.814315 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127970 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127970 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 279110946 # number of integer regfile reads -system.cpu1.int_regfile_writes 44685160 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22658 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19886 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15820673 # number of misc regfile reads -system.cpu1.misc_regfile_writes 438571 # number of misc regfile writes +system.cpu1.rob.rob_reads 119835622 # The number of ROB reads +system.cpu1.rob.rob_writes 98622587 # The number of ROB writes +system.cpu1.timesIdled 873829 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159271894 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285541005 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29230871 # Number of Instructions Simulated +system.cpu1.committedOps 37869136 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29230871 # Number of Instructions Simulated +system.cpu1.cpi 8.028133 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.028133 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124562 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124562 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 270257014 # number of integer regfile reads +system.cpu1.int_regfile_writes 43086162 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22099 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19636 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14849439 # number of misc regfile reads +system.cpu1.misc_regfile_writes 404495 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1705,17 +1687,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1125362728944 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1125362728944 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192737213912 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192737213912 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83058 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83053 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 133b16bb8..cc1497460 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.609477 # Number of seconds simulated -sim_ticks 2609476867000 # Number of ticks simulated -final_tick 2609476867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.608779 # Number of seconds simulated +sim_ticks 2608778789000 # Number of ticks simulated +final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 397155 # Simulator instruction rate (inst/s) -host_op_rate 505377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17213891867 # Simulator tick rate (ticks/s) -host_mem_usage 448796 # Number of bytes of host memory used -host_seconds 151.59 # Real time elapsed on the host -sim_insts 60205243 # Number of instructions simulated -sim_ops 76610733 # Number of ops (including micro ops) simulated +host_inst_rate 458042 # Simulator instruction rate (inst/s) +host_op_rate 582855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19847185908 # Simulator tick rate (ticks/s) +host_mem_usage 403628 # Number of bytes of host memory used +host_seconds 131.44 # Real time elapsed on the host +sim_insts 60206536 # Number of instructions simulated +sim_ops 76612339 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 349152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4456460 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 356032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4588440 # Number of bytes read from this memory -system.physmem.bytes_read::total 132433668 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 349152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 356032 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4486284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4557412 # Number of bytes read from this memory +system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522768 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1493500 # Number of bytes written to this memory -system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1520308 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1495832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71715 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380692 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373375 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47014554 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 71233 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380077 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373958 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 133802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1707798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 136438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1758375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50751041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 133802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 136438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1407424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 583553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 572337 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2563314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1407424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47014554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1719687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1746952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 582766 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 573384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 133802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2291351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 136438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2330712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53314355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494028 # Total number of read requests seen -system.physmem.writeReqs 811452 # Total number of write requests seen -system.physmem.cpureqs 213833 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991617792 # Total number of bytes read from memory -system.physmem.bytesWritten 51932928 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132433668 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2302454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2320336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494012 # Total number of read requests seen +system.physmem.writeReqs 811397 # Total number of write requests seen +system.physmem.cpureqs 213789 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991616768 # Total number of bytes read from memory +system.physmem.bytesWritten 51929408 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132432464 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6687308 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4517 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 968429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967970 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967933 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967538 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 974536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 968050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 968196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 968244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967963 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50348 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 49920 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50745 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 50919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51015 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51209 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51259 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 974838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967895 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 968555 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 968388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 968240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968019 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967639 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967512 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50747 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50200 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50721 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2609472479500 # Total gap between requests +system.physmem.totGap 2608774377500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6673 # Categorize read packet sizes +system.physmem.readPktSize::2 6676 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 151931 # Categorize read packet sizes +system.physmem.readPktSize::6 151912 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 754067 # categorize write packet sizes +system.physmem.writePktSize::2 754035 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57385 # categorize write packet sizes +system.physmem.writePktSize::6 57362 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -130,26 +130,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4517 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4515 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1117981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 962159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 962420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 998543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2811240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2816443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5545406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 36112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 58787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 30559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 58397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1116413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3651904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2754719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2759720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2733933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 61766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 162702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -166,30 +166,30 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35321 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -199,27 +199,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 286738639625 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 365542479625 # Sum of mem lat for all requests -system.physmem.totBusLat 61976008000 # Total cycles spent in databus access -system.physmem.totBankLat 16827832000 # Total cycles spent in bank access -system.physmem.avgQLat 18506.43 # Average queueing delay per request -system.physmem.avgBankLat 1086.09 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23592.52 # Average memory access latency -system.physmem.avgRdBW 380.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.75 # Average consumed read bandwidth in MB/s +system.physmem.totQLat 338341857800 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 433208122800 # Sum of mem lat for all requests +system.physmem.totBusLat 77469930000 # Total cycles spent in databus access +system.physmem.totBankLat 17396335000 # Total cycles spent in bank access +system.physmem.avgQLat 21836.98 # Average queueing delay per request +system.physmem.avgBankLat 1122.78 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27959.76 # Average memory access latency +system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.50 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 1.25 # Average write queue length over time -system.physmem.readRowHits 15452119 # Number of row buffer hits during reads -system.physmem.writeRowHits 785190 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes -system.physmem.avgGap 160036.53 # Average gap between requests +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 1.24 # Average write queue length over time +system.physmem.readRowHits 15419486 # Number of row buffer hits during reads +system.physmem.writeRowHits 793977 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes +system.physmem.avgGap 159994.42 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -232,205 +232,205 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 61820 # number of replacements -system.l2c.tagsinuse 50921.903557 # Cycle average of tags in use -system.l2c.total_refs 1697937 # Total number of references to valid blocks. -system.l2c.sampled_refs 127204 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.348142 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2557805301500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37911.972595 # Average occupied blocks per requestor +system.l2c.replacements 61800 # number of replacements +system.l2c.tagsinuse 50918.253702 # Cycle average of tags in use +system.l2c.total_refs 1698591 # Total number of references to valid blocks. +system.l2c.sampled_refs 127185 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.355278 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2557152484500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37907.717848 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000639 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3578.783807 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2862.372936 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3416.906879 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3151.866517 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.578491 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.000642 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4327.115126 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3096.490855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2668.881351 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2918.047697 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.578426 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.054608 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043676 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.052138 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.048094 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.777007 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9713 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3454 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 390514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 186540 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9847 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 453502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 184024 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241218 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596393 # number of Writeback hits -system.l2c.Writeback_hits::total 596393 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.066027 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.047249 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.040724 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044526 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.776951 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 10142 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3715 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 409497 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188260 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9560 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3405 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 434855 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 182318 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241752 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596435 # number of Writeback hits +system.l2c.Writeback_hits::total 596435 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58662 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114563 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9713 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 390514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 242441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9847 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 453502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 242686 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355781 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9713 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3454 # number of overall hits -system.l2c.overall_hits::cpu0.inst 390514 # number of overall hits -system.l2c.overall_hits::cpu0.data 242441 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9847 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3624 # number of overall hits -system.l2c.overall_hits::cpu1.inst 453502 # number of overall hits -system.l2c.overall_hits::cpu1.data 242686 # number of overall hits -system.l2c.overall_hits::total 1355781 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57590 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56979 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114569 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 10142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3715 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 409497 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 245850 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9560 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3405 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 434855 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 239297 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356321 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10142 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3715 # number of overall hits +system.l2c.overall_hits::cpu0.inst 409497 # number of overall hits +system.l2c.overall_hits::cpu0.data 245850 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9560 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3405 # number of overall hits +system.l2c.overall_hits::cpu1.inst 434855 # number of overall hits +system.l2c.overall_hits::cpu1.data 239297 # number of overall hits +system.l2c.overall_hits::total 1356321 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5042 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5096 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5563 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4755 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20459 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1441 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1437 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2878 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65351 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67760 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133111 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 6138 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5512 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4467 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4338 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20458 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1394 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2871 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.223868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.231377 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101701 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39576.914187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43258.955970 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40924.497507 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.401490 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.096830 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.105197 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33566.811232 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33076.563652 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -588,135 +588,135 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7346324 # DTB read hits -system.cpu0.dtb.read_misses 6876 # DTB read misses -system.cpu0.dtb.write_hits 5393725 # DTB write hits -system.cpu0.dtb.write_misses 1788 # DTB write misses -system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7507423 # DTB read hits +system.cpu0.dtb.read_misses 6880 # DTB read misses +system.cpu0.dtb.write_hits 5552288 # DTB write hits +system.cpu0.dtb.write_misses 1844 # DTB write misses +system.cpu0.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6380 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6531 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 236 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7353200 # DTB read accesses -system.cpu0.dtb.write_accesses 5395513 # DTB write accesses +system.cpu0.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7514303 # DTB read accesses +system.cpu0.dtb.write_accesses 5554132 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12740049 # DTB hits -system.cpu0.dtb.misses 8664 # DTB misses -system.cpu0.dtb.accesses 12748713 # DTB accesses -system.cpu0.itb.inst_hits 30077314 # ITB inst hits -system.cpu0.itb.inst_misses 3618 # ITB inst misses +system.cpu0.dtb.hits 13059711 # DTB hits +system.cpu0.dtb.misses 8724 # DTB misses +system.cpu0.dtb.accesses 13068435 # DTB accesses +system.cpu0.itb.inst_hits 30766737 # ITB inst hits +system.cpu0.itb.inst_misses 3610 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2643 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2714 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30080932 # ITB inst accesses -system.cpu0.itb.hits 30077314 # DTB hits -system.cpu0.itb.misses 3618 # DTB misses -system.cpu0.itb.accesses 30080932 # DTB accesses -system.cpu0.numCycles 2667978103 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30770347 # ITB inst accesses +system.cpu0.itb.hits 30766737 # DTB hits +system.cpu0.itb.misses 3610 # DTB misses +system.cpu0.itb.accesses 30770347 # DTB accesses +system.cpu0.numCycles 2552892042 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29443364 # Number of instructions committed -system.cpu0.committedOps 37313873 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33552683 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4308 # Number of float alu accesses -system.cpu0.num_func_calls 997498 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3872350 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33552683 # number of integer instructions -system.cpu0.num_fp_insts 4308 # number of float instructions -system.cpu0.num_int_register_reads 192457043 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36187608 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3214 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1096 # number of times the floating registers were written -system.cpu0.num_mem_refs 13317945 # number of memory refs -system.cpu0.num_load_insts 7675788 # Number of load instructions -system.cpu0.num_store_insts 5642157 # Number of store instructions -system.cpu0.num_idle_cycles 1511306252.685236 # Number of idle cycles -system.cpu0.num_busy_cycles 1156671850.314764 # Number of busy cycles -system.cpu0.not_idle_fraction 0.433539 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.566461 # Percentage of idle cycles +system.cpu0.committedInsts 30144083 # Number of instructions committed +system.cpu0.committedOps 38293118 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34424567 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5276 # Number of float alu accesses +system.cpu0.num_func_calls 1041312 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4017319 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34424567 # number of integer instructions +system.cpu0.num_fp_insts 5276 # number of float instructions +system.cpu0.num_int_register_reads 197342497 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37147622 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3922 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1356 # number of times the floating registers were written +system.cpu0.num_mem_refs 13659512 # number of memory refs +system.cpu0.num_load_insts 7847120 # Number of load instructions +system.cpu0.num_store_insts 5812392 # Number of store instructions +system.cpu0.num_idle_cycles 3486759367.777020 # Number of idle cycles +system.cpu0.num_busy_cycles -933867325.777020 # Number of busy cycles +system.cpu0.not_idle_fraction -0.365808 # Percentage of non-idle cycles +system.cpu0.idle_fraction 1.365808 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83014 # number of quiesce instructions executed -system.cpu0.icache.replacements 855749 # number of replacements -system.cpu0.icache.tagsinuse 510.984146 # Cycle average of tags in use -system.cpu0.icache.total_refs 60643040 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 856261 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 70.823078 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 18731806000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 165.100321 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 345.883825 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.322462 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.675554 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29681003 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30962037 # 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miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014638 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013923 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013176 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014638 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013923 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013176 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014638 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013923 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13523.601414 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13502.970975 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13512.519547 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13512.519547 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13512.519547 # average overall miss latency +system.cpu0.kern.inst.quiesce 83016 # number of quiesce instructions executed +system.cpu0.icache.replacements 856082 # number of replacements +system.cpu0.icache.tagsinuse 510.977353 # Cycle average of tags in use +system.cpu0.icache.total_refs 60644038 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 856594 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 70.796711 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 18804733000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 354.105005 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 156.872348 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.691611 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.306391 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998003 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 30350365 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30293673 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60644038 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30350365 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30293673 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60644038 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30350365 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30293673 # number of overall hits +system.cpu0.icache.overall_hits::total 60644038 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 416372 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 440222 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856594 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 416372 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 440222 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856594 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 416372 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 440222 # number of overall misses +system.cpu0.icache.overall_misses::total 856594 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5679878500 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027201 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025039 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024017 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.052674 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040614 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046045 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12145.021237 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.475746 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12162.627911 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29674.236004 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30197.305033 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29941.154052 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11924.025864 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11294.755877 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.962041 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100988882500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806861000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795743500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027677 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024605 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048841 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043685 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12267.246831 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12155.890582 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.672724 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29619.883276 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30551.209498 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30088.839578 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.315677 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11359.159780 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11620.061323 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -976,68 +976,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7651718 # DTB read hits -system.cpu1.dtb.read_misses 6996 # DTB read misses -system.cpu1.dtb.write_hits 5838563 # DTB write hits -system.cpu1.dtb.write_misses 1808 # DTB write misses -system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7490923 # DTB read hits +system.cpu1.dtb.read_misses 7080 # DTB read misses +system.cpu1.dtb.write_hits 5680189 # DTB write hits +system.cpu1.dtb.write_misses 1780 # DTB write misses +system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6464 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6451 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 130 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 216 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7658714 # DTB read accesses -system.cpu1.dtb.write_accesses 5840371 # DTB write accesses +system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7498003 # DTB read accesses +system.cpu1.dtb.write_accesses 5681969 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13490281 # DTB hits -system.cpu1.dtb.misses 8804 # DTB misses -system.cpu1.dtb.accesses 13499085 # DTB accesses -system.cpu1.itb.inst_hits 31421987 # ITB inst hits -system.cpu1.itb.inst_misses 3616 # ITB inst misses +system.cpu1.dtb.hits 13171112 # DTB hits +system.cpu1.dtb.misses 8860 # DTB misses +system.cpu1.dtb.accesses 13179972 # DTB accesses +system.cpu1.itb.inst_hits 30733895 # ITB inst hits +system.cpu1.itb.inst_misses 3661 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1275 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2808 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2756 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31425603 # ITB inst accesses -system.cpu1.itb.hits 31421987 # DTB hits -system.cpu1.itb.misses 3616 # DTB misses -system.cpu1.itb.accesses 31425603 # DTB accesses -system.cpu1.numCycles 2550975631 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30737556 # ITB inst accesses +system.cpu1.itb.hits 30733895 # DTB hits +system.cpu1.itb.misses 3661 # DTB misses +system.cpu1.itb.accesses 30737556 # DTB accesses +system.cpu1.numCycles 2664665536 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30761879 # Number of instructions committed -system.cpu1.committedOps 39296860 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35324832 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5961 # Number of float alu accesses -system.cpu1.num_func_calls 1142639 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4076383 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35324832 # number of integer instructions -system.cpu1.num_fp_insts 5961 # number of float instructions -system.cpu1.num_int_register_reads 202353181 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37998347 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4279 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1684 # number of times the floating registers were written -system.cpu1.num_mem_refs 14079956 # number of memory refs -system.cpu1.num_load_insts 7986446 # Number of load instructions -system.cpu1.num_store_insts 6093510 # Number of store instructions -system.cpu1.num_idle_cycles 3341647478.137703 # Number of idle cycles -system.cpu1.num_busy_cycles -790671847.137703 # Number of busy cycles -system.cpu1.not_idle_fraction -0.309949 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.309949 # Percentage of idle cycles +system.cpu1.committedInsts 30062453 # Number of instructions committed +system.cpu1.committedOps 38319221 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34454483 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses +system.cpu1.num_func_calls 1098871 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3931518 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34454483 # number of integer instructions +system.cpu1.num_fp_insts 4993 # number of float instructions +system.cpu1.num_int_register_reads 197476279 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37039984 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written +system.cpu1.num_mem_refs 13738954 # number of memory refs +system.cpu1.num_load_insts 7815473 # Number of load instructions +system.cpu1.num_store_insts 5923481 # Number of store instructions +system.cpu1.num_idle_cycles 1359992851.787481 # Number of idle cycles +system.cpu1.num_busy_cycles 1304672684.212520 # Number of busy cycles +system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.replacements 0 # number of replacements @@ -1054,10 +1054,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1128670778319 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1128670778319 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1196180344448 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1196180344448 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |