diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2533 |
1 files changed, 1266 insertions, 1267 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 0e907e72d..7ec12ef0d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144275 # Number of seconds simulated -sim_ticks 5144274809000 # Number of ticks simulated -final_tick 5144274809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.144266 # Number of seconds simulated +sim_ticks 5144266112000 # Number of ticks simulated +final_tick 5144266112000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169693 # Simulator instruction rate (inst/s) -host_op_rate 335427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145113000 # Simulator tick rate (ticks/s) -host_mem_usage 770200 # Number of bytes of host memory used -host_seconds 2398.14 # Real time elapsed on the host -sim_insts 406947274 # Number of instructions simulated -sim_ops 804399711 # Number of ops (including micro ops) simulated +host_inst_rate 171088 # Simulator instruction rate (inst/s) +host_op_rate 338186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2162643270 # Simulator tick rate (ticks/s) +host_mem_usage 817576 # Number of bytes of host memory used +host_seconds 2378.69 # Real time elapsed on the host +sim_insts 406967147 # Number of instructions simulated +sim_ops 804441344 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1034048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10709312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1037760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10694784 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11775872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1034048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1034048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9547776 # Number of bytes written to this memory -system.physmem.bytes_written::total 9547776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167333 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11765248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1037760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1037760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9531136 # Number of bytes written to this memory +system.physmem.bytes_written::total 9531136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167106 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183998 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149184 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149184 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2081792 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 183832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2078972 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2289122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1856000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1856000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1856000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2081792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2287061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852769 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852769 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2078972 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4145122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 183998 # Number of read requests accepted -system.physmem.writeReqs 149184 # Number of write requests accepted -system.physmem.readBursts 183998 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149184 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11761088 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14784 # Total number of bytes read from write queue -system.physmem.bytesWritten 9546240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11775872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9547776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 231 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 4139829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 183832 # Number of read requests accepted +system.physmem.writeReqs 148924 # Number of write requests accepted +system.physmem.readBursts 183832 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148924 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11753920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11328 # Total number of bytes read from write queue +system.physmem.bytesWritten 9529408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11765248 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9531136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 177 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 58239 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11315 # Per bank write bursts -system.physmem.perBankRdBursts::1 10581 # Per bank write bursts -system.physmem.perBankRdBursts::2 12129 # Per bank write bursts -system.physmem.perBankRdBursts::3 11752 # Per bank write bursts -system.physmem.perBankRdBursts::4 11319 # Per bank write bursts -system.physmem.perBankRdBursts::5 10663 # Per bank write bursts -system.physmem.perBankRdBursts::6 10930 # Per bank write bursts -system.physmem.perBankRdBursts::7 11239 # Per bank write bursts -system.physmem.perBankRdBursts::8 10920 # Per bank write bursts -system.physmem.perBankRdBursts::9 11403 # Per bank write bursts -system.physmem.perBankRdBursts::10 11471 # Per bank write bursts -system.physmem.perBankRdBursts::11 11421 # Per bank write bursts -system.physmem.perBankRdBursts::12 12415 # Per bank write bursts -system.physmem.perBankRdBursts::13 12512 # Per bank write bursts -system.physmem.perBankRdBursts::14 11823 # Per bank write bursts -system.physmem.perBankRdBursts::15 11874 # Per bank write bursts -system.physmem.perBankWrBursts::0 9756 # Per bank write bursts -system.physmem.perBankWrBursts::1 9158 # Per bank write bursts -system.physmem.perBankWrBursts::2 9767 # Per bank write bursts -system.physmem.perBankWrBursts::3 9469 # Per bank write bursts -system.physmem.perBankWrBursts::4 9300 # Per bank write bursts -system.physmem.perBankWrBursts::5 9148 # Per bank write bursts -system.physmem.perBankWrBursts::6 8815 # Per bank write bursts -system.physmem.perBankWrBursts::7 8963 # Per bank write bursts -system.physmem.perBankWrBursts::8 8876 # Per bank write bursts -system.physmem.perBankWrBursts::9 9249 # Per bank write bursts -system.physmem.perBankWrBursts::10 9141 # Per bank write bursts -system.physmem.perBankWrBursts::11 9048 # Per bank write bursts -system.physmem.perBankWrBursts::12 9841 # Per bank write bursts -system.physmem.perBankWrBursts::13 9699 # Per bank write bursts -system.physmem.perBankWrBursts::14 9635 # Per bank write bursts -system.physmem.perBankWrBursts::15 9295 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11604 # Per bank write bursts +system.physmem.perBankRdBursts::1 10712 # Per bank write bursts +system.physmem.perBankRdBursts::2 11807 # Per bank write bursts +system.physmem.perBankRdBursts::3 11944 # Per bank write bursts +system.physmem.perBankRdBursts::4 11505 # Per bank write bursts +system.physmem.perBankRdBursts::5 10649 # Per bank write bursts +system.physmem.perBankRdBursts::6 11472 # Per bank write bursts +system.physmem.perBankRdBursts::7 11273 # Per bank write bursts +system.physmem.perBankRdBursts::8 10779 # Per bank write bursts +system.physmem.perBankRdBursts::9 10837 # Per bank write bursts +system.physmem.perBankRdBursts::10 10616 # Per bank write bursts +system.physmem.perBankRdBursts::11 10970 # Per bank write bursts +system.physmem.perBankRdBursts::12 12334 # Per bank write bursts +system.physmem.perBankRdBursts::13 12596 # Per bank write bursts +system.physmem.perBankRdBursts::14 12433 # Per bank write bursts +system.physmem.perBankRdBursts::15 12124 # Per bank write bursts +system.physmem.perBankWrBursts::0 10095 # Per bank write bursts +system.physmem.perBankWrBursts::1 9143 # Per bank write bursts +system.physmem.perBankWrBursts::2 9309 # Per bank write bursts +system.physmem.perBankWrBursts::3 9560 # Per bank write bursts +system.physmem.perBankWrBursts::4 9320 # Per bank write bursts +system.physmem.perBankWrBursts::5 8650 # Per bank write bursts +system.physmem.perBankWrBursts::6 9309 # Per bank write bursts +system.physmem.perBankWrBursts::7 8633 # Per bank write bursts +system.physmem.perBankWrBursts::8 9264 # Per bank write bursts +system.physmem.perBankWrBursts::9 9181 # Per bank write bursts +system.physmem.perBankWrBursts::10 8947 # Per bank write bursts +system.physmem.perBankWrBursts::11 9087 # Per bank write bursts +system.physmem.perBankWrBursts::12 9676 # Per bank write bursts +system.physmem.perBankWrBursts::13 9763 # Per bank write bursts +system.physmem.perBankWrBursts::14 9717 # Per bank write bursts +system.physmem.perBankWrBursts::15 9243 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 5144274759500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 5144265940500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 183998 # Read request sizes (log2) +system.physmem.readPktSize::6 183832 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149184 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 169620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11412 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148924 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 169282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11661 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -156,300 +156,300 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 292.108413 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.353373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.792232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28114 38.54% 38.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17711 24.28% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7670 10.52% 73.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4213 5.78% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2951 4.05% 83.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2449 3.36% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1349 1.85% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1138 1.56% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7348 10.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72943 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.251615 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.083563 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7276 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 72695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 292.774799 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.092405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.788617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27722 38.13% 38.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17851 24.56% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7685 10.57% 73.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4254 5.85% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2907 4.00% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2448 3.37% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1364 1.88% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1142 1.57% 89.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7322 10.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 72695 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.828551 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.649701 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7109 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7277 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7277 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.497458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.666266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.148532 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6223 85.52% 85.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 179 2.46% 87.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 37 0.51% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 181 2.49% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 17 0.23% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.08% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 102 1.40% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.07% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 29 0.40% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 31 0.43% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.12% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 222 3.05% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.08% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.55% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.23% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7277 # Writes before turning the bus around for reads -system.physmem.totQLat 2097648589 # Total ticks spent queuing -system.physmem.totMemAccLat 5543279839 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 918835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11414.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7110 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7110 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.941913 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.730767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.006357 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6192 87.09% 87.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 167 2.35% 89.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 37 0.52% 89.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 45 0.63% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 23 0.32% 90.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.30% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 97 1.36% 92.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.13% 92.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 166 2.33% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.25% 95.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.10% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.23% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 121 1.70% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 38 0.53% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 106 1.49% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.24% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.07% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7110 # Writes before turning the bus around for reads +system.physmem.totQLat 2119857534 # Total ticks spent queuing +system.physmem.totMemAccLat 5563388784 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 918275000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11542.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30164.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30292.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing -system.physmem.readRowHits 150147 # Number of row buffer hits during reads -system.physmem.writeRowHits 109836 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes -system.physmem.avgGap 15439833.96 # Average gap between requests -system.physmem.pageHitRate 78.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 269030160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 146792250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 701430600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 481956480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 132992885070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2969904214500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3440495289780 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.800889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4940616567724 # Time in different power states -system.physmem_0.memoryStateTime::REF 171778620000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing +system.physmem.readRowHits 149881 # Number of row buffer hits during reads +system.physmem.writeRowHits 109975 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes +system.physmem.avgGap 15459573.80 # Average gap between requests +system.physmem.pageHitRate 78.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 270058320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 147353250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 709527000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 479643120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 132965716590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2969918703000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3440488964880 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.801684 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4940650410974 # Time in different power states +system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31879461276 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31837441026 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 282418920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 154097625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 731944200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 484600320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 133085381535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2969823077250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3440560500570 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.813565 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4940481114488 # Time in different power states -system.physmem_1.memoryStateTime::REF 171778620000 # Time in different power states +system.physmem_1.actEnergy 279515880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 152513625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 722974200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 485209440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 132979028940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2969907025500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3440524231185 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.808539 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4940617535740 # Time in different power states +system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32014679262 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31863205510 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86341843 # Number of BP lookups -system.cpu.branchPred.condPredicted 86341843 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843606 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79482226 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77803537 # Number of BTB hits +system.cpu.branchPred.lookups 86364991 # Number of BP lookups +system.cpu.branchPred.condPredicted 86364991 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844127 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79785258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77812669 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.887969 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1532975 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 177711 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.527627 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1536742 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177773 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 465489033 # number of cpu cycles simulated +system.cpu.numCycles 465360105 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27349012 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426558725 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86341843 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79336512 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433328456 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1773234 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 140367 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 61411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 195746 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 62 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8924695 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 425342 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4681 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 461962620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.822369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.015343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27264808 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426684669 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86364991 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79349411 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433306610 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1772802 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 134530 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 64125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 192382 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 876 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8941256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 423617 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4382 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 461849793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.823288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.015889 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 297385469 64.37% 64.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2141918 0.46% 64.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72009169 15.59% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1542851 0.33% 80.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2093373 0.45% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2277762 0.49% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1468275 0.32% 82.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1844826 0.40% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81198977 17.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 297255411 64.36% 64.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2121995 0.46% 64.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72014573 15.59% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1541910 0.33% 80.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2093291 0.45% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2283864 0.49% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1472775 0.32% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1848688 0.40% 82.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81217286 17.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 461962620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185486 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.916367 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23051751 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 281963390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 147749616 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8311246 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 886617 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 834090099 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 886617 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26334343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 229948938 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14545958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152100341 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 38146423 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 830806639 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 454355 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12555277 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 214921 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22219847 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 992487524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1803840100 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1108929979 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 295 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 961885153 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30602369 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460175 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42648824 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17020536 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10013615 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1265948 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1065839 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825617137 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1152647 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820744592 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 214843 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22370068 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33775079 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 142908 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 461962620 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.776647 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400230 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 461849793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185587 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.916891 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22977374 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 281921600 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 147739670 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8324748 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 886401 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 834278152 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 886401 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 26267496 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 229970737 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14504506 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152095213 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 38125440 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 830978624 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 455578 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12565136 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 219239 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22179017 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 992691182 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1804301856 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1109183623 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 961933159 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30758021 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 459775 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 462810 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42714636 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17039027 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10018616 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1305141 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1111349 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825753425 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1154163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820868911 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 214819 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22466239 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33875924 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 142660 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 461849793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.777350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400586 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278779319 60.35% 60.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13677385 2.96% 63.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9694463 2.10% 65.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7479161 1.62% 67.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 73155086 15.84% 82.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4780135 1.03% 83.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72637826 15.72% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1181137 0.26% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578108 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278664222 60.34% 60.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13660041 2.96% 63.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9686600 2.10% 65.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7488458 1.62% 67.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 73146885 15.84% 82.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4790867 1.04% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72643551 15.73% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1186237 0.26% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 582932 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 461962620 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 461849793 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2412123 76.39% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 586072 18.56% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159607 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2421761 76.44% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 586525 18.51% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160044 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 284241 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 792878234 96.60% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149840 0.02% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126459 0.02% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 284830 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 792980272 96.60% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149980 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126454 0.02% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 91 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued @@ -473,96 +473,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18033989 2.20% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9271738 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18050334 2.20% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9276952 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820744592 # Type of FU issued -system.cpu.iq.rate 1.763188 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3157802 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003847 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2106824012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 849151947 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816471101 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 436 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823617942 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 211 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1861954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820868911 # Type of FU issued +system.cpu.iq.rate 1.763943 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3168330 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2106970311 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 849385719 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 816582122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 452 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 530 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823752187 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 224 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1863434 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3065804 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14153 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1593948 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3081685 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14588 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13991 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1596193 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2095806 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68873 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2095838 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68033 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 886617 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 206103955 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15659492 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826769784 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 162986 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17020536 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10013615 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 683525 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 383471 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14451239 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 476576 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 982927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819239221 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17663851 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1381012 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 886401 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 206156511 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15627383 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826907588 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 167586 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17039027 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10018616 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 684984 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 384487 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14418162 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13991 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 476529 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 505758 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 982287 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819355250 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17680454 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1388114 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26724913 # number of memory reference insts executed -system.cpu.iew.exec_branches 82983667 # Number of branches executed -system.cpu.iew.exec_stores 9061062 # Number of stores executed -system.cpu.iew.exec_rate 1.759954 # Inst execution rate -system.cpu.iew.wb_sent 818769187 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816471257 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638649867 # num instructions producing a value -system.cpu.iew.wb_consumers 1046653125 # num instructions consuming a value -system.cpu.iew.wb_rate 1.754008 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610183 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 22245724 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1009739 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 854697 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 458607756 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.754004 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.647518 # Number of insts commited each cycle +system.cpu.iew.exec_refs 26746540 # number of memory reference insts executed +system.cpu.iew.exec_branches 82995794 # Number of branches executed +system.cpu.iew.exec_stores 9066086 # Number of stores executed +system.cpu.iew.exec_rate 1.760691 # Inst execution rate +system.cpu.iew.wb_sent 818880550 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 816582286 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638742122 # num instructions producing a value +system.cpu.iew.wb_consumers 1046798890 # num instructions consuming a value +system.cpu.iew.wb_rate 1.754732 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610186 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 22341740 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1011503 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 854574 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 458481638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.754577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.647842 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 288145143 62.83% 62.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11087272 2.42% 65.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3640468 0.79% 66.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74478879 16.24% 82.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2430107 0.53% 82.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1625402 0.35% 83.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1001040 0.22% 83.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70854372 15.45% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5345073 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 288021226 62.82% 62.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11081670 2.42% 65.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3642063 0.79% 66.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74473498 16.24% 82.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2428435 0.53% 82.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1625237 0.35% 83.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1003852 0.22% 83.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70853239 15.45% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5352418 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 458607756 # Number of insts commited each cycle -system.cpu.commit.committedInsts 406947274 # Number of instructions committed -system.cpu.commit.committedOps 804399711 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 458481638 # Number of insts commited each cycle +system.cpu.commit.committedInsts 406967147 # Number of instructions committed +system.cpu.commit.committedOps 804441344 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22374398 # Number of memory references committed -system.cpu.commit.loads 13954731 # Number of loads committed -system.cpu.commit.membars 448033 # Number of memory barriers committed -system.cpu.commit.branches 81999646 # Number of branches committed +system.cpu.commit.refs 22379764 # Number of memory references committed +system.cpu.commit.loads 13957341 # Number of loads committed +system.cpu.commit.membars 448127 # Number of memory barriers committed +system.cpu.commit.branches 82004213 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 733379682 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155571 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171831 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 781589650 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144528 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121874 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 733419549 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155856 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171897 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 781625831 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144579 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121842 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -589,231 +589,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13952145 1.73% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8419667 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13954756 1.73% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8422423 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 804399711 # Class of committed instruction -system.cpu.commit.bw_lim_events 5345073 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1279829790 # The number of ROB reads -system.cpu.rob.rob_writes 1656663443 # The number of ROB writes -system.cpu.timesIdled 287506 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3526413 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9823058000 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 406947274 # Number of Instructions Simulated -system.cpu.committedOps 804399711 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.143856 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.143856 # CPI: Total CPI of All Threads -system.cpu.ipc 0.874236 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.874236 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088022059 # number of integer regfile reads -system.cpu.int_regfile_writes 653481018 # number of integer regfile writes -system.cpu.fp_regfile_reads 156 # number of floating regfile reads -system.cpu.cc_regfile_reads 414844045 # number of cc regfile reads -system.cpu.cc_regfile_writes 320950754 # number of cc regfile writes -system.cpu.misc_regfile_reads 264261421 # number of misc regfile reads -system.cpu.misc_regfile_writes 400173 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1656014 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995636 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18946459 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656526 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.437466 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 804441344 # Class of committed instruction +system.cpu.commit.bw_lim_events 5352418 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1279833930 # The number of ROB reads +system.cpu.rob.rob_writes 1656952294 # The number of ROB writes +system.cpu.timesIdled 286358 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3510312 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9823169535 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 406967147 # Number of Instructions Simulated +system.cpu.committedOps 804441344 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.143483 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.143483 # CPI: Total CPI of All Threads +system.cpu.ipc 0.874521 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.874521 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088188706 # number of integer regfile reads +system.cpu.int_regfile_writes 653573677 # number of integer regfile writes +system.cpu.fp_regfile_reads 164 # number of floating regfile reads +system.cpu.cc_regfile_reads 414911991 # number of cc regfile reads +system.cpu.cc_regfile_writes 320992687 # number of cc regfile writes +system.cpu.misc_regfile_reads 264310319 # number of misc regfile reads +system.cpu.misc_regfile_writes 400396 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1655678 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993569 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18965333 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1656190 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.451182 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995636 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993569 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87599396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87599396 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10805755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10805755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8075007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8075007 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62855 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62855 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 18880762 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18880762 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18943617 # number of overall hits -system.cpu.dcache.overall_hits::total 18943617 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1800696 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1800696 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334991 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334991 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406405 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406405 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2135687 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2135687 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2542092 # number of overall misses -system.cpu.dcache.overall_misses::total 2542092 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30137867500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30137867500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21089945740 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21089945740 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51227813240 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51227813240 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51227813240 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51227813240 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12606451 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12606451 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8409998 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8409998 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 469260 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 469260 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21016449 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21016449 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21485709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21485709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142839 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.142839 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039832 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039832 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.866055 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.866055 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101620 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101620 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118315 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118315 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16736.788164 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16736.788164 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62956.753286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62956.753286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23986.573519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23986.573519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20151.832916 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20151.832916 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 556428 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87673930 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87673930 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10821466 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10821466 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077929 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077929 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63073 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63073 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18899395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18899395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18962468 # number of overall hits +system.cpu.dcache.overall_hits::total 18962468 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1800836 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1800836 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334794 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334794 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406327 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406327 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2135630 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2135630 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2541957 # number of overall misses +system.cpu.dcache.overall_misses::total 2541957 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30075089000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30075089000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21061915731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21061915731 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51137004731 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51137004731 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51137004731 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51137004731 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12622302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12622302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8412723 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412723 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 469400 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 469400 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21035025 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21035025 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21504425 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21504425 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142671 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039796 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039796 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865631 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.865631 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101527 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101527 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118206 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118206 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16700.626265 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16700.626265 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62910.075243 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62910.075243 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23944.693009 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23944.693009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20117.179296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20117.179296 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 547266 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 52454 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52094 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.607923 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.505356 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558074 # number of writebacks -system.cpu.dcache.writebacks::total 1558074 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834885 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 834885 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44903 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44903 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 879788 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 879788 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 879788 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 879788 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965811 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 965811 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290088 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290088 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402915 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402915 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1255899 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1255899 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1658814 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1658814 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13899 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 13899 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587359 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 587359 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14288232000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14288232000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19138141242 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19138141242 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6806565500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6806565500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33426373242 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33426373242 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40232938742 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40232938742 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98114325000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98114325000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2778681500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2778681500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100893006500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 100893006500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076612 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076612 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034493 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034493 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858618 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858618 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059758 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059758 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077205 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077205 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14794.024918 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14794.024918 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65973.570923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65973.570923 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16893.303799 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16893.303799 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26615.494751 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26615.494751 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24254.038573 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24254.038573 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.837269 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.837269 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199919.526585 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199919.526585 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171774.002782 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171774.002782 # average overall mshr uncacheable latency +system.cpu.dcache.writebacks::writebacks 1558302 # number of writebacks +system.cpu.dcache.writebacks::total 1558302 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835082 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 835082 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44918 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44918 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 880000 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 880000 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 880000 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 880000 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965754 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 965754 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289876 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289876 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402839 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402839 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1255630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1255630 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1658469 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1658469 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13931 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13931 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587407 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 587407 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14293741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14293741500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19116755234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19116755234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6811295000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6811295000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33410496734 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33410496734 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40221791734 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40221791734 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98116957000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98116957000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2783856500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2783856500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100900813500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100900813500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034457 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034457 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858200 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858200 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059692 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059692 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077122 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077122 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14800.602949 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14800.602949 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65948.044109 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65948.044109 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16908.231328 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.231328 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26608.552467 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26608.552467 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24252.362712 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24252.362712 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.653356 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.653356 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199831.778049 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199831.778049 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171773.256873 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171773.256873 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 76780 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.821773 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 101894 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 76796 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.326814 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 199830391500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821773 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988861 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988861 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 437119 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 437119 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 101894 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 101894 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 101894 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 101894 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 101894 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 101894 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77777 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 77777 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77777 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 77777 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77777 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 77777 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 965958500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 965958500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 965958500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 965958500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 965958500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 965958500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 179671 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 179671 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 179671 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 179671 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 179671 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 179671 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432886 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432886 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432886 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432886 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432886 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432886 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12419.590624 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12419.590624 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12419.590624 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12419.590624 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 70584 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.821836 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 110496 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70598 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.565143 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 199830439500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821836 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988865 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988865 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 435866 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 435866 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110530 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 110530 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110530 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 110530 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110530 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 110530 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71602 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71602 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71602 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71602 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71602 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71602 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914983500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914983500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914983500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 914983500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914983500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 914983500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182132 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 182132 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182132 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 182132 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182132 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 182132 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.393132 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.393132 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.393132 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.393132 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.393132 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.393132 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12778.742214 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12778.742214 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12778.742214 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12778.742214 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12778.742214 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12778.742214 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,182 +822,182 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 21553 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 21553 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77777 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77777 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77777 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 77777 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77777 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 77777 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 888181500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 888181500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 888181500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 888181500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 888181500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 888181500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.432886 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.432886 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.432886 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11419.590624 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20861 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20861 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71602 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71602 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71602 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71602 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71602 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71602 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 843381500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 843381500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 843381500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 843381500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 843381500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 843381500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.393132 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.393132 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.393132 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11778.742214 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11778.742214 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11778.742214 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 981325 # number of replacements -system.cpu.icache.tags.tagsinuse 508.752321 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7876209 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981837 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.021911 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 975620 # number of replacements +system.cpu.icache.tags.tagsinuse 509.114510 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7899697 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 976132 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.092857 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 150355632500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.752321 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.993657 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.993657 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 509.114510 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994364 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994364 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9906588 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9906588 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7876209 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7876209 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7876209 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7876209 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7876209 # number of overall hits -system.cpu.icache.overall_hits::total 7876209 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1048476 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1048476 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1048476 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1048476 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1048476 # number of overall misses -system.cpu.icache.overall_misses::total 1048476 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15750091989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15750091989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15750091989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15750091989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15750091989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15750091989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8924685 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8924685 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8924685 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8924685 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8924685 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8924685 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117480 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.117480 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.117480 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.117480 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.117480 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.117480 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15021.890810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15021.890810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15021.890810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15021.890810 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 14497 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 291 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9917449 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9917449 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7899697 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7899697 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7899697 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7899697 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7899697 # number of overall hits +system.cpu.icache.overall_hits::total 7899697 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1041547 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1041547 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1041547 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1041547 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1041547 # number of overall misses +system.cpu.icache.overall_misses::total 1041547 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15667212986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15667212986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15667212986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15667212986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15667212986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15667212986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8941244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8941244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8941244 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8941244 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8941244 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8941244 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116488 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116488 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116488 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116488 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116488 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116488 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15042.252521 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15042.252521 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15042.252521 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15042.252521 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15042.252521 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15042.252521 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12938 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 311 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 471 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.286869 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 72.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.469214 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 77.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 981325 # number of writebacks -system.cpu.icache.writebacks::total 981325 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66573 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66573 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66573 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66573 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66573 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66573 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981903 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981903 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981903 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981903 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981903 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13872010992 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13872010992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13872010992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13872010992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13872010992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13872010992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.110021 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.110021 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.110021 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14127.679610 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14127.679610 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 975620 # number of writebacks +system.cpu.icache.writebacks::total 975620 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65342 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65342 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65342 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65342 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65342 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65342 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 976205 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 976205 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 976205 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 976205 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 976205 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 976205 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13808957489 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13808957489 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13808957489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13808957489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13808957489 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13808957489 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109180 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109180 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109180 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14145.550872 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14145.550872 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14145.550872 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14145.550872 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14145.550872 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14145.550872 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13612 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.021123 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 25352 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13625 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.860697 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5116302133500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.021123 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376320 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376320 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 94236 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 94236 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25363 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25363 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 12936 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.024979 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 24186 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 12951 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.867501 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5115444997000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.024979 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376561 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376561 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 89804 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 89804 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24185 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 24185 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25365 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25365 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25365 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25365 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14502 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14502 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14502 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14502 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14502 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14502 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176957500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176957500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176957500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 176957500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176957500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 176957500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39865 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 39865 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24187 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 24187 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24187 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 24187 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 13810 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 13810 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 13810 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 13810 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 13810 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 13810 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 163118000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 163118000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 163118000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 163118000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 163118000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 163118000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37995 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 37995 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39867 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 39867 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39867 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 39867 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363778 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363778 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363760 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.363760 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363760 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.363760 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12202.282444 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12202.282444 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12202.282444 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12202.282444 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37997 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 37997 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37997 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 37997 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363450 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.363450 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363450 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.363450 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11811.585807 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11811.585807 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11811.585807 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11811.585807 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11811.585807 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11811.585807 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1006,187 +1006,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2767 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2767 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14502 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14502 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14502 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14502 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14502 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14502 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 162455500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 162455500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 162455500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 162455500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 162455500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 162455500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363778 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363778 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363760 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363760 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11202.282444 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2462 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2462 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 13810 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 13810 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 13810 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 13810 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 13810 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 13810 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149308000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 149308000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 149308000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 149308000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 149308000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 149308000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363450 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363450 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363450 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363450 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10811.585807 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10811.585807 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10811.585807 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112087 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64799.238973 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4898447 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176177 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.804123 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111812 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64798.412308 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4876376 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176112 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.689062 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50590.672109 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.620858 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139554 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3112.121923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11083.684529 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771952 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50635.420946 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.805219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143023 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3115.012545 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11033.030575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.772635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047487 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169124 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988758 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64090 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 706 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3231 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53982 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977936 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43579518 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43579518 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1582394 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1582394 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 980190 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 980190 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 342 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 342 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 155444 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 155444 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 965615 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 965615 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 66816 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12095 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332257 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1411168 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 66816 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12095 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 965615 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1487701 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2532227 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 66816 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12095 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 965615 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1487701 # number of overall hits -system.cpu.l2cache.overall_hits::total 2532227 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1438 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1438 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132521 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132521 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16160 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16160 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 60 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35761 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 35826 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 60 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16160 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 168282 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 184507 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 60 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16160 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 168282 # number of overall misses -system.cpu.l2cache.overall_misses::total 184507 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 57872000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 57872000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16936777500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16936777500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2166148500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2166148500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 8579000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 679000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4824922500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4834180500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 8579000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 679000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2166148500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21761700000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23937106500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 8579000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 679000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2166148500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21761700000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23937106500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1582394 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1582394 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 980190 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 980190 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1780 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1780 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287965 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287965 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 981775 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 981775 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 66876 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12100 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368018 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1446994 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 66876 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12100 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 981775 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1655983 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2716734 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 66876 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12100 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 981775 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1655983 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2716734 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807865 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807865 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460198 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.460198 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016460 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016460 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000897 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000413 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026141 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024759 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000897 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000413 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016460 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101621 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.067915 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000897 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000413 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016460 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101621 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.067915 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40244.784423 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40244.784423 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127804.480045 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127804.480045 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134043.842822 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134043.842822 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 142983.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135800 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134921.352870 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134934.977391 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 142983.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135800 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134043.842822 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129316.860983 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 129735.492420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 142983.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135800 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134043.842822 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129316.860983 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 129735.492420 # average overall miss latency +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047531 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.168351 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.988745 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 754 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3256 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6271 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53979 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.981140 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43447179 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43447179 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1581625 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1581625 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 974382 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 974382 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 155418 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 155418 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 959842 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 959842 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 64107 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 10951 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332187 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1407245 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 64107 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10951 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 959842 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1487605 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2522505 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 64107 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10951 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 959842 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1487605 # number of overall hits +system.cpu.l2cache.overall_hits::total 2522505 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1494 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1494 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 132350 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 132350 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16217 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16217 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 62 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 6 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35695 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 35763 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16217 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 168045 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 184330 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16217 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168045 # number of overall misses +system.cpu.l2cache.overall_misses::total 184330 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 55230000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 55230000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16916399500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16916399500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2173643500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2173643500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9044000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 812500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4836164500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4846021000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 812500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2173643500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 21752564000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23936064000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9044000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 812500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2173643500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 21752564000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23936064000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1581625 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1581625 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 974382 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 974382 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1814 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1814 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287768 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 976059 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 976059 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 64169 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 10957 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1367882 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1443008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64169 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10957 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 976059 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1655650 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2706835 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64169 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10957 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 976059 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1655650 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2706835 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823594 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823594 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459919 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.459919 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016615 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016615 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000966 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000548 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026095 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024784 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000966 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000548 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016615 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101498 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.068098 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000966 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000548 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016615 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101498 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.068098 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 36967.871486 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 36967.871486 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127815.636570 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127815.636570 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134034.870815 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134034.870815 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 145870.967742 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135416.666667 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135485.768315 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135503.760870 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 145870.967742 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135416.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134034.870815 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129444.874885 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 129854.413281 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 145870.967742 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135416.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134034.870815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129444.874885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 129854.413281 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1195,188 +1195,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102517 # number of writebacks -system.cpu.l2cache.writebacks::total 102517 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 102257 # number of writebacks +system.cpu.l2cache.writebacks::total 102257 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1438 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1438 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132521 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 132521 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16157 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16157 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 60 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35760 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35825 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 60 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 168281 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 184503 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 60 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16157 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 168281 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 184503 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13899 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13899 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587359 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587359 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102774999 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102774999 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15611567500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15611567500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2004346500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2004346500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 7979000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 629000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4468306500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4476914500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 7979000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 629000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2004346500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20079874000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22092828500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 7979000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 629000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2004346500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20079874000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22092828500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90946019500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90946019500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2618766000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2618766000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93564785500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93564785500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1494 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1494 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132350 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132350 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16215 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16215 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 62 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 6 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35694 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35762 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16215 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 184327 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16215 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168044 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 184327 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573476 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573476 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13931 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13931 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587407 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587407 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102660500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102660500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15592899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15592899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2011389507 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2011389507 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8424000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 752500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4479803007 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4488979507 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8424000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 752500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2011389507 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20072702507 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22093268514 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8424000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 752500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2011389507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20072702507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22093268514 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90948457000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90948457000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2623573000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2623573000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93572030000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93572030000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807865 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807865 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016457 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026140 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024758 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067914 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.067914 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71470.792072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71470.792072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117804.480045 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117804.480045 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124054.372718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124054.372718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125800 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124952.642617 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124966.210747 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.740488 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.740488 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188413.986618 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188413.986618 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159297.440747 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159297.440747 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823594 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823594 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016613 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026094 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024783 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101497 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068097 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101497 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068097 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68715.194110 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68715.194110 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117815.636570 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117815.636570 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124044.989639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124044.989639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125505.771474 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125523.726497 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124044.989639 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119449.087781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119859.101022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124044.989639 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119449.087781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119859.101022 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.566168 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.566168 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188326.250808 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188326.250808 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159296.756763 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159296.756763 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5460741 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2718937 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 72407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1221 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1221 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5434918 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2706203 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 65803 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3016607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1731587 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 980190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 117679 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 981903 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1461779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3003914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1730558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 975620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 168030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 976205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1454773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2943868 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146532 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31429 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 174582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9296411 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125565760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207412623 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 951488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5659456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 339589327 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 223808 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3529303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.165576 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2927884 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146809 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 37703 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 206355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9318751 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 124907456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207405643 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 858816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5441920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 338613835 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 220482 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3516168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.160049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3464951 98.18% 98.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 53009 1.50% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 11343 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3458199 98.35% 98.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 46816 1.33% 99.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 11153 0.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3529303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5594725985 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3516168 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5575385475 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 671790 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 661286 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474740212 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1466090916 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3066745270 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3066273273 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 21763478 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20730469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 116728873 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 107476352 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 212016 # Transaction distribution -system.iobus.trans_dist::ReadResp 212016 # Transaction distribution -system.iobus.trans_dist::WriteReq 57726 # Transaction distribution -system.iobus.trans_dist::WriteResp 57726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1645 # Transaction distribution -system.iobus.trans_dist::MessageResp 1645 # Transaction distribution +system.iobus.trans_dist::ReadReq 212032 # Transaction distribution +system.iobus.trans_dist::ReadResp 212032 # Transaction distribution +system.iobus.trans_dist::WriteReq 57756 # Transaction distribution +system.iobus.trans_dist::WriteResp 57756 # Transaction distribution +system.iobus.trans_dist::MessageReq 1647 # Transaction distribution +system.iobus.trans_dist::MessageResp 1647 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) @@ -1391,15 +1391,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 542774 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 542870 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) @@ -1414,37 +1414,37 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3262754 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3980596 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3262814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3982096 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10514500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10538500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1031500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1023500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 300003000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1175500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1174500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 24561500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 24563000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -1452,27 +1452,27 @@ system.iobus.reqLayer15.occupancy 10000 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 241121329 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 242078063 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1231500 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1233000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50160000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.116025 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.116006 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4999365177000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116025 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007252 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007252 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4999354367000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116006 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007250 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007250 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1486,14 +1486,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 904 system.iocache.demand_misses::total 904 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145501183 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 145501183 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6077027146 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6077027146 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 145501183 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 145501183 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 145501183 # number of overall miss cycles -system.iocache.overall_miss_latency::total 145501183 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149927198 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149927198 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867794865 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5867794865 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 149927198 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 149927198 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 149927198 # number of overall miss cycles +system.iocache.overall_miss_latency::total 149927198 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1510,19 +1510,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160952.636062 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 130073.355009 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130073.355009 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 160952.636062 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 160952.636062 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1232 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165848.670354 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125594.924336 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125594.924336 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 165848.670354 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 165848.670354 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 254 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 114 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.807018 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.043478 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1536,14 +1536,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 904 system.iocache.demand_mshr_misses::total 904 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 904 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 904 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100301183 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3741027146 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3741027146 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100301183 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100301183 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104727198 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3529874733 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3529874733 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 104727198 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 104727198 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1552,81 +1552,80 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110952.636062 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80073.355009 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80073.355009 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115848.670354 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75553.825621 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.825621 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 573460 # Transaction distribution -system.membus.trans_dist::ReadResp 626337 # Transaction distribution -system.membus.trans_dist::WriteReq 13899 # Transaction distribution -system.membus.trans_dist::WriteResp 13899 # Transaction distribution -system.membus.trans_dist::WritebackDirty 149184 # Transaction distribution -system.membus.trans_dist::CleanEvict 9829 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1709 # Transaction distribution -system.membus.trans_dist::ReadExReq 132252 # Transaction distribution -system.membus.trans_dist::ReadExResp 132250 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52886 # Transaction distribution -system.membus.trans_dist::MessageReq 1645 # Transaction distribution -system.membus.trans_dist::MessageResp 1645 # Transaction distribution -system.membus.trans_dist::BadAddressError 9 # Transaction distribution +system.membus.trans_dist::ReadReq 573476 # Transaction distribution +system.membus.trans_dist::ReadResp 626351 # Transaction distribution +system.membus.trans_dist::WriteReq 13931 # Transaction distribution +system.membus.trans_dist::WriteResp 13931 # Transaction distribution +system.membus.trans_dist::WritebackDirty 148924 # Transaction distribution +system.membus.trans_dist::CleanEvict 10358 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2192 # Transaction distribution +system.membus.trans_dist::UpgradeResp 19 # Transaction distribution +system.membus.trans_dist::ReadExReq 132088 # Transaction distribution +system.membus.trans_dist::ReadExResp 132085 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52881 # Transaction distribution +system.membus.trans_dist::MessageReq 1647 # Transaction distribution +system.membus.trans_dist::MessageResp 1647 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 483648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1803484 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460961 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18308608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19997967 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730486 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 481353 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1656179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1755109 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460969 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18281344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19970763 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23019587 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1629 # Total snoops (count) -system.membus.snoop_fanout::samples 982619 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001674 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040881 # Request fanout histogram +system.membus.pkt_size::total 22992391 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1583 # Total snoops (count) +system.membus.snoop_fanout::samples 982226 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001677 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040914 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 980974 99.83% 99.83% # Request fanout histogram -system.membus.snoop_fanout::2 1645 0.17% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 980579 99.83% 99.83% # Request fanout histogram +system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 982619 # Request fanout histogram -system.membus.reqLayer0.occupancy 339006500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 982226 # Request fanout histogram +system.membus.reqLayer0.occupancy 339026000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 369115500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 369109500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3980404 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3981904 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1013900787 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1012407982 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 12000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 2335404 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2334904 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2139201818 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2135091502 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85763851 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 4662400 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. |