diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2681 |
1 files changed, 1345 insertions, 1336 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 7ec12ef0d..b4b530730 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144266 # Number of seconds simulated -sim_ticks 5144266112000 # Number of ticks simulated -final_tick 5144266112000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.230834 # Number of seconds simulated +sim_ticks 5230834315000 # Number of ticks simulated +final_tick 5230834315000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171088 # Simulator instruction rate (inst/s) -host_op_rate 338186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2162643270 # Simulator tick rate (ticks/s) -host_mem_usage 817576 # Number of bytes of host memory used -host_seconds 2378.69 # Real time elapsed on the host -sim_insts 406967147 # Number of instructions simulated -sim_ops 804441344 # Number of ops (including micro ops) simulated +host_inst_rate 192642 # Simulator instruction rate (inst/s) +host_op_rate 380808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2470040631 # Simulator tick rate (ticks/s) +host_mem_usage 757076 # Number of bytes of host memory used +host_seconds 2117.71 # Real time elapsed on the host +sim_insts 407959263 # Number of instructions simulated +sim_ops 806441023 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1037760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10694784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1022720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10555840 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11765248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1037760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1037760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9531136 # Number of bytes written to this memory -system.physmem.bytes_written::total 9531136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167106 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11615232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1022720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1022720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9293760 # Number of bytes written to this memory +system.physmem.bytes_written::total 9293760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164935 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183832 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2078972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2287061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201731 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201731 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852769 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1852769 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2078972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4139829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 183832 # Number of read requests accepted -system.physmem.writeReqs 148924 # Number of write requests accepted -system.physmem.readBursts 183832 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148924 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11753920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11328 # Total number of bytes read from write queue -system.physmem.bytesWritten 9529408 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11765248 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9531136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 177 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 181488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145215 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145215 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 1505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 86 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 195518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2018003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2220531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 195518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 195518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1776726 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1776726 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1776726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 86 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 195518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2018003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3997258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 181488 # Number of read requests accepted +system.physmem.writeReqs 145215 # Number of write requests accepted +system.physmem.readBursts 181488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145215 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11596608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue +system.physmem.bytesWritten 9292096 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11615232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9293760 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11604 # Per bank write bursts -system.physmem.perBankRdBursts::1 10712 # Per bank write bursts -system.physmem.perBankRdBursts::2 11807 # Per bank write bursts -system.physmem.perBankRdBursts::3 11944 # Per bank write bursts -system.physmem.perBankRdBursts::4 11505 # Per bank write bursts -system.physmem.perBankRdBursts::5 10649 # Per bank write bursts -system.physmem.perBankRdBursts::6 11472 # Per bank write bursts -system.physmem.perBankRdBursts::7 11273 # Per bank write bursts -system.physmem.perBankRdBursts::8 10779 # Per bank write bursts -system.physmem.perBankRdBursts::9 10837 # Per bank write bursts -system.physmem.perBankRdBursts::10 10616 # Per bank write bursts -system.physmem.perBankRdBursts::11 10970 # Per bank write bursts -system.physmem.perBankRdBursts::12 12334 # Per bank write bursts -system.physmem.perBankRdBursts::13 12596 # Per bank write bursts -system.physmem.perBankRdBursts::14 12433 # Per bank write bursts -system.physmem.perBankRdBursts::15 12124 # Per bank write bursts -system.physmem.perBankWrBursts::0 10095 # Per bank write bursts -system.physmem.perBankWrBursts::1 9143 # Per bank write bursts -system.physmem.perBankWrBursts::2 9309 # Per bank write bursts -system.physmem.perBankWrBursts::3 9560 # Per bank write bursts -system.physmem.perBankWrBursts::4 9320 # Per bank write bursts -system.physmem.perBankWrBursts::5 8650 # Per bank write bursts -system.physmem.perBankWrBursts::6 9309 # Per bank write bursts -system.physmem.perBankWrBursts::7 8633 # Per bank write bursts -system.physmem.perBankWrBursts::8 9264 # Per bank write bursts -system.physmem.perBankWrBursts::9 9181 # Per bank write bursts -system.physmem.perBankWrBursts::10 8947 # Per bank write bursts -system.physmem.perBankWrBursts::11 9087 # Per bank write bursts -system.physmem.perBankWrBursts::12 9676 # Per bank write bursts -system.physmem.perBankWrBursts::13 9763 # Per bank write bursts -system.physmem.perBankWrBursts::14 9717 # Per bank write bursts -system.physmem.perBankWrBursts::15 9243 # Per bank write bursts +system.physmem.perBankRdBursts::0 11156 # Per bank write bursts +system.physmem.perBankRdBursts::1 11363 # Per bank write bursts +system.physmem.perBankRdBursts::2 11879 # Per bank write bursts +system.physmem.perBankRdBursts::3 11399 # Per bank write bursts +system.physmem.perBankRdBursts::4 11231 # Per bank write bursts +system.physmem.perBankRdBursts::5 10765 # Per bank write bursts +system.physmem.perBankRdBursts::6 10426 # Per bank write bursts +system.physmem.perBankRdBursts::7 10967 # Per bank write bursts +system.physmem.perBankRdBursts::8 10953 # Per bank write bursts +system.physmem.perBankRdBursts::9 10767 # Per bank write bursts +system.physmem.perBankRdBursts::10 11374 # Per bank write bursts +system.physmem.perBankRdBursts::11 11178 # Per bank write bursts +system.physmem.perBankRdBursts::12 12058 # Per bank write bursts +system.physmem.perBankRdBursts::13 12613 # Per bank write bursts +system.physmem.perBankRdBursts::14 11821 # Per bank write bursts +system.physmem.perBankRdBursts::15 11247 # Per bank write bursts +system.physmem.perBankWrBursts::0 9305 # Per bank write bursts +system.physmem.perBankWrBursts::1 9167 # Per bank write bursts +system.physmem.perBankWrBursts::2 9550 # Per bank write bursts +system.physmem.perBankWrBursts::3 8690 # Per bank write bursts +system.physmem.perBankWrBursts::4 9047 # Per bank write bursts +system.physmem.perBankWrBursts::5 8729 # Per bank write bursts +system.physmem.perBankWrBursts::6 8333 # Per bank write bursts +system.physmem.perBankWrBursts::7 8814 # Per bank write bursts +system.physmem.perBankWrBursts::8 9019 # Per bank write bursts +system.physmem.perBankWrBursts::9 9026 # Per bank write bursts +system.physmem.perBankWrBursts::10 9076 # Per bank write bursts +system.physmem.perBankWrBursts::11 9210 # Per bank write bursts +system.physmem.perBankWrBursts::12 9034 # Per bank write bursts +system.physmem.perBankWrBursts::13 9699 # Per bank write bursts +system.physmem.perBankWrBursts::14 9456 # Per bank write bursts +system.physmem.perBankWrBursts::15 9034 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 5144265940500 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 5230834265500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 183832 # Read request sizes (log2) +system.physmem.readPktSize::6 181488 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148924 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 169282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.writePktSize::6 145215 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 166675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,664 +156,671 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 292.774799 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.092405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.788617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27722 38.13% 38.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17851 24.56% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7685 10.57% 73.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4254 5.85% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2907 4.00% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2448 3.37% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1364 1.88% 88.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1142 1.57% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7322 10.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72695 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.828551 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.649701 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7109 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 71822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.839019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.771532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 314.503983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28254 39.34% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17135 23.86% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7363 10.25% 73.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4141 5.77% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2915 4.06% 83.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2283 3.18% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1315 1.83% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1115 1.55% 89.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7301 10.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71822 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6865 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.391843 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 580.532608 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6864 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7110 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7110 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.941913 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.730767 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.006357 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6192 87.09% 87.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 167 2.35% 89.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 37 0.52% 89.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 45 0.63% 90.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 23 0.32% 90.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.30% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 97 1.36% 92.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.13% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 166 2.33% 95.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.25% 95.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.10% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.23% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 121 1.70% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.11% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 38 0.53% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 106 1.49% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.24% 99.79% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6865 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.149162 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.881845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.152110 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5944 86.58% 86.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 183 2.67% 89.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.45% 89.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.64% 90.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 19 0.28% 90.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.25% 90.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 108 1.57% 92.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.09% 92.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 159 2.32% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.17% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.15% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 18 0.26% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 123 1.79% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 32 0.47% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 120 1.75% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.19% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.07% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7110 # Writes before turning the bus around for reads -system.physmem.totQLat 2119857534 # Total ticks spent queuing -system.physmem.totMemAccLat 5563388784 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 918275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11542.61 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6865 # Writes before turning the bus around for reads +system.physmem.totQLat 2046328821 # Total ticks spent queuing +system.physmem.totMemAccLat 5443772571 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 905985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11293.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30292.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30043.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing -system.physmem.readRowHits 149881 # Number of row buffer hits during reads -system.physmem.writeRowHits 109975 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.32 # Average write queue length when enqueuing +system.physmem.readRowHits 147319 # Number of row buffer hits during reads +system.physmem.writeRowHits 107244 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes -system.physmem.avgGap 15459573.80 # Average gap between requests -system.physmem.pageHitRate 78.13 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 270058320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 147353250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 709527000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 479643120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 132965716590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2969918703000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3440488964880 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.801684 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4940650410974 # Time in different power states -system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states +system.physmem.avgGap 16010977.14 # Average gap between requests +system.physmem.pageHitRate 77.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 266013720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 145146375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 695643000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 464194800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 136227969945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3019002265500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3498453875580 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.813765 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 5022288614990 # Time in different power states +system.physmem_0.memoryStateTime::REF 174669040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31837441026 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33876500010 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 279515880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 152513625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 722974200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 485209440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 132979028940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2969907025500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3440524231185 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.808539 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4940617535740 # Time in different power states -system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states +system.physmem_1.actEnergy 276960600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 151119375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 717685800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 476629920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 341652642240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 136555945380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3018714567750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3498545551065 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.831291 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 5021804288475 # Time in different power states +system.physmem_1.memoryStateTime::REF 174669040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31863205510 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34360826525 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86364991 # Number of BP lookups -system.cpu.branchPred.condPredicted 86364991 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 844127 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79785258 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77812669 # Number of BTB hits +system.cpu.branchPred.lookups 94759510 # Number of BP lookups +system.cpu.branchPred.condPredicted 94759510 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2569243 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 91334471 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.527627 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1536742 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 177773 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 2549727 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 537871 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 91334471 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 76457686 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14876785 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1743030 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 465360105 # number of cpu cycles simulated +system.cpu.numCycles 480891878 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27264808 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426684669 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86364991 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79349411 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433306610 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1772802 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 134530 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 64125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 192382 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 876 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8941256 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 423617 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4382 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 461849793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.823288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.015889 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31923465 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 465887359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94759510 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79007413 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 440671990 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5255038 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 191860 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 57153 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 353002 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 55 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 773 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12757750 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1092264 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5767 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 475825817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.921076 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.087709 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 297255411 64.36% 64.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2121995 0.46% 64.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72014573 15.59% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1541910 0.33% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2093291 0.45% 81.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2283864 0.49% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1472775 0.32% 82.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1848688 0.40% 82.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81217286 17.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 301327473 63.33% 63.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2357212 0.50% 63.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72486885 15.23% 79.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1661724 0.35% 79.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2316398 0.49% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2498634 0.53% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1681394 0.35% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2034597 0.43% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 89461500 18.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 461849793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185587 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.916891 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22977374 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 281921600 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 147739670 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8324748 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 886401 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 834278152 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 886401 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26267496 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 229970737 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14504506 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152095213 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 38125440 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 830978624 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 455578 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12565136 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 219239 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22179017 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 992691182 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1804301856 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1109183623 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 961933159 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30758021 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 459775 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 462810 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42714636 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17039027 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10018616 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1305141 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1111349 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825753425 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1154163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820868911 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 214819 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22466239 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33875924 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 142660 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 461849793 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.777350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400586 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 475825817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197050 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.968799 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27555997 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 279962496 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 157784659 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7895146 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2627519 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 893342997 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 2627519 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31132089 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 232770175 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13972853 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 161343580 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33979601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 881934442 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 459863 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11536689 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 128312 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19728876 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1046728889 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1924876453 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1183291014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 238 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964344248 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 82384633 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 601367 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 610252 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38099382 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 22094008 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12941388 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1476239 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1186105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 863334374 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1274378 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 846301447 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1080231 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 58167725 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 86490196 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 262880 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 475825817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.778595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.407570 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278664222 60.34% 60.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13660041 2.96% 63.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9686600 2.10% 65.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7488458 1.62% 67.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 73146885 15.84% 82.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4790867 1.04% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72643551 15.73% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1186237 0.26% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 582932 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 287398661 60.40% 60.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14176451 2.98% 63.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10047775 2.11% 65.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7166598 1.51% 67.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75162617 15.80% 82.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5098284 1.07% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 73991117 15.55% 99.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1833450 0.39% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 950864 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 461849793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 475825817 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2421761 76.44% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 586525 18.51% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160044 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2341238 73.82% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 650739 20.52% 94.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 179640 5.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 284830 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 792980272 96.60% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149980 0.02% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126454 0.02% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18050334 2.20% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9276952 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 356316 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 813370459 96.11% 96.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 158919 0.02% 96.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125217 0.01% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 33 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 21536842 2.54% 98.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 10753661 1.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820868911 # Type of FU issued -system.cpu.iq.rate 1.763943 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3168330 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003860 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2106970311 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 849385719 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816582122 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 452 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 530 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823752187 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 224 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1863434 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 846301447 # Type of FU issued +system.cpu.iq.rate 1.759858 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3171617 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003748 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2172680182 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 922790965 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 836180835 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 370 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 849116572 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 176 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1830080 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3081685 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14588 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13991 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1596193 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8142730 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39108 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18452 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4524667 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2095838 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68033 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2096489 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 69686 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 886401 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 206156511 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15627383 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826907588 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 167586 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17039027 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10018616 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 684984 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 384487 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14418162 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13991 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 476529 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 505758 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 982287 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819355250 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17680454 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1388114 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2627519 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 209544850 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15006849 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 864608752 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 226211 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 22094027 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12941388 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 792823 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 380512 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13811616 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18452 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 814414 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2555334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3369748 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 840380811 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 20115901 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5466441 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26746540 # number of memory reference insts executed -system.cpu.iew.exec_branches 82995794 # Number of branches executed -system.cpu.iew.exec_stores 9066086 # Number of stores executed -system.cpu.iew.exec_rate 1.760691 # Inst execution rate -system.cpu.iew.wb_sent 818880550 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816582286 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638742122 # num instructions producing a value -system.cpu.iew.wb_consumers 1046798890 # num instructions consuming a value -system.cpu.iew.wb_rate 1.754732 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610186 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 22341740 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1011503 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 854574 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 458481638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.754577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.647842 # Number of insts commited each cycle +system.cpu.iew.exec_refs 30041341 # number of memory reference insts executed +system.cpu.iew.exec_branches 84810471 # Number of branches executed +system.cpu.iew.exec_stores 9925440 # Number of stores executed +system.cpu.iew.exec_rate 1.747546 # Inst execution rate +system.cpu.iew.wb_sent 839049436 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 836180959 # cumulative count of insts written-back +system.cpu.iew.wb_producers 651539387 # num instructions producing a value +system.cpu.iew.wb_consumers 1065055120 # num instructions consuming a value +system.cpu.iew.wb_rate 1.738813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611742 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 58084156 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1011498 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2594633 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 466580325 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.728408 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.632712 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 288021226 62.82% 62.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11081670 2.42% 65.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3642063 0.79% 66.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74473498 16.24% 82.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2428435 0.53% 82.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1625237 0.35% 83.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1003852 0.22% 83.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70853239 15.45% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5352418 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 295124018 63.25% 63.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11517659 2.47% 65.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3731538 0.80% 66.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74584029 15.99% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2769867 0.59% 83.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1676646 0.36% 83.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1039317 0.22% 83.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71088407 15.24% 98.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5048844 1.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 458481638 # Number of insts commited each cycle -system.cpu.commit.committedInsts 406967147 # Number of instructions committed -system.cpu.commit.committedOps 804441344 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 466580325 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407959263 # Number of instructions committed +system.cpu.commit.committedOps 806441023 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22379764 # Number of memory references committed -system.cpu.commit.loads 13957341 # Number of loads committed -system.cpu.commit.membars 448127 # Number of memory barriers committed -system.cpu.commit.branches 82004213 # Number of branches committed +system.cpu.commit.refs 22368017 # Number of memory references committed +system.cpu.commit.loads 13951296 # Number of loads committed +system.cpu.commit.membars 447981 # Number of memory barriers committed +system.cpu.commit.branches 82209281 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 733419549 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155856 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171897 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 781625831 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144579 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121842 0.02% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13954756 1.73% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8422423 1.05% 100.00% # Class of committed instruction +system.cpu.commit.int_insts 735219945 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155854 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 172239 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783638607 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 143690 0.02% 97.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121021 0.02% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.23% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13948729 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8416721 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 804441344 # Class of committed instruction -system.cpu.commit.bw_lim_events 5352418 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1279833930 # The number of ROB reads -system.cpu.rob.rob_writes 1656952294 # The number of ROB writes -system.cpu.timesIdled 286358 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3510312 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9823169535 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 406967147 # Number of Instructions Simulated -system.cpu.committedOps 804441344 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.143483 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.143483 # CPI: Total CPI of All Threads -system.cpu.ipc 0.874521 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.874521 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088188706 # number of integer regfile reads -system.cpu.int_regfile_writes 653573677 # number of integer regfile writes -system.cpu.fp_regfile_reads 164 # number of floating regfile reads -system.cpu.cc_regfile_reads 414911991 # number of cc regfile reads -system.cpu.cc_regfile_writes 320992687 # number of cc regfile writes -system.cpu.misc_regfile_reads 264310319 # number of misc regfile reads -system.cpu.misc_regfile_writes 400396 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1655678 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993569 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18965333 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656190 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.451182 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993569 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 806441023 # Class of committed instruction +system.cpu.commit.bw_lim_events 5048844 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1325977641 # The number of ROB reads +system.cpu.rob.rob_writes 1738470998 # The number of ROB writes +system.cpu.timesIdled 409236 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5066061 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9980774176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407959263 # Number of Instructions Simulated +system.cpu.committedOps 806441023 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.178774 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178774 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848339 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848339 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1112363546 # number of integer regfile reads +system.cpu.int_regfile_writes 669949193 # number of integer regfile writes +system.cpu.fp_regfile_reads 124 # number of floating regfile reads +system.cpu.cc_regfile_reads 420347609 # number of cc regfile reads +system.cpu.cc_regfile_writes 325273387 # number of cc regfile writes +system.cpu.misc_regfile_reads 273375214 # number of misc regfile reads +system.cpu.misc_regfile_writes 400822 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1703381 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994824 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21315243 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1703893 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.509731 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 65900500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994824 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87673930 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87673930 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10821466 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10821466 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077929 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077929 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63073 # 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number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2541957 # number of overall misses -system.cpu.dcache.overall_misses::total 2541957 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30075089000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30075089000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21061915731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21061915731 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51137004731 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51137004731 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51137004731 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51137004731 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12622302 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12622302 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8412723 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8412723 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 469400 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 469400 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21035025 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21035025 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21504425 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21504425 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.142671 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039796 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039796 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865631 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.865631 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101527 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101527 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118206 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16700.626265 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16700.626265 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62910.075243 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62910.075243 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23944.693009 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23944.693009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20117.179296 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20117.179296 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 547266 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 52094 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.505356 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 97435588 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97435588 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13163533 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13163533 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077773 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077773 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 71009 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 71009 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 21241306 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21241306 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21312315 # number of overall hits +system.cpu.dcache.overall_hits::total 21312315 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1883327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1883327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 329239 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 329239 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 408040 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 408040 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2212566 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2212566 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2620606 # number of overall misses +system.cpu.dcache.overall_misses::total 2620606 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31677233500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31677233500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20451778744 # 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number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23453872 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23453872 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23932921 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23932921 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125164 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.125164 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039162 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039162 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.851771 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.851771 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.094337 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.094337 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109498 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109498 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16819.826562 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16819.826562 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62118.335750 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62118.335750 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23560.432658 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23560.432658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19891.968592 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19891.968592 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 529664 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 193 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52278 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.131681 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558302 # number of writebacks -system.cpu.dcache.writebacks::total 1558302 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835082 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 835082 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44918 # 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number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6811295000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33410496734 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33410496734 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40221791734 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40221791734 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98116957000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98116957000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2783856500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2783856500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100900813500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 100900813500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076512 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076512 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034457 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034457 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858200 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858200 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059692 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059692 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077122 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077122 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14800.602949 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14800.602949 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65948.044109 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65948.044109 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16908.231328 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.231328 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26608.552467 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26608.552467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24252.362712 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24252.362712 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.653356 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.653356 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199831.778049 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199831.778049 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171773.256873 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171773.256873 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13974 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13974 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587450 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 587450 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15261276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15261276000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18535708244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18535708244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6777922000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6777922000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33796984244 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33796984244 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40574906244 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40574906244 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98117221000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98117221000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2788550500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2788550500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100905771500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100905771500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.067459 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.067459 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034152 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034152 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.844571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.844571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055520 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055520 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071314 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.071314 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15035.147383 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15035.147383 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64557.581505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64557.581505 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16752.527861 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16752.527861 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25954.575627 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25954.575627 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23773.198327 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23773.198327 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171092.113707 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171092.113707 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199552.776585 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199552.776585 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171769.123330 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171769.123330 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 70584 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.821836 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 110496 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 70598 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.565143 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 199830439500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821836 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988865 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988865 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 148390 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.865349 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 319136 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 148405 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 2.150440 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 195927668000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.865349 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.991584 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.991584 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 435866 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 435866 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110530 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 110530 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110530 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 110530 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110530 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 110530 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71602 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 71602 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71602 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 71602 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71602 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 71602 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914983500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914983500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914983500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 914983500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914983500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 914983500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182132 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 182132 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182132 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 182132 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182132 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 182132 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.393132 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.393132 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.393132 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.393132 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.393132 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.393132 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12778.742214 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12778.742214 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12778.742214 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12778.742214 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12778.742214 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12778.742214 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 1086216 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 1086216 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 319137 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 319137 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 319137 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 319137 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 319137 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 319137 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 149314 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 149314 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 149314 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 149314 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 149314 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 149314 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1956836500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1956836500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1956836500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1956836500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1956836500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1956836500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 468451 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 468451 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 468451 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 468451 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 468451 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 468451 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.318740 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.318740 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.318740 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.318740 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.318740 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.318740 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13105.512544 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13105.512544 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13105.512544 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13105.512544 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13105.512544 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,182 +829,184 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 20861 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 20861 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71602 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71602 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71602 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 71602 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71602 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 71602 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 843381500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 843381500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 843381500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 843381500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 843381500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 843381500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.393132 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.393132 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.393132 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11778.742214 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11778.742214 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11778.742214 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35466 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35466 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 149314 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 149314 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 149314 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 149314 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 149314 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 149314 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1807522500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1807522500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1807522500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1807522500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.318740 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.318740 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.318740 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.318740 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12105.512544 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 12105.512544 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 12105.512544 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 975620 # number of replacements -system.cpu.icache.tags.tagsinuse 509.114510 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7899697 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 976132 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.092857 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 150355632500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.114510 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994364 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994364 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1273398 # number of replacements +system.cpu.icache.tags.tagsinuse 510.770567 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11313989 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1273910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.881310 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 150946764500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.770567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997599 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997599 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9917449 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9917449 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7899697 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7899697 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7899697 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7899697 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7899697 # number of overall hits -system.cpu.icache.overall_hits::total 7899697 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1041547 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1041547 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1041547 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1041547 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1041547 # number of overall misses -system.cpu.icache.overall_misses::total 1041547 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15667212986 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15667212986 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15667212986 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15667212986 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15667212986 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15667212986 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8941244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8941244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8941244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8941244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8941244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8941244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116488 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116488 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.116488 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.116488 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.116488 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.116488 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15042.252521 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15042.252521 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15042.252521 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15042.252521 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15042.252521 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15042.252521 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 12938 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 311 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 471 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.469214 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 77.750000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 14031709 # Number of tag accesses +system.cpu.icache.tags.data_accesses 14031709 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11313989 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11313989 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11313989 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11313989 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11313989 # number of overall hits +system.cpu.icache.overall_hits::total 11313989 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1443748 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1443748 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1443748 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1443748 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1443748 # number of overall misses +system.cpu.icache.overall_misses::total 1443748 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20254966986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20254966986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20254966986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20254966986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20254966986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20254966986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12757737 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12757737 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12757737 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12757737 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12757737 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12757737 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.113166 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.113166 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.113166 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.113166 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.113166 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.113166 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14029.433797 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14029.433797 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14029.433797 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14029.433797 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14029.433797 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 10512 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 700 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 591 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.786802 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 233.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 975620 # number of writebacks -system.cpu.icache.writebacks::total 975620 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65342 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65342 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65342 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65342 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65342 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65342 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 976205 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 976205 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 976205 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 976205 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 976205 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 976205 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13808957489 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13808957489 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13808957489 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13808957489 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13808957489 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13808957489 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109180 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109180 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109180 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14145.550872 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14145.550872 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14145.550872 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14145.550872 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14145.550872 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14145.550872 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1273398 # number of writebacks +system.cpu.icache.writebacks::total 1273398 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 169776 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 169776 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 169776 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 169776 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 169776 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 169776 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1273972 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1273972 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1273972 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1273972 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1273972 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1273972 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329222989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17329222989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329222989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17329222989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329222989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17329222989 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.099859 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.099859 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.099859 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.099859 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13602.514803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13602.514803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13602.514803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13602.514803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 12936 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.024979 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 24186 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 12951 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.867501 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5115444997000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.024979 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376561 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376561 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 89804 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 89804 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24185 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 24185 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 15042 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 8.049036 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 49432 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 15055 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 3.283427 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5151195295500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 8.049036 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.503065 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.503065 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 146624 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 146624 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 49439 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 49439 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24187 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 24187 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24187 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 24187 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 13810 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 13810 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 13810 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 13810 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 13810 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 13810 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 163118000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 163118000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 163118000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 163118000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 163118000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 163118000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37995 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 37995 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 49441 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 49441 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 49441 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 49441 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15914 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15914 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15914 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15914 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15914 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15914 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 193233000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 193233000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 193233000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 193233000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 193233000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 193233000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 65353 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 65353 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37997 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 37997 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37997 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 37997 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363469 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363469 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363450 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.363450 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363450 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.363450 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11811.585807 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11811.585807 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11811.585807 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11811.585807 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11811.585807 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11811.585807 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 65355 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 65355 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 65355 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 65355 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.243508 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.243508 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.243501 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.243501 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.243501 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.243501 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12142.327510 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12142.327510 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12142.327510 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12142.327510 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12142.327510 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1006,187 +1015,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2462 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2462 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 13810 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 13810 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 13810 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 13810 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 13810 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 13810 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149308000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 149308000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 149308000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 149308000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 149308000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 149308000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363469 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363469 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363450 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363450 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363450 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363450 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10811.585807 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10811.585807 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10811.585807 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3121 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3121 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15914 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15914 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15914 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 15914 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15914 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 15914 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 177319000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 177319000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 177319000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 177319000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 177319000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 177319000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.243508 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.243508 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.243501 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.243501 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.243501 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11142.327510 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11142.327510 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11142.327510 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111812 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64798.412308 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4876376 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176112 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.689062 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 108236 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64755.938748 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5712490 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 172394 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 33.136246 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50635.420946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.805219 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143023 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3115.012545 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11033.030575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.772635 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000226 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.168351 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988745 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 754 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3256 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6271 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53979 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.981140 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43447179 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43447179 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1581625 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1581625 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 974382 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 974382 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 155418 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 155418 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 959842 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 959842 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 64107 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 10951 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332187 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1407245 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 64107 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10951 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 959842 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1487605 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2522505 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 64107 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10951 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 959842 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1487605 # number of overall hits -system.cpu.l2cache.overall_hits::total 2522505 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1494 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1494 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132350 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132350 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16217 # 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number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16217 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 168045 # number of overall misses -system.cpu.l2cache.overall_misses::total 184330 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 55230000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 55230000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16916399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16916399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2173643500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2173643500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9044000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 812500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4836164500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4846021000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 812500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2173643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21752564000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23936064000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9044000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 812500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2173643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21752564000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23936064000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1581625 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1581625 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 974382 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 974382 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1814 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1814 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287768 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287768 # 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number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823594 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823594 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016613 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000548 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125505.771474 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125523.726497 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124044.989639 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119449.087781 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119859.101022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124044.989639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119449.087781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119859.101022 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.566168 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.566168 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188326.250808 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188326.250808 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159296.756763 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159296.756763 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815016 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815016 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.448437 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.448437 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.012545 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.027248 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024665 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.058301 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000874 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000534 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012545 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.097698 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058301 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68689.586115 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68689.586115 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117684.570244 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117684.570244 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 123632.196809 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 123632.196809 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124134.473333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124146.795937 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127967.479675 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125071.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 123632.196809 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119182.561757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119578.158875 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.860863 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.860863 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188047.874624 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188047.874624 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159292.547451 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159292.547451 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5434918 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2706203 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 65803 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 6286174 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3130505 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 100234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1075 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3003914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1730558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 975620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 168030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 976205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1454773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3431921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1776699 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1273398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 245932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 285009 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 285009 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1273972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1585641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 611 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2927884 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146809 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 37703 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 206355 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9318751 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 124907456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207405643 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 858816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5441920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 338613835 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 220482 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3516168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019658 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.160049 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3821192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6291134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 44073 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 438470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 10594869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 163022080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 212667383 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1039232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 11278848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 388007543 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 217979 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3938524 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.178796 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3458199 98.35% 98.35% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 46816 1.33% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 11153 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3847922 97.70% 97.70% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 77931 1.98% 99.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 12671 0.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3516168 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5575385475 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3938524 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 6348684473 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 661286 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 630788 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1466090916 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1913086215 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3066273273 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3138237012 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20730469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 23891458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 107476352 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 224120198 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 212032 # Transaction distribution -system.iobus.trans_dist::ReadResp 212032 # Transaction distribution +system.iobus.trans_dist::ReadReq 212035 # Transaction distribution +system.iobus.trans_dist::ReadResp 212035 # Transaction distribution system.iobus.trans_dist::WriteReq 57756 # Transaction distribution system.iobus.trans_dist::WriteResp 57756 # Transaction distribution -system.iobus.trans_dist::MessageReq 1647 # Transaction distribution -system.iobus.trans_dist::MessageResp 1647 # Transaction distribution +system.iobus.trans_dist::MessageReq 1666 # Transaction distribution +system.iobus.trans_dist::MessageResp 1666 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) @@ -1392,11 +1401,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 542870 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95254 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95254 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 542914 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) @@ -1415,93 +1424,93 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3262814 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3982096 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3262914 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3997256 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10538500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10437000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1023500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 990000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 93500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 32500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 300003000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 300003500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1174500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1177000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 24563000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 24512500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 242078063 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 242091318 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1233000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1227500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50160000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50166000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1666000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.116006 # Cycle average of tags in use +system.iocache.tags.replacements 47572 # number of replacements +system.iocache.tags.tagsinuse 0.366690 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4999354367000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116006 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007250 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007250 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5003383592000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.366690 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.022918 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.022918 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428616 # Number of tag accesses -system.iocache.tags.data_accesses 428616 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.tags.tag_accesses 428643 # Number of tag accesses +system.iocache.tags.data_accesses 428643 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 907 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses -system.iocache.demand_misses::total 904 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses -system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149927198 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149927198 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867794865 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5867794865 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 149927198 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 149927198 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 149927198 # number of overall miss cycles -system.iocache.overall_miss_latency::total 149927198 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses +system.iocache.demand_misses::total 907 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses +system.iocache.overall_misses::total 907 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150838200 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 150838200 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5868267118 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5868267118 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 150838200 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 150838200 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 150838200 # number of overall miss cycles +system.iocache.overall_miss_latency::total 150838200 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1510,40 +1519,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 165848.670354 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125594.924336 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125594.924336 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 165848.670354 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 165848.670354 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 254 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166304.520397 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125605.032491 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125605.032491 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 166304.520397 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166304.520397 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 166304.520397 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 20 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.043478 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.300000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 904 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 904 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 904 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 904 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104727198 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3529874733 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3529874733 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 104727198 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 104727198 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 907 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 907 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 907 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 105488200 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530357439 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3530357439 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 105488200 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105488200 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 105488200 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1552,76 +1561,76 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115848.670354 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75553.825621 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.825621 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 116304.520397 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75564.157513 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75564.157513 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116304.520397 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 116304.520397 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 573476 # Transaction distribution -system.membus.trans_dist::ReadResp 626351 # Transaction distribution -system.membus.trans_dist::WriteReq 13931 # Transaction distribution -system.membus.trans_dist::WriteResp 13931 # Transaction distribution -system.membus.trans_dist::WritebackDirty 148924 # Transaction distribution -system.membus.trans_dist::CleanEvict 10358 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2192 # Transaction distribution -system.membus.trans_dist::UpgradeResp 19 # Transaction distribution -system.membus.trans_dist::ReadExReq 132088 # Transaction distribution -system.membus.trans_dist::ReadExResp 132085 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52881 # Transaction distribution -system.membus.trans_dist::MessageReq 1647 # Transaction distribution -system.membus.trans_dist::MessageResp 1647 # Transaction distribution -system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.trans_dist::ReadResp 628544 # Transaction distribution +system.membus.trans_dist::WriteReq 13974 # Transaction distribution +system.membus.trans_dist::WriteResp 13974 # Transaction distribution +system.membus.trans_dist::WritebackDirty 145215 # Transaction distribution +system.membus.trans_dist::CleanEvict 10528 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2175 # Transaction distribution +system.membus.trans_dist::UpgradeResp 20 # Transaction distribution +system.membus.trans_dist::ReadExReq 127539 # Transaction distribution +system.membus.trans_dist::ReadExResp 127538 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 55679 # Transaction distribution +system.membus.trans_dist::MessageReq 1666 # Transaction distribution +system.membus.trans_dist::MessageResp 1666 # Transaction distribution +system.membus.trans_dist::BadAddressError 611 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730486 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 481353 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1656179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95636 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95636 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1755109 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473091 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 1222 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1649213 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1748187 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460969 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18281344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19970763 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1461141 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17893952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19583543 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22992391 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1583 # Total snoops (count) -system.membus.snoop_fanout::samples 982226 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001677 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040914 # Request fanout histogram +system.membus.pkt_size::total 22605247 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1549 # Total snoops (count) +system.membus.snoop_fanout::samples 976982 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001705 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.041259 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 980579 99.83% 99.83% # Request fanout histogram -system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 975316 99.83% 99.83% # Request fanout histogram +system.membus.snoop_fanout::2 1666 0.17% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 982226 # Request fanout histogram -system.membus.reqLayer0.occupancy 339026000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 976982 # Request fanout histogram +system.membus.reqLayer0.occupancy 338839000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 369109500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 368956000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3981904 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3998744 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1012407982 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 991501459 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 741500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 2334904 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2332744 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2135091502 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2123206000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 4662400 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 4681146 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |